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https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk
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| Rev 11 |
Rev 13 |
| Line 51... |
Line 51... |
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output reg [asz-1:0] cur_rdptr,
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output reg [asz-1:0] cur_rdptr,
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output reg [asz-1:0] com_rdptr,
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output reg [asz-1:0] com_rdptr,
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input [asz-1:0] wrptr,
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input [asz-1:0] wrptr,
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output reg mem_re,
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output reg mem_re,
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input mem_we,
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output reg [asz:0] usage,
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output reg [asz:0] usage,
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output p_srdy,
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output p_srdy,
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input p_drdy,
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input p_drdy,
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| Line 119... |
Line 120... |
tmp_usage = wrptr[asz-1:0] - cur_rdptr[asz-1:0];
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tmp_usage = wrptr[asz-1:0] - cur_rdptr[asz-1:0];
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if (~tmp_usage[asz])
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if (~tmp_usage[asz])
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usage = tmp_usage[asz-1:0];
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usage = tmp_usage[asz-1:0];
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else
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else
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usage = fifo_size - (cur_rdptr[asz-1:0] - wrptr[asz-1:0]);
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usage = fifo_size - (cur_rdptr[asz-1:0] - wrptr[asz-1:0]);
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end
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end // always @ *
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/* -----\/----- EXCLUDED -----\/-----
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// alternate usage calc
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reg [asz-1:0] prev_wr;
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reg [asz:0] usage2, nxt_usage2;
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wire lcl_wr_en;
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//assign lcl_wr_en = (prev_wr0 != wrptr[0]);
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always @(posedge clk)
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begin
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if (reset)
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begin
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/-*AUTORESET*-/
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// Beginning of autoreset for uninitialized flops
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usage2 <= {(1+(asz)){1'b0}};
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// End of automatics
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end
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else
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begin
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usage2 <= #1 nxt_usage2;
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end
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end
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always @*
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begin
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if (mem_re & !mem_we)
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nxt_usage2 = usage2 - 1;
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else if (!mem_re & mem_we)
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nxt_usage2 = usage2 + 1;
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else
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nxt_usage2 = usage2;
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end
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-----/\----- EXCLUDED -----/\----- */
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (reset)
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if (reset)
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cur_rdptr <= `SDLIB_DELAY bound_low;
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cur_rdptr <= `SDLIB_DELAY bound_low;
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