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| Rev 14 |
Rev 16 |
| Line 38... |
Line 38... |
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module sd_fifo_tail_b
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module sd_fifo_tail_b
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#(parameter width=8,
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#(parameter width=8,
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parameter depth=16,
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parameter depth=16,
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parameter commit=0,
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parameter commit=0,
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parameter asz=$clog2(depth))
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parameter asz=$clog2(depth),
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parameter usz=$clog2(depth+1)
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)
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(
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(
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input clk,
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input clk,
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input reset,
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input reset,
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input enable,
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input enable,
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output reg [asz-1:0] com_rdptr,
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output reg [asz-1:0] com_rdptr,
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input [asz-1:0] wrptr,
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input [asz-1:0] wrptr,
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output reg mem_re,
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output reg mem_re,
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input mem_we,
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input mem_we,
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output reg [asz:0] usage,
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output reg [usz:0] p_usage,
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output p_srdy,
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output p_srdy,
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input p_drdy,
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input p_drdy,
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input p_commit,
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input p_commit,
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input p_abort,
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input p_abort,
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reg nxt_irdy;
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reg nxt_irdy;
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reg [width-1:0] hold_a, hold_b;
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reg [width-1:0] hold_a, hold_b;
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reg valid_a, valid_b;
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reg valid_a, valid_b;
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reg prev_re;
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reg prev_re;
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reg [asz:0] tmp_usage;
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reg [usz:0] tmp_usage;
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reg [asz:0] fifo_size;
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reg [usz:0] fifo_size;
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wire rbuf1_drdy;
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wire rbuf1_drdy;
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wire ip_srdy, ip_drdy;
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wire ip_srdy, ip_drdy;
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wire [width-1:0] ip_data;
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wire [width-1:0] ip_data;
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// Stage 1 -- Read pipeline
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// Stage 1 -- Read pipeline
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mem_re = 0;
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mem_re = 0;
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end // else: !if(enable & !empty & (!valid_a | !valid_b |...
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end // else: !if(enable & !empty & (!valid_a | !valid_b |...
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fifo_size = (bound_high - bound_low + 1);
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fifo_size = (bound_high - bound_low + 1);
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tmp_usage = wrptr[asz-1:0] - cur_rdptr[asz-1:0];
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tmp_usage = wrptr[asz-1:0] - cur_rdptr[asz-1:0];
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if (~tmp_usage[asz])
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if (~tmp_usage[usz])
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usage = tmp_usage[asz-1:0];
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p_usage = tmp_usage[usz-1:0];
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else
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else
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usage = fifo_size - (cur_rdptr[asz-1:0] - wrptr[asz-1:0]);
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p_usage = fifo_size - (cur_rdptr[asz-1:0] - wrptr[asz-1:0]);
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end // always @ *
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end // always @ *
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/* -----\/----- EXCLUDED -----\/-----
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/* -----\/----- EXCLUDED -----\/-----
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// alternate usage calc
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// alternate usage calc
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reg [asz-1:0] prev_wr;
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reg [asz-1:0] prev_wr;
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