URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [closure/] [sd_output.v] - Diff between revs 2 and 30

Rev 2	Rev 30
Line 35...	Line 35...
`input p_drdy,`	`input p_drdy,`
`output reg [width-1:0] p_data`	`output reg [width-1:0] p_data`
`);`	`);`

`reg load; // true when data will be loaded into p_data`	`reg load; // true when data will be loaded into p_data`
`reg drain; // true when data will be emptied from p_data`
`reg hold; // true when data will be held in p_data`
`reg nxt_p_srdy;`	`reg nxt_p_srdy;`

`always @*`	`always @*`
`begin`	`begin`
`drain = p_srdy & p_drdy;`	`ic_drdy = p_drdy \| !p_srdy;`
`hold = p_srdy & !p_drdy;`
`ic_drdy = drain \| !p_srdy;`
`load = ic_srdy & ic_drdy;`	`load = ic_srdy & ic_drdy;`
`nxt_p_srdy = load \| hold;`	`nxt_p_srdy = load \| (p_srdy & !p_drdy);`
`end`	`end`

always @(`SDLIB_CLOCKING)	always @(`SDLIB_CLOCKING)
`begin`	`begin`
`if (reset)`	`if (reset)`