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https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk
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| Rev 2 |
Rev 14 |
| Line 34... |
Line 34... |
parameter width=128)
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parameter width=128)
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(input clk,
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(input clk,
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input reset,
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input reset,
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input c_srdy,
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input c_srdy,
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output reg c_drdy,
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//output reg c_drdy,
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output c_drdy,
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input [width-1:0] c_data,
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input [width-1:0] c_data,
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input [mirror-1:0] c_dst_vld,
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input [mirror-1:0] c_dst_vld,
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output reg [mirror-1:0] p_srdy,
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output reg [mirror-1:0] p_srdy,
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input [mirror-1:0] p_drdy,
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input [mirror-1:0] p_drdy,
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| Line 51... |
Line 52... |
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always @(posedge clk)
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always @(posedge clk)
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if (load)
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if (load)
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p_data <= `SDLIB_DELAY c_data;
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p_data <= `SDLIB_DELAY c_data;
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assign c_drdy = (p_srdy == 0);
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always @*
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always @*
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begin
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begin
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nxt_p_srdy = p_srdy;
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nxt_p_srdy = p_srdy;
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nxt_state = state;
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c_drdy = 0;
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load = 0;
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load = 0;
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case (state)
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if (p_srdy == {mirror{1'b0}})
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0 :
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begin
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begin
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c_drdy = 1'b1;
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if (c_srdy)
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if (c_srdy)
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begin
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begin
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if (c_dst_vld == {mirror{1'b0}})
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if (c_dst_vld == {mirror{1'b0}})
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nxt_p_srdy = {mirror{1'b1}};
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nxt_p_srdy = {mirror{1'b1}};
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else
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else
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nxt_p_srdy = c_dst_vld;
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nxt_p_srdy = c_dst_vld;
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nxt_state = 1;
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load = 1;
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load = 1;
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end
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end
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end
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end
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else
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1 :
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begin
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begin
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nxt_p_srdy = p_srdy & ~p_drdy;
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nxt_p_srdy = p_srdy & ~p_drdy;
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if (p_srdy == {mirror{1'b0}})
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begin
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nxt_state = 1'b0;
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end
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end
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end
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endcase
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end
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end
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always @(`SDLIB_CLOCKING)
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always @(`SDLIB_CLOCKING)
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begin
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begin
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if (reset)
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if (reset)
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