| Line 12... |
Line 12... |
// turn due to flow control.
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// turn due to flow control.
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// Mode 1 : Each input can transmit for as long as it has data.
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// Mode 1 : Each input can transmit for as long as it has data.
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// When input deasserts, device will begin to hunt for a
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// When input deasserts, device will begin to hunt for a
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// new input with data.
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// new input with data.
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// Mode 2 : Continue to accept input until the incoming data
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// Mode 2 : Continue to accept input until the incoming data
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// matches a particular "end pattern". The trigger pattern
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// matches a particular "end pattern". The end pattern
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// is when (c_data & eod_mask) == eod_pattern. Once
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// is provided on the c_rearb (re-arbitrate) input. When
|
// trigger pattern is seen, begin hunting for new input.
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// c_rearb is high, will hunt for new inputs on next clock.
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//
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//
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// This component also supports two arbitration modes: slow and fast.
|
// This component also supports two arbitration modes: slow and fast.
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// slow rotates the grant from requestor to requestor cycle by cycle,
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// slow rotates the grant from requestor to requestor cycle by cycle,
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// so each requestor gets serviced at most once every #inputs cycles.
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// so each requestor gets serviced at most once every #inputs cycles.
|
// This can be useful for producing a TDM-type interface, however
|
// This can be useful for producing a TDM-type interface, however
|
| Line 49... |
Line 49... |
|
|
module sd_rrmux
|
module sd_rrmux
|
#(parameter width=8,
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#(parameter width=8,
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parameter inputs=2,
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parameter inputs=2,
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parameter mode=0,
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parameter mode=0,
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parameter eod_pattern=0,
|
|
parameter eod_mask=0,
|
|
parameter fast_arb=0)
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parameter fast_arb=0)
|
(
|
(
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input clk,
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input clk,
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input reset,
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input reset,
|
|
|
input [(width*inputs)-1:0] c_data,
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input [(width*inputs)-1:0] c_data,
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input [inputs-1:0] c_srdy,
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input [inputs-1:0] c_srdy,
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output [inputs-1:0] c_drdy,
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output [inputs-1:0] c_drdy,
|
|
input c_rearb, // for use with mode 2 only
|
|
|
output reg [width-1:0] p_data,
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output reg [width-1:0] p_data,
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output [inputs-1:0] p_grant,
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output [inputs-1:0] p_grant,
|
output reg p_srdy,
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output reg p_srdy,
|
input p_drdy
|
input p_drdy
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| Line 75... |
Line 74... |
|
|
wire [width-1:0] rr_mux_grid [0:inputs-1];
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wire [width-1:0] rr_mux_grid [0:inputs-1];
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reg rr_locked;
|
reg rr_locked;
|
genvar i;
|
genvar i;
|
integer j;
|
integer j;
|
wire trig_pattern;
|
|
|
|
assign c_drdy = rr_state & {inputs{p_drdy}};
|
assign c_drdy = rr_state & {inputs{p_drdy}};
|
assign p_grant = rr_state;
|
assign p_grant = rr_state;
|
|
|
function [inputs-1:0] nxt_grant;
|
function [inputs-1:0] nxt_grant;
|
| Line 106... |
Line 104... |
|
|
if (mode == 2)
|
if (mode == 2)
|
begin : tp_gen
|
begin : tp_gen
|
reg nxt_rr_locked;
|
reg nxt_rr_locked;
|
|
|
assign trig_pattern = (rr_mux_grid[data_ind] & eod_mask) == eod_pattern;
|
|
always @*
|
always @*
|
begin
|
begin
|
data_ind = 0;
|
data_ind = 0;
|
for (j=0; j<inputs; j=j+1)
|
for (j=0; j<inputs; j=j+1)
|
if (rr_state[j])
|
if (rr_state[j])
|
| Line 118... |
Line 115... |
|
|
nxt_rr_locked = rr_locked;
|
nxt_rr_locked = rr_locked;
|
|
|
if ((c_srdy & rr_state) & (!rr_locked))
|
if ((c_srdy & rr_state) & (!rr_locked))
|
nxt_rr_locked = 1;
|
nxt_rr_locked = 1;
|
else if ((c_srdy & rr_state) & p_drdy & trig_pattern )
|
else if ((c_srdy & rr_state & c_rearb) & p_drdy )
|
nxt_rr_locked = 0;
|
nxt_rr_locked = 0;
|
end
|
end
|
|
|
always @(`SDLIB_CLOCKING)
|
always @(`SDLIB_CLOCKING)
|
begin
|
begin
|
| Line 130... |
Line 127... |
rr_locked <= `SDLIB_DELAY 0;
|
rr_locked <= `SDLIB_DELAY 0;
|
else
|
else
|
rr_locked <= `SDLIB_DELAY nxt_rr_locked;
|
rr_locked <= `SDLIB_DELAY nxt_rr_locked;
|
end
|
end
|
end // block: tp_gen
|
end // block: tp_gen
|
else
|
|
begin : ntp_gen
|
|
assign trig_pattern = 1'b0;
|
|
end
|
|
endgenerate
|
endgenerate
|
|
|
always @*
|
always @*
|
begin
|
begin
|
p_data = 0;
|
p_data = 0;
|
