URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [forks/] [sd_rrmux.v] - Diff between revs 24 and 29

Rev 24	Rev 29
Line 48...	Line 48...
`endif	`endif

`module sd_rrmux`	`module sd_rrmux`
`#(parameter width=8,`	`#(parameter width=8,`
`parameter inputs=2,`	`parameter inputs=2,`
	`parameter inputs_asz=1, // log2(inputs)`
`parameter mode=0,`	`parameter mode=0,`
`parameter fast_arb=0)`	`parameter fast_arb=0)`
`(`	`(`
`input clk,`	`input clk,`
`input reset,`	`input reset,`
Line 68...	Line 69...
`);`	`);`

`reg [inputs-1:0] rr_state;`	`reg [inputs-1:0] rr_state;`
`reg [inputs-1:0] nxt_rr_state;`	`reg [inputs-1:0] nxt_rr_state;`

`reg [$clog2(inputs)-1:0] data_ind;`

`wire [width-1:0] rr_mux_grid [0:inputs-1];`	`wire [width-1:0] rr_mux_grid [0:inputs-1];`
`reg rr_locked;`	`reg rr_locked;`
`genvar i;`	`genvar i;`
`integer j;`	`integer j;`

Line 103...	Line 102...
`end`	`end`

`if (mode == 2)`	`if (mode == 2)`
`begin : tp_gen`	`begin : tp_gen`
`reg nxt_rr_locked;`	`reg nxt_rr_locked;`
	`reg selected_srdy;`

`always @*`	`always @*`
`begin`	`begin`
`data_ind = 0;`	`if (c_rearb)`
`for (j=0; j<inputs; j=j+1)`
`if (rr_state[j])`
`data_ind = j;`

`nxt_rr_locked = rr_locked;`

`if ((c_srdy & rr_state) & (!rr_locked))`
`nxt_rr_locked = 1;`
`else if ((c_srdy & rr_state & c_rearb) & p_drdy )`
`nxt_rr_locked = 0;`	`nxt_rr_locked = 0;`
	`else if ((nxt_rr_state != rr_state) && (nxt_rr_state != 0))`
	`nxt_rr_locked = 1;`
	`else`
	`nxt_rr_locked = rr_locked;`
`end`	`end`

always @(`SDLIB_CLOCKING)	always @(`SDLIB_CLOCKING)
`begin`	`begin`
`if (reset)`	`if (reset)`