| Line 8... |
Line 8... |
// Mode 0 : Each input gets a single cycle, regardless of data
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// Mode 0 : Each input gets a single cycle, regardless of data
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// availability. This mode functions like a TDM
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// availability. This mode functions like a TDM
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// demultiplexer. Output flow control will cause the
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// demultiplexer. Output flow control will cause the
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// component to stall, so that inputs do not miss their
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// component to stall, so that inputs do not miss their
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// turn due to flow control.
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// turn due to flow control.
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// Mode 0 fast arb : Each input gets a single grant. If the
|
|
// output is not ready (p_drdy deasserted), then the
|
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// machine will hold on that particular input until it
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// receives a grant. Once a single token has been
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// accepted the machine will round-robin arbitrate.
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// When there are no requests the machine returns to
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// its default state.
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// Mode 1 : Each input can transmit for as long as it has data.
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// Mode 1 : Each input can transmit for as long as it has data.
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// When input deasserts, device will begin to hunt for a
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// When input deasserts, device will begin to hunt for a
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// new input with data.
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// new input with data.
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// Mode 2 : Continue to accept input until the incoming data
|
// Mode 2 : Continue to accept input until the incoming data
|
// matches a particular "end pattern". The end pattern
|
// matches a particular "end pattern". The end pattern
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| Line 60... |
Line 67... |
input [(width*inputs)-1:0] c_data,
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input [(width*inputs)-1:0] c_data,
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input [inputs-1:0] c_srdy,
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input [inputs-1:0] c_srdy,
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output [inputs-1:0] c_drdy,
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output [inputs-1:0] c_drdy,
|
input c_rearb, // for use with mode 2 only
|
input c_rearb, // for use with mode 2 only
|
|
|
output reg [width-1:0] p_data,
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output [width-1:0] p_data,
|
output [inputs-1:0] p_grant,
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output [inputs-1:0] p_grant,
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output reg p_srdy,
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output p_srdy,
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input p_drdy
|
input p_drdy
|
);
|
);
|
|
|
reg [inputs-1:0] rr_state;
|
reg [inputs-1:0] rr_state;
|
reg [inputs-1:0] nxt_rr_state;
|
reg [inputs-1:0] nxt_rr_state;
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|
|
wire [width-1:0] rr_mux_grid [0:inputs-1];
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//wire [width-1:0] rr_mux_grid [0:inputs-1];
|
reg rr_locked;
|
reg rr_locked;
|
genvar i;
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//genvar i;
|
integer j;
|
integer j;
|
|
|
assign c_drdy = rr_state & {inputs{p_drdy}};
|
assign c_drdy = rr_state & {inputs{p_drdy}};
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assign p_grant = rr_state;
|
assign p_grant = rr_state;
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|
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| Line 93... |
Line 100... |
else
|
else
|
nxt_grant = cur_req & (~cur_req + 1);
|
nxt_grant = cur_req & (~cur_req + 1);
|
end
|
end
|
endfunction
|
endfunction
|
|
|
generate
|
always @*
|
for (i=0; i<inputs; i=i+1)
|
begin
|
begin : grid_assign
|
data_ind = 0;
|
assign rr_mux_grid[i] = c_data >> (i*width);
|
for (j=0; j<inputs; j=j+1)
|
|
if (rr_state[j])
|
|
data_ind = j;
|
end
|
end
|
|
|
|
generate
|
|
/* -----\/----- EXCLUDED -----\/-----
|
|
for (i=0; i<inputs; i=i+1)
|
|
begin : grid_assign
|
|
wire [width-1:0] temp;
|
|
assign temp = c_data >> (i*width);
|
|
assign rr_mux_grid[i] = c_data >> (i*width);
|
|
end
|
|
-----/\----- EXCLUDED -----/\----- */
|
|
|
if (mode == 2)
|
if (mode == 2)
|
begin : tp_gen
|
begin : tp_gen
|
reg nxt_rr_locked;
|
reg nxt_rr_locked;
|
reg selected_srdy;
|
reg selected_srdy;
|
|
|
always @*
|
always @*
|
begin
|
begin
|
if (c_rearb)
|
/* -----\/----- EXCLUDED -----\/-----
|
|
data_ind = 0;
|
|
for (j=0; j<inputs; j=j+1)
|
|
if (rr_state[j])
|
|
data_ind = j;
|
|
-----/\----- EXCLUDED -----/\----- */
|
|
|
|
nxt_rr_locked = rr_locked;
|
|
|
|
if ((c_srdy & rr_state) & (!rr_locked))
|
|
nxt_rr_locked = 1;
|
|
else if ((c_srdy & rr_state & c_rearb) & p_drdy )
|
nxt_rr_locked = 0;
|
nxt_rr_locked = 0;
|
else if ((nxt_rr_state != rr_state) && (nxt_rr_state != 0))
|
else if ((nxt_rr_state != rr_state) && (nxt_rr_state != 0))
|
nxt_rr_locked = 1;
|
nxt_rr_locked = 1;
|
else
|
else
|
nxt_rr_locked = rr_locked;
|
nxt_rr_locked = rr_locked;
|
| Line 124... |
Line 154... |
rr_locked <= `SDLIB_DELAY nxt_rr_locked;
|
rr_locked <= `SDLIB_DELAY nxt_rr_locked;
|
end
|
end
|
end // block: tp_gen
|
end // block: tp_gen
|
endgenerate
|
endgenerate
|
|
|
always @*
|
assign p_srdy = |(rr_state & c_srdy);
|
begin
|
assign p_data = c_data[data_ind*width +: width];
|
p_data = 0;
|
|
p_srdy = 0;
|
|
for (j=0; j<inputs; j=j+1)
|
|
if (rr_state[j])
|
|
begin
|
|
p_data = rr_mux_grid[j];
|
|
p_srdy = c_srdy[j];
|
|
end
|
|
end
|
|
|
|
always @*
|
always @*
|
begin
|
begin
|
if ((mode == 1) & (c_srdy & rr_state))
|
if ((mode == 1) & (c_srdy & rr_state))
|
nxt_rr_state = rr_state;
|
nxt_rr_state = rr_state;
|
else if ((mode == 0) & !p_drdy)
|
else if ((mode == 0) && !p_drdy && !fast_arb)
|
|
nxt_rr_state = rr_state;
|
|
else if ((mode == 0) && |(rr_state & c_srdy) && !p_drdy && fast_arb)
|
nxt_rr_state = rr_state;
|
nxt_rr_state = rr_state;
|
else if ((mode == 2) & (rr_locked | (c_srdy & rr_state)))
|
else if ((mode == 2) & (rr_locked | (c_srdy & rr_state)))
|
nxt_rr_state = rr_state;
|
nxt_rr_state = rr_state;
|
else if (fast_arb)
|
else if (fast_arb)
|
nxt_rr_state = nxt_grant (rr_state, c_srdy);
|
nxt_rr_state = nxt_grant (rr_state, c_srdy);
|
| Line 153... |
Line 176... |
end
|
end
|
|
|
always @(`SDLIB_CLOCKING)
|
always @(`SDLIB_CLOCKING)
|
begin
|
begin
|
if (reset)
|
if (reset)
|
rr_state <= `SDLIB_DELAY 1;
|
rr_state <= `SDLIB_DELAY (fast_arb)? 0 : 1;
|
else
|
else
|
rr_state <= `SDLIB_DELAY nxt_rr_state;
|
rr_state <= `SDLIB_DELAY nxt_rr_state;
|
end
|
end
|
|
|
endmodule // sd_rrmux
|
endmodule // sd_rrmux
|
