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https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk
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| Line 36... |
Line 36... |
end
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end
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end // always @ (posedge clk)
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end // always @ (posedge clk)
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assign d_out = array[r_addr];
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assign d_out = array[r_addr];
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`ifndef verilator
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genvar g;
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genvar g;
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generate
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generate
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for (g=0; g<depth; g=g+1)
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for (g=0; g<depth; g=g+1)
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begin : breakout
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begin : breakout
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wire [width-1:0] brk;
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wire [width-1:0] brk;
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assign brk=array[g];
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assign brk=array[g];
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end
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end
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endgenerate
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endgenerate
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`endif
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endmodule
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endmodule
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