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// ------------------------- CONFIDENTIAL ------------------------------------
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright 2008-2011 by Michael A. Morris, dba M. A. Morris & Associates
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// Copyright 2008-2013 by Michael A. Morris, dba M. A. Morris & Associates
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//
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//
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// All rights reserved. No part of this source code may be reproduced or
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// All rights reserved. The source code contained herein is publicly released
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// transmitted in any form or by any means, electronic or mechanical,
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// under the terms and conditions of the GNU Lesser Public License. No part of
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// including photocopying, recording, or any information storage and
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// this source code may be reproduced or transmitted in any form or by any
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// retrieval system, without permission in writing from Michael A. Morris,
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// means, electronic or mechanical, including photocopying, recording, or any
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// dba M. A. Morris & Associates.
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// information storage and retrieval system in violation of the license under
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// which the source code is released.
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//
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// The source code contained herein is free; it may be redistributed and/or
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// modified in accordance with the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either version 2.1 of
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// the GNU Lesser General Public License, or any later version.
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//
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// The source code contained herein is freely released WITHOUT ANY WARRANTY;
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// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
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// more details.)
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//
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// A copy of the GNU Lesser General Public License should have been received
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// along with the source code contained herein; if not, a copy can be obtained
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// by writing to:
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//
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// Free Software Foundation, Inc.
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// 51 Franklin Street, Fifth Floor
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// Boston, MA 02110-1301 USA
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//
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//
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// Further, no use of this source code is permitted in any form or means
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// Further, no use of this source code is permitted in any form or means
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// without a valid, written license agreement with Michael A. Morris, dba
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// without inclusion of this banner prominently in any derived works.
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// M. A. Morris & Associates.
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//
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//
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// Michael A. Morris
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// Michael A. Morris
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// dba M. A. Morris & Associates
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// Huntsville, AL
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// 164 Raleigh Way
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// Huntsville, AL 35811, USA
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// Ph. +1 256 508 5869
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//
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// Licensed To: DopplerTech, Inc. (DTI)
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// 9345 E. South Frontage Rd.
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// Yuma, AZ 85365
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//
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//
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// ----------------------------------------------------------------------------
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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// Company: M. A. Morris & Associates
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// Company: M. A. Morris & Associates
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// Engineer: Michael A. Morris
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// Engineer: Michael A. Morris
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//
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//
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// Create Date: 07:33 05/10/2008
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// Create Date: 07:33 05/10/2008
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// Design Name: LTAS
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// Design Name: Synchronous Serial Peripheral (SSP) Interface UART
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// Module Name: C:/XProjects/ISE10.1i/LTAS/LTAS_Top.v
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// Module Name: ../VerilogCoponentsLib/SSP_UART/SSPx_Slv.v
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// Project Name: LTAS
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// Project Name: Verilog Components Library
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// Target Devices: XC3S700AN-5FFG484I
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// Target Devices: XC3S50A-4VQG100I, XC3S20A-4VQG100I, XC3S700AN-4FFG484I
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// Tool versions: ISE 10.1i SP3
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// Tool versions: ISE 10.1i SP3
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//
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//
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// Description:
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// Description:
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//
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//
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// This module implements a full-duplex (Slave) SSP interface for 16-bit
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// This module implements a full-duplex (Slave) SSP interface for 16-bit
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// 2.00 11B06 MAM Modified the interface to separate RA[3:1] and
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// 2.00 11B06 MAM Modified the interface to separate RA[3:1] and
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// RA[0] into RA[2:0] address port and a WnR command
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// RA[0] into RA[2:0] address port and a WnR command
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// port. This makes the operation of the SSP/SPI I/F
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// port. This makes the operation of the SSP/SPI I/F
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// more clear.
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// more clear.
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//
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//
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// 2.10 13G06 MAM Changed the asynchronous reset generated by ~SSEL.
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// Previously, a number of internal circuits were
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// reset asynchronously on system reset, Rst, or ~SSEL.
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// Added a FF, clocked on posedge SCK, that is asyn-
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// chronously reset as before, but synchronously de-
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// asserts on first rising edge of SCK. This signal,
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// SSP_Rst, is used to asynchronously reset the same
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// circuits as before: BC, EOC, and RDI. SPI Modes 0 or
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// 3 are still supported.
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//
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// 2.20 14D25 MAM Encountered an issue whereby RA[2] held in reset
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// after SSEL deasserted and then reasserted. The
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// asynchronous reset on the signal SSP_Rst, a FF
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// clocked on the falling edge of SCK, was changed to
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// the combinatorial signal Rst_SSP. Rst_SSP is the
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// source of the asynchronous reset of the SSP_Rst FF.
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// The additional delay in the SSP_Rst signal caused
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// RA[2] to be kept in reset at the start of a new
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// SSP transfer cycle. Also added two additional CE
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// signals while tracking down this issue: CE_RA and
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// CE_WnR. They were previously driven directly by the
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// bit counter.
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//
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//
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// Additional Comments:
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// Additional Comments:
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module SSPx_Slv(
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module SSPx_Slv(
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input Rst, // System Reset
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input Rst, // System Reset
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//
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//
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input SSEL, // Slave Select
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input SSEL, // Slave Select
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//
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//
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reg [15:1] RDI; // Serial Input Shift Register
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reg [15:1] RDI; // Serial Input Shift Register
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reg [11:0] rDO; // output data register
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reg [11:0] rDO; // output data register
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reg SSP_Rst;
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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// Implementation
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// Implementation
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//
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//
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// Module Reset - asynchronous because SCK not continuous
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// Module Reset - asynchronous because SCK not continuous
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assign Rst_SSP = (Rst | ~SSEL);
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assign Rst_SSP = (Rst | ~SSEL);
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always @(posedge SCK or posedge Rst_SSP)
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begin
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if(Rst_SSP)
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SSP_Rst <= #1 ~0;
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else
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SSP_Rst <= #1 0;
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end
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// Bit Counter, count from 0 to 15
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// Bit Counter, count from 0 to 15
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// Clock on negedge SCK to align MISO in bit cell
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// Clock on negedge SCK to align MISO in bit cell
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always @(negedge SCK or posedge Rst_SSP)
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always @(negedge SCK or posedge SSP_Rst)
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begin
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begin
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if(Rst_SSP)
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if(SSP_Rst)
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BC <= #1 4'd0;
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BC <= #1 4'd0;
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else
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else
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BC <= #1 (BC + 1);
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BC <= #1 (BC + 1);
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end
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end
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// End-Of-Cycle, asserted during last bit of transfer (bit 15)
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// End-Of-Cycle, asserted during last bit of transfer (bit 15)
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// Clock on negedge SCK to center rising edge in bit cell
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// Clock on negedge SCK to center rising edge in bit cell
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always @(negedge SCK or posedge Rst_SSP)
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always @(negedge SCK or posedge SSP_Rst)
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begin
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begin
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if(Rst_SSP)
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if(SSP_Rst)
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EOC <= #1 1'b0;
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EOC <= #1 1'b0;
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else
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else
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EOC <= #1 (BC == 14);
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EOC <= #1 (BC == 14);
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end
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end
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4'b1010 : RDI[ 5] <= #1 MOSI;
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4'b1010 : RDI[ 5] <= #1 MOSI;
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4'b1011 : RDI[ 4] <= #1 MOSI;
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4'b1011 : RDI[ 4] <= #1 MOSI;
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4'b1100 : RDI[ 3] <= #1 MOSI;
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4'b1100 : RDI[ 3] <= #1 MOSI;
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4'b1101 : RDI[ 2] <= #1 MOSI;
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4'b1101 : RDI[ 2] <= #1 MOSI;
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4'b1110 : RDI[ 1] <= #1 MOSI;
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4'b1110 : RDI[ 1] <= #1 MOSI;
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default : RDI <= #1 RDI;
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endcase
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endcase
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end
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end
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// Assign RA, WnR, and DI bus from RDI and MOSI
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// Assign RA, WnR, and DI bus from RDI and MOSI
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//always @(posedge SCK or posedge Rst)
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assign CE_RA = (BC == 2);
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//begin
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// if(Rst)
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// RA <= #1 0;
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// else if(BC == 2)
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// RA <= #1 {RDI[15:14], MOSI};
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//end
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//
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//always @(posedge SCK or posedge Rst)
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//begin
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// if(Rst)
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// WnR <= #1 0;
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// else if(BC == 3)
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// WnR <= #1 MOSI;
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//end
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always @(negedge SCK or posedge Rst)
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always @(negedge SCK or posedge Rst_SSP)
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begin
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begin
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if(Rst)
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if(Rst_SSP)
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RA <= #1 0;
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RA <= #1 0;
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else if(BC == 2)
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else if(CE_RA)
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RA <= #1 RDI[15:13];
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RA <= #1 RDI[15:13];
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end
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end
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always @(negedge SCK or posedge Rst)
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assign CE_WnR = (BC == 3);
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always @(negedge SCK or posedge Rst_SSP)
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begin
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begin
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if(Rst)
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if(Rst_SSP)
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WnR <= #1 0;
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WnR <= #1 0;
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else if(EOC)
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else if(EOC)
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WnR <= #1 0;
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WnR <= #1 0;
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else if(BC == 3)
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else if(CE_WnR)
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WnR <= #1 RDI[12];
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WnR <= #1 RDI[12];
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end
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end
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always @(posedge SCK or posedge Rst)
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always @(*) DI <= {RDI[11:1], MOSI};
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begin
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if(Rst)
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DI <= #1 0;
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else if(EOC)
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DI <= #1 {RDI[11:1], MOSI};
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end
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always @(negedge SCK or posedge Rst)
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always @(negedge SCK or posedge Rst)
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begin
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begin
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if(Rst)
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if(Rst)
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rDO <= #1 0;
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rDO <= #1 0;
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rDO <= #1 DO;
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rDO <= #1 DO;
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end
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end
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// Generate MISO: multiplex MOSI and DO using En and BC
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// Generate MISO: multiplex MOSI and DO using En and BC
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always @(BC or rDO or MOSI)
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always @(*)
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begin
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begin
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case(BC)
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case(BC)
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4'b0000 : MISO <= MOSI;
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4'b0000 : MISO <= MOSI;
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4'b0001 : MISO <= MOSI;
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4'b0001 : MISO <= MOSI;
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4'b0010 : MISO <= MOSI;
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4'b0010 : MISO <= MOSI;
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