OpenCores
URL https://opencores.org/ocsvn/sv_dir_tb/sv_dir_tb/trunk

Subversion Repositories sv_dir_tb

[/] [sv_dir_tb/] [trunk/] [tb_gen/] [tb_mod_template.sv] - Diff between revs 2 and 6

Only display areas with differences | Details | Blame | View Log

Rev 2 Rev 6
/////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////
//   Copyright  2014 Ken Campbell
//   Copyright  2014 Ken Campbell
//
//
//   Licensed under the Apache License, Version 2.0 (the "License");
//   Licensed under the Apache License, Version 2.0 (the "License");
//   you may not use this file except in compliance with the License.
//   you may not use this file except in compliance with the License.
//   You may obtain a copy of the License at
//   You may obtain a copy of the License at
//
//
//     http://www.apache.org/licenses/LICENSE-2.0
//     http://www.apache.org/licenses/LICENSE-2.0
//
//
//   Unless required by applicable law or agreed to in writing, software
//   Unless required by applicable law or agreed to in writing, software
//   distributed under the License is distributed on an "AS IS" BASIS,
//   distributed under the License is distributed on an "AS IS" BASIS,
//   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//   See the License for the specific language governing permissions and
//   See the License for the specific language governing permissions and
//   limitations under the License.
//   limitations under the License.
//
//
//   test bench module file  template.
//   test bench module file  template.
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
>>header
>>header
//  The package.
//  The package.
  `include "../sv/tb_pkg.sv"
  `include "../sv/tb_pkg.sv"
module tb_mod (dut_if.tb_conn tif);
module tb_mod (dut_if.tb_conn tif);
  import tb_pkg::*;
  import tb_pkg::*;
 
  //  some handy defs
 
  `define PAR1 r.rtn_val.par1
 
  `define PAR2 r.rtn_val.par2
 
  `define PAR3 r.rtn_val.par3
 
  `define PAR4 r.rtn_val.par4
  //  package and container
  //  package and container
  cmd_lst  cmds;
  cmd_lst  cmds;
  tb_trans r;
  tb_trans r;
  integer  in_fh;
  integer  in_fh;
  integer  stat;
  integer  stat;
  logic    clock;
  logic    clock;
  //////////////////////////////////////////////
  //////////////////////////////////////////////
  //   DUT signals
  //   DUT signals
>>insert sigs
>>insert sigs
  ////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////
  //  drive DUT  signals through interface
  //  drive DUT  signals through interface
>>drive sigs
>>drive sigs
  ////////////////////////////////////////////////////
  ////////////////////////////////////////////////////
  //  instruction variables
  //  instruction variables
  integer  was_def     = 0;
  integer  was_def     = 0;
  string   cmd_string;
  string   cmd_string;
  logic  [31:0]  tmp_vec;
  logic  [31:0]  tmp_vec;
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  //   clock driver
  //   clock driver
  initial begin
  initial begin
    while(1) begin
    while(1) begin
      #10 clock = 0;
      #10 clock = 0;
      #10 clock = 1;
      #10 clock = 1;
    end
    end
  end
  end
  //////////////////////////////////////////////////////////
  //////////////////////////////////////////////////////////
  //  stimulus_file processing
  //  stimulus_file processing
  initial begin : Process_STM
  initial begin : Process_STM
    cmds = new();
    cmds = new();
    r    = new();
    r    = new();
    //  define the default instructions
    //  define the default instructions
    cmds.define_defaults();
    cmds.define_defaults();
    //  User instructions
    //  User instructions
    cmds.define_instruction("RESET", 0);
    cmds.define_instruction("RESET", 0);
    //cmds.define_instruction("READ", 1);
    //cmds.define_instruction("READ", 1);
    //cmds.define_instruction("WRITE", 2);
    //cmds.define_instruction("WRITE", 2);
    //cmds.define_instruction("VERIFY", 1);
    //cmds.define_instruction("VERIFY", 1);
    //  load the stimulus file
    //  load the stimulus file
    cmds.load_stm(`STM_FILE);
    cmds.load_stm(tb_top.STM_FILE);
 
 
    r.cmd = cmds;
    r.cmd = cmds;
    /////////////////////////////////////////////////////
    /////////////////////////////////////////////////////
    //  the main loop.
    //  the main loop.
    while (r.cmd != null) begin
    while (r.cmd != null) begin
      r      = r.cmd.get(r);
      r      = r.cmd.get(r);
      r.next++;
      r.next++;
      //  process default instructions
      //  process default instructions
      was_def  =  r.cmd.exec_defaults(r);
      was_def  =  r.cmd.exec_defaults(r);
      if(was_def) begin
      if(was_def) begin
        continue;
        continue;
      end
      end
      ///////////////////////////////////////////////////////
      ///////////////////////////////////////////////////////
      //   Process User  instructions.
      //   Process User  instructions.
      // get the command string
      // get the command string
      cmd_string = r.cmd.lst_cmds.cmd;
      cmd_string = r.cmd.lst_cmds.cmd;
      //  output the dynamic text if there is some. (Note:  before command runs.)
      //  output the dynamic text if there is some. (Note:  before command runs.)
      r.cmd.print_str_wvar();
      r.cmd.print_str_wvar();
      ///////////////////////////////////////////////////////////////////////////
      ///////////////////////////////////////////////////////////////////////////
      //  RESET
      //  RESET
      if (cmd_string == "RESET") begin
      if (cmd_string == "RESET") begin
        @(posedge clock)
        @(posedge clock);
      ///////////////////////////////////////////////////////////////////////////
      ///////////////////////////////////////////////////////////////////////////
      //  READ
      //  READ
      //end else if (cmd_string == "READ") begin
      //end else if (cmd_string == "READ") begin
      //  @(posedge clock)
      //  @(posedge clock)
      ///////////////////////////////////////////////////////////////////////////
      ///////////////////////////////////////////////////////////////////////////
      //  WRITE
      //  WRITE
      //end else if (cmd_string == "WRITE") begin
      //end else if (cmd_string == "WRITE") begin
      //////////////////////////////////////////////////////////////////////////
      //////////////////////////////////////////////////////////////////////////
      //  VERIFY
      //  VERIFY
      //end else if (cmd_string == "VERIFY") begin
      //end else if (cmd_string == "VERIFY") begin
      //  verify_command : assert (tmp_vec == r.rtn_val.par1) else begin
      //  verify_command : assert (tmp_vec == r.rtn_val.par1) else begin
      //    $fatal(0,"VERIFY failed expected: %x  Got: %x", r.rtn_val.par1, tmp_vec);
      //    $fatal(0,"VERIFY failed expected: %x  Got: %x", r.rtn_val.par1, tmp_vec);
      //  end
      //  end
      end else begin
      end else begin
        $display("ERROR:  Command not found in the else if chain. Is it spelled correctly in the else if?");
        $display("ERROR:  Command not found in the else if chain. Is it spelled correctly in the else if?");
      end //  end of else if chain
      end //  end of else if chain
    end  //  end main while loop
    end  //  end main while loop
    //  should never end up outside the while loop.
    //  should never end up outside the while loop.
    $display("ERROR:  Some how, a run off the beginning or end of the instruction sequence, has not been caught!!");
    $display("ERROR:  Some how, a run off the beginning or end of the instruction sequence, has not been caught!!");
  end   //  end Process_STM
  end   //  end Process_STM
endmodule // tb_mod
endmodule // tb_mod
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.