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/* *****************************************************************************
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* title: uart_16550_rll module *
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* description: RS232 Protocol 16550D uart (mostly supported) *
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* languages: systemVerilog *
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* *
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* Copyright (C) 2010 miyagi.hiroshi *
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* *
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* This library is free software; you can redistribute it and/or *
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* modify it under the terms of the GNU Lesser General Public *
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* License as published by the Free Software Foundation; either *
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* version 2.1 of the License, or (at your option) any later version. *
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* *
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* This library is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
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* Lesser General Public License for more details. *
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* *
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* You should have received a copy of the GNU Lesser General Public *
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* License along with this library; if not, write to the Free Software *
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
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* *
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* *** GNU LESSER GENERAL PUBLIC LICENSE *** *
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* from http://www.gnu.org/licenses/lgpl.txt *
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*****************************************************************************
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* redleaflogic,ltd *
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* miyagi.hiroshi@redleaflogic.biz *
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* $Id: uart_interface_be.sv 108 2010-03-30 02:56:26Z hiroshi $ *
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***************************************************************************** */
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`ifdef SYN
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/* empty */
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`else
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timeunit 1ps ;
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timeprecision 1ps ;
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`endif
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import uart_top_package:: * ;
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interface wb_ext_bus() ;
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wire clk_i ; // clock
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wire nrst_i ; // reset
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wire [15:0] adr_i ; // address
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wire [31:0] dat_i ; // data input
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wire [31:0] dat_o ; // clk_rst_manager
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wire we_i ; // write enable
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wire [3:0] sel_i ; // select
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wire stb_i ; //
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wire ack_o ; // acknowledge accept
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wire cyc_i ; // cycle assrted
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wire intr_o ; //
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modport master_mp(
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output clk_i, nrst_i, adr_i, dat_i, we_i, sel_i, cyc_i, stb_i,
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input dat_o, ack_o, intr_o
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) ;
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modport slave_mp(
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input clk_i, nrst_i, adr_i, dat_i, we_i, sel_i, stb_i, cyc_i,
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output dat_o, ack_o, intr_o) ;
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logic [31:0] bw_data ;
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logic [4:0] b_addr ;
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logic cs3, we ;
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logic [3:0] be ;
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assign adr_i = b_addr ;
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assign dat_i = we == 1'b1 ? bw_data : 'hx ;
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assign stb_i = cs3 ;
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assign cyc_i = cs3 ;
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assign we_i = we ;
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assign sel_i = be ;
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assign clk_b = clk_i ;
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initial begin
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bw_data = 0 ;
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b_addr = 0;
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cs3 = 1'b0 ;
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we = 1'b0 ;
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be = 4'b0000 ;
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end
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task write(
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input logic [31:0] wdat,
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input logic [4:0] adr
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) ;
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@(posedge clk_b) ;
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#(STEP*0.1) ;
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b_addr = adr ;
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cs3 = 1'b1 ;
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@(posedge clk_b) ;
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#(STEP*0.1) ;
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bw_data = wdat ;
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we = 1'b1 ;
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`ifdef ALIGN_4B
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be = 4'b1111 ;
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`else
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be[0] = adr[1:0] == 2'b00 ;
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be[1] = adr[1:0] == 2'b01 ;
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be[2] = adr[1:0] == 2'b10 ;
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be[3] = adr[1:0] == 2'b11 ;
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`endif
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@(posedge clk_b) ;
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#(STEP*0.1) ;
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cs3 = 1'b0 ;
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we = 1'b0 ;
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be = 4'b0000 ;
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b_addr = 'hx ;
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bw_data = 'hx ;
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endtask
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task read(
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output logic [31:0] rdat,
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input logic [4:0] adr
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) ;
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@(posedge clk_b) ;
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#(STEP*0.1) ;
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b_addr = adr ;
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cs3 = 1'b1 ;
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we = 1'b0 ;
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be = 4'b0000 ;
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@(posedge clk_b) ;
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#(STEP*0.1) ;
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@(posedge clk_b) ;
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#(STEP*0.1) ;
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cs3 = 1'b1 ;
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we = 1'b0 ;
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`ifdef ALIGN_4B
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be = 4'b1111 ;
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`else
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be[0] = adr[1:0] == 2'b00 ;
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be[1] = adr[1:0] == 2'b01 ;
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be[2] = adr[1:0] == 2'b10 ;
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be[3] = adr[1:0] == 2'b11 ;
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`endif
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@(posedge clk_b) ;
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rdat = dat_o ;
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#(STEP*0.1) ;
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cs3 = 1'b0 ;
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we = 1'b0 ;
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be = 4'b0000 ;
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b_addr = 'hx ;
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bw_data = 'hx ;
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endtask
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task nop() ;
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@(posedge clk_b) ;
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#(STEP*0.1) ;
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b_addr = 'hx ;
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bw_data = 'hx ;
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cs3 = 1'b0 ;
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we = 1'b0 ;
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be = 4'b0000 ;
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endtask
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endinterface : wb_ext_bus
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