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/* *****************************************************************************
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* title: uart_16550_rll module *
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* description: RS232 Protocol 16550D uart (mostly supported) *
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* languages: systemVerilog *
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* *
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* Copyright (C) 2010 miyagi.hiroshi *
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* *
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* This library is free software; you can redistribute it and/or *
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* modify it under the terms of the GNU Lesser General Public *
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* License as published by the Free Software Foundation; either *
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* version 2.1 of the License, or (at your option) any later version. *
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* *
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* This library is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
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* Lesser General Public License for more details. *
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* *
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* You should have received a copy of the GNU Lesser General Public *
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* License along with this library; if not, write to the Free Software *
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
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* *
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* *** GNU LESSER GENERAL PUBLIC LICENSE *** *
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* from http://www.gnu.org/licenses/lgpl.txt *
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*****************************************************************************
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* redleaflogic,ltd *
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* miyagi.hiroshi@redleaflogic.biz *
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* $Id: uart_top.sv 108 2010-03-30 02:56:26Z hiroshi $ *
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***************************************************************************** */
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`ifdef SYN
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/* empty */
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`else
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timeunit 1ps ;
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timeprecision 1ps ;
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`endif
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// import uart_top_package:: * ;
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module uart_top
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(
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input wire clk_i, // clock
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input wire nrst_i, // reset
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input wire [15:0] adr_i, // address
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input wire [31:0] dat_i, // data input
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output wire [31:0] dat_o, // clk_rst_manager
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input wire we_i, // write enable
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input wire [3:0] sel_i, // select
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input wire stb_i, //
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output wire ack_o, // acknowledge accept
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input wire cyc_i, // cycle assrted
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output wire intr_o, //
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output wire stx_o,
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output wire rts_o,
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output wire dtr_o,
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input wire srx_i,
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input wire cts_i,
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input wire dsr_i,
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input wire ri_i,
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input wire dcd_i
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) ;
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uart_bus uart_bus() ;
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wb_bus wb_bus() ;
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assign wb_bus.clk_i = clk_i ;
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assign wb_bus.nrst_i = nrst_i ;
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assign wb_bus.adr_i = adr_i ;
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assign wb_bus.dat_i = dat_i ;
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assign dat_o = wb_bus.dat_o ;
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assign wb_bus.we_i = we_i ;
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assign wb_bus.sel_i = sel_i ;
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assign wb_bus.stb_i = stb_i ;
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assign ack_o = wb_bus.ack_o ;
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assign wb_bus.cyc_i = cyc_i ;
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assign intr_o = wb_bus.intr_o ;
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assign stx_o = uart_bus.stx_o ;
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assign rts_o = uart_bus.rts_o ;
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assign dtr_o = uart_bus.dtr_o ;
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assign uart_bus.srx_i = srx_i ;
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assign uart_bus.cts_i = cts_i ;
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assign uart_bus.dsr_i = dsr_i ;
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assign uart_bus.ri_i = ri_i ;
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assign uart_bus.dcd_i = dcd_i ;
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uart_16550_rll um(.wb_bus(wb_bus.slave_mp), .uart_bus(uart_bus)) ;
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endmodule
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