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/* *****************************************************************************
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* title: uart_16550_rll module *
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* description: RS232 Protocol 16550D uart (mostly supported) *
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* languages: systemVerilog *
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* *
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* Copyright (C) 2010 miyagi.hiroshi *
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* *
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* This library is free software; you can redistribute it and/or *
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* modify it under the terms of the GNU Lesser General Public *
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* License as published by the Free Software Foundation; either *
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* version 2.1 of the License, or (at your option) any later version. *
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* *
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* This library is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
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* Lesser General Public License for more details. *
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* *
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* You should have received a copy of the GNU Lesser General Public *
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* License along with this library; if not, write to the Free Software *
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
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* *
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* *** GNU LESSER GENERAL PUBLIC LICENSE *** *
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* from http://www.gnu.org/licenses/lgpl.txt *
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*****************************************************************************
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* redleaflogic,ltd *
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* miyagi.hiroshi@redleaflogic.biz *
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* $Id: fifo_package.sv 108 2010-03-30 02:56:26Z hiroshi $ *
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***************************************************************************** */
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package fifo_package ;
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`ifdef SYN
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/* empty */
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`else
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timeunit 1ps ;
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timeprecision 1ps ;
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`endif
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// -- read for manual -> 4.4 FIFO Control Register (FCR)
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// -- almost trgger level --
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localparam LEVEL_1 = 5'h1 ;
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localparam LEVEL_2 = 5'h4 ;
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localparam LEVEL_3 = 5'h8 ;
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localparam LEVEL_4 = 5'hE ;
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typedef struct {
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logic [10:0] mem [0:15] ;
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logic [0:0] err [0:15] ;
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logic [3:0] write_pointer ;
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logic [3:0] read_pointer ;
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logic full ;
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logic almost_full ;
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logic empty ;
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} u_fifo_t ;
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endpackage : fifo_package
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