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/* *****************************************************************************
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* title: uart_16550_rll module *
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* description: RS232 Protocol 16550D uart (mostly supported) *
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* languages: systemVerilog *
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* *
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* Copyright (C) 2010 miyagi.hiroshi *
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* *
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* This library is free software; you can redistribute it and/or *
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* modify it under the terms of the GNU Lesser General Public *
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* License as published by the Free Software Foundation; either *
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* version 2.1 of the License, or (at your option) any later version. *
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* *
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* This library is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
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* Lesser General Public License for more details. *
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* *
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* You should have received a copy of the GNU Lesser General Public *
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* License along with this library; if not, write to the Free Software *
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
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* *
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* *** GNU LESSER GENERAL PUBLIC LICENSE *** *
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* from http://www.gnu.org/licenses/lgpl.txt *
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*****************************************************************************
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* redleaflogic,ltd *
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* miyagi.hiroshi@redleaflogic.biz *
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* $Id: uart_codec_state.sv 108 2010-03-30 02:56:26Z hiroshi $ *
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***************************************************************************** */
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`ifdef SYN
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/* empty */
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`else
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timeunit 1ps ;
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timeprecision 1ps ;
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`endif
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import uart_package:: * ;
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module uart_codec_state(input u_reg_t u_reg,
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input u_codec_t codec,
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input wire receiver_mode,
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input wire timeout_signal,
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output codec_state_t next_state
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) ;
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// import uart_package:: * ;
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// -- count state -------------------
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// - IDLE --> START -> SEND0..SEND6->SEND7->PARITY->STOP
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// - ^ ^ | | ^ ^ |
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// - | | +------+---->+------+ |
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// - +---------+-------------------------------------+
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// - IDLE -> START :: transmit data : start bit
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// - STOP -> START :: transmit data : start bit
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// - START -> SEND0 :: alway
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// - SEND1 -> SEND2 :: alway
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// - .......
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// - SEND6 -> PARITY :: 7bit && parity
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// - SEND6 -> STOP :: 7bit
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// - SEND6 -> SEND7 :: 8bit
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// - SEND7 -> PARITY :: 8bit && parity
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// - SEND7 -> STOP :: 8bit
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// - STOP -> IDLE :: not start bit
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// ----------------------------------
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always_comb begin
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case (codec.state)
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IDLE : begin
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if(codec.start == 1'b1)
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next_state = START ;
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else
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next_state = IDLE ;
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end
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TIMEOUT : begin
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if(codec.start == 1'b1)
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next_state = START ;
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else if(timeout_signal == 1'b1 || u_reg.line_status_reg.data_ready == 1'b0)
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next_state = IDLE ;
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else
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next_state = TIMEOUT ;
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end
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START : next_state = SEL_0 ;
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SEL_0 : next_state = SEL_1 ;
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SEL_1 : next_state = SEL_2 ;
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SEL_2 : next_state = SEL_3 ;
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SEL_3 : next_state = SEL_4 ;
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SEL_4 : next_state = SEL_5 ;
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SEL_5 : begin
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if(u_reg.line_control_reg.char_length == CHAR_7_BIT)
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next_state = DATA_END ;
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else
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next_state = SEL_6 ;
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end
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SEL_6 : next_state = DATA_END ;
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DATA_END : begin
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if(u_reg.line_control_reg.parity_enable == 1'b1)
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next_state = PARITY ;
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else
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next_state = STOP ;
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end
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PARITY : next_state = STOP ;
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STOP : begin
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if(codec.start == 1'b1)
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next_state = START ;
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else if(u_reg.line_status_reg.data_ready == 1'b1 && receiver_mode == 1'b1)
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next_state = TIMEOUT ;
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else
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next_state = IDLE ;
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end
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default : next_state = IDLE ;
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endcase
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end
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endmodule
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