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/* *****************************************************************************
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* title: uart_16550_rll module *
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* description: RS232 Protocol 16550D uart (mostly supported) *
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* languages: systemVerilog *
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* *
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* Copyright (C) 2010 miyagi.hiroshi *
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* *
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* This library is free software; you can redistribute it and/or *
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* modify it under the terms of the GNU Lesser General Public *
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* License as published by the Free Software Foundation; either *
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* version 2.1 of the License, or (at your option) any later version. *
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* *
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* This library is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
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* Lesser General Public License for more details. *
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* *
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* You should have received a copy of the GNU Lesser General Public *
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* License along with this library; if not, write to the Free Software *
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
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* *
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* *** GNU LESSER GENERAL PUBLIC LICENSE *** *
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* from http://www.gnu.org/licenses/lgpl.txt *
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*****************************************************************************
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* redleaflogic,ltd *
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* miyagi.hiroshi@redleaflogic.biz *
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* $Id: uart_fifo.sv 108 2010-03-30 02:56:26Z hiroshi $ *
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***************************************************************************** */
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`ifdef SYN
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/* empty */
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`else
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timeunit 1ps ;
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timeprecision 1ps ;
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`endif
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// module uart_fifo #(parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 2)
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import fifo_package:: * ;
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module uart_fifo
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(input wire clk_i,
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input wire nrst_i,
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input wire clear,
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input wire [1:0] almost_empty_level,
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fifo_bus fifo_pop,
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fifo_bus fifo_push,
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output wire all_error
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) ;
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parameter ADDR_WIDTH = 2 ;
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parameter DATA_WIDTH = 2 ;
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// u_fifo_t #(DATA_WIDTH(8), ADDR_WIDTH(4)) u_fifo ;
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u_fifo_t u_fifo ;
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wire [ADDR_WIDTH-1:0] r_c1 ;
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reg f_fr ;
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wire pop = fifo_pop.pop ;
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wire push = fifo_push.push ;
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wire [DATA_WIDTH-1:0] push_dat = fifo_push.push_dat ;
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logic almost_full ;
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assign fifo_push.empty = (u_fifo.write_pointer == u_fifo.read_pointer) & ~f_fr ;
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assign fifo_push.full = (u_fifo.write_pointer == u_fifo.read_pointer) & f_fr ;
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assign fifo_pop.empty = (u_fifo.write_pointer == u_fifo.read_pointer) & ~f_fr ;
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assign fifo_pop.full = (u_fifo.write_pointer == u_fifo.read_pointer) & f_fr ;
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assign fifo_push.almost_full = almost_full ;
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always_comb begin
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case (almost_empty_level)
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2'b00 : begin
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almost_full = f_fr == 1'b1
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? (u_fifo.write_pointer - u_fifo.read_pointer) == LEVEL_1
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: (u_fifo.write_pointer + u_fifo.read_pointer) == LEVEL_1 ;
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end
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2'b01 : begin
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almost_full = f_fr == 1'b1
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? (u_fifo.write_pointer - u_fifo.read_pointer) == LEVEL_2
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: (u_fifo.write_pointer + u_fifo.read_pointer) == LEVEL_2 ;
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end
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2'b10 : begin
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almost_full = f_fr == 1'b1
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? (u_fifo.write_pointer - u_fifo.read_pointer) == LEVEL_3
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: (u_fifo.write_pointer + u_fifo.read_pointer) == LEVEL_3 ;
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end
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2'b11 : begin
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almost_full = f_fr == 1'b1
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? (u_fifo.write_pointer - u_fifo.read_pointer) == LEVEL_4
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: (u_fifo.write_pointer + u_fifo.read_pointer) == LEVEL_4 ;
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end
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endcase // case (almost_empty_level)
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end // always_comb begin
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assign #100 fifo_pop.pop_dat = u_fifo.mem[u_fifo.read_pointer] ;
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assign all_error = u_fifo.err[0] |
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u_fifo.err[1] |
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u_fifo.err[2] |
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u_fifo.err[3] |
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u_fifo.err[4] |
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u_fifo.err[5] |
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u_fifo.err[6] |
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u_fifo.err[7] |
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u_fifo.err[8] |
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u_fifo.err[9] |
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u_fifo.err[10] |
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u_fifo.err[11] |
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u_fifo.err[12] |
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u_fifo.err[13] |
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u_fifo.err[14] |
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u_fifo.err[15] ;
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always @(posedge clk_i, negedge nrst_i) begin
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if(nrst_i == 1'b0) begin
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u_fifo.err[0] <= #1 1'b0 ;
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u_fifo.err[1] <= #1 1'b0 ;
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u_fifo.err[2] <= #1 1'b0 ;
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u_fifo.err[3] <= #1 1'b0 ;
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u_fifo.err[4] <= #1 1'b0 ;
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u_fifo.err[5] <= #1 1'b0 ;
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u_fifo.err[6] <= #1 1'b0 ;
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u_fifo.err[7] <= #1 1'b0 ;
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u_fifo.err[8] <= #1 1'b0 ;
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u_fifo.err[9] <= #1 1'b0 ;
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u_fifo.err[10] <= #1 1'b0 ;
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u_fifo.err[11] <= #1 1'b0 ;
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u_fifo.err[12] <= #1 1'b0 ;
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u_fifo.err[13] <= #1 1'b0 ;
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u_fifo.err[14] <= #1 1'b0 ;
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u_fifo.err[15] <= #1 1'b0 ;
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u_fifo.mem[4'h0] <= #1 11'h000 ; // initial addr:'h0->data::'h0
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end
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else
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case ({push, pop})
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2'b01 : u_fifo.err[u_fifo.read_pointer] <= #1 1'b0 ;
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2'b10 : begin
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u_fifo.mem[u_fifo.write_pointer] <= #1 push_dat[10:0] ;
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u_fifo.err[u_fifo.write_pointer] <= #1 |(push_dat[10:8]) ;
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end
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2'b11 : begin
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u_fifo.mem[u_fifo.write_pointer] <= #1 push_dat[10:0] ;
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u_fifo.err[u_fifo.write_pointer] <= #1 |(push_dat[10:8]) ;
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u_fifo.err[u_fifo.read_pointer] <= #1 1'b0 ;
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end
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default : u_fifo.err <= #1 u_fifo.err ;
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endcase // case ({push, pop})
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end // always @ (posedge clk_i, negedge nrst_i)
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assign r_c1 = u_fifo.read_pointer - 'h01 ;
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always @(posedge clk_i, negedge nrst_i) begin
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if(nrst_i == 1'b0)
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f_fr <= #1 1'b0 ;
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else if(r_c1 == u_fifo.write_pointer)
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f_fr <= #1 1'b1 ;
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else if(pop == 1'b1 || clear == 1'b1)
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f_fr <= #1 1'b0 ;
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else
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f_fr <= #1 f_fr ;
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end
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always @(posedge clk_i, negedge nrst_i) begin
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if(nrst_i == 1'b0)
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u_fifo.write_pointer <= #1 'h00 ;
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else if(clear == 1'b1)
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u_fifo.write_pointer <= #1 'h00 ;
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else if(push == 1'b1)
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u_fifo.write_pointer <= #1 u_fifo.write_pointer + 'h01 ;
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else
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u_fifo.write_pointer <= #1 u_fifo.write_pointer ;
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end
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// -- read pinter inc & clear to current error bit --
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always @(posedge clk_i, negedge nrst_i) begin
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if(nrst_i == 1'b0)
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u_fifo.read_pointer <= #1 'h00 ;
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else if(clear == 1'b1)
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u_fifo.read_pointer <= #1 'h00 ;
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else if(pop == 1'b1)
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u_fifo.read_pointer <= #1 u_fifo.read_pointer + 'h01 ;
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else
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u_fifo.read_pointer <= #1 u_fifo.read_pointer ;
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end
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endmodule
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