| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The IN port controller.
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-- The IN port controller.
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--
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--
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-- $Id: t400_io_in.vhd,v 1.2 2006-05-23 01:13:28 arniml Exp $
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-- $Id: t400_io_in.vhd,v 1.3 2006-05-27 19:14:18 arniml Exp $
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--
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--
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 53... |
Line 53... |
port (
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port (
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-- System Interface -------------------------------------------------------
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-- System Interface -------------------------------------------------------
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ck_i : in std_logic;
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ck_i : in std_logic;
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ck_en_i : in boolean;
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ck_en_i : in boolean;
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por_i : in boolean;
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por_i : in boolean;
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icyc_en_i : in boolean;
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in_en_i : in boolean;
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in_en_i : in boolean;
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-- Control Interface ------------------------------------------------------
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-- Control Interface ------------------------------------------------------
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op_i : in io_in_op_t;
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op_i : in io_in_op_t;
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en1_i : in std_logic;
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en1_i : in std_logic;
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-- Port Interface ---------------------------------------------------------
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-- Port Interface ---------------------------------------------------------
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| Line 78... |
Line 79... |
std_logic_vector(2 downto 0);
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std_logic_vector(2 downto 0);
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signal neg_edge_q : neg_edge_t;
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signal neg_edge_q : neg_edge_t;
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signal neg_edge_s : std_logic_vector(2 downto 0);
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signal neg_edge_s : std_logic_vector(2 downto 0);
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|
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signal il_q : std_logic_vector(1 downto 0);
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signal il_q : std_logic_vector(1 downto 0);
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signal int_q,
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int_icyc_q : boolean;
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|
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begin
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begin
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|
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process seq
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-- Process seq
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| Line 93... |
Line 96... |
variable neg_edge_v : std_logic_vector(2 downto 0);
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variable neg_edge_v : std_logic_vector(2 downto 0);
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begin
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begin
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if por_i then
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if por_i then
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neg_edge_q <= (others => (others => '0'));
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neg_edge_q <= (others => (others => '0'));
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il_q <= (others => '0');
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il_q <= (others => '0');
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int_q <= false;
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int_icyc_q <= false;
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|
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elsif ck_i'event and ck_i = '1' then
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elsif ck_i'event and ck_i = '1' then
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-- negative edge detector filp-flops ------------------------------------
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-- negative edge detector filp-flops ------------------------------------
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neg_edge_v(idx_in3_c) := to_X01(io_in_i(3));
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neg_edge_v(idx_in3_c) := to_X01(io_in_i(3));
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neg_edge_v(idx_in0_c) := to_X01(io_in_i(0));
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neg_edge_v(idx_in0_c) := to_X01(io_in_i(0));
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| Line 117... |
Line 122... |
((neg_edge_q(0)(idx_in0_c) or neg_edge_v(idx_in0_c)) = '0') then
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((neg_edge_q(0)(idx_in0_c) or neg_edge_v(idx_in0_c)) = '0') then
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il_q(0) <= '1';
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il_q(0) <= '1';
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end if;
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end if;
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end if;
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end if;
|
|
|
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-- Interrupt trigger ----------------------------------------------------
|
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if in_en_i then
|
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if neg_edge_q(1)(idx_int_c) = '1' and
|
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((neg_edge_q(0)(idx_int_c) or neg_edge_v(idx_int_c)) = '0') then
|
|
int_q <= true;
|
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end if;
|
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end if;
|
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if icyc_en_i then
|
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-- delay interrupt request until end of current instruction
|
|
-- this ensures that the interrupt is valid for a full instruction
|
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-- (i.e. the next one)
|
|
int_icyc_q <= int_q;
|
|
end if;
|
|
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if ck_en_i then
|
if ck_en_i then
|
if op_i = IOIN_INIL then
|
if op_i = IOIN_INIL then
|
il_q <= (others => '0');
|
il_q <= (others => '0');
|
end if;
|
end if;
|
|
|
|
if op_i = IOIN_INTACK then
|
|
int_q <= false;
|
|
int_icyc_q <= false;
|
|
end if;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process seq;
|
end process seq;
|
--
|
--
|
| Line 135... |
Line 159... |
-- Output mapping
|
-- Output mapping
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
in_o <= il_q(1) & "00" & il_q(0)
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in_o <= il_q(1) & "00" & il_q(0)
|
when op_i = IOIN_INIL else
|
when op_i = IOIN_INIL else
|
io_in_i;
|
io_in_i;
|
int_o <= false;
|
int_o <= int_icyc_q;
|
|
|
end rtl;
|
end rtl;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.2 2006/05/23 01:13:28 arniml
|
|
-- + reset neg_edge flip-flops to '1'
|
|
-- -> after por, a 1-to-0 edge is required to trigger the latches initially
|
|
-- + use to_X01
|
|
--
|
-- Revision 1.1 2006/05/22 00:00:55 arniml
|
-- Revision 1.1 2006/05/22 00:00:55 arniml
|
-- initial check-in
|
-- initial check-in
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
No newline at end of file
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No newline at end of file
|
