;; *******************************************************************
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;; *******************************************************************
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;; $Id: test.asm,v 1.2 2006-05-27 22:46:29 arniml Exp $
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;; $Id: test.asm 179 2009-04-01 19:48:38Z arniml $
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;;
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;;
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;; Checks the XAS instruction.
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;; Checks the XAS instruction.
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;;
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;;
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;; the cpu type is defined on asl's command line
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;; the cpu type is defined on asl's command line
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org 0x00
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org 0x00
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clra
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clra
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;; *******************************************************************
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;; *******************************************************************
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;; Test counter functionality
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;; Test counter functionality
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;;
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;;
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lei 0x5
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lei 0x5
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;; enable counter
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;; enable counter
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clra
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clra
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camq
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camq
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;; clear SKL
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;; clear SKL
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xas
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xas
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nop ; spend some time to let effect of SKL
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nop ; spend some time to let effect of SKL
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nop ; falling edge pass by
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nop ; falling edge pass by
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nop ;
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nop ;
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;; -------------------------------------------------------------------
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;; -------------------------------------------------------------------
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;; step 1
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;; step 1
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;; decrement counter from 1 to 0
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;; decrement counter from 1 to 0
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;; test SO by controlling SI via SO
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;; test SO by controlling SI via SO
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;;
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;;
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;; load 0x1 to counter
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;; load 0x1 to counter
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clra
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clra
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aisc 0x1
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aisc 0x1
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xas
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xas
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;; decrement via SO
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;; decrement via SO
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lei 0xd
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lei 0xd
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nop ; ensure minimum '1' duration
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nop ; ensure minimum '1' duration
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lei 0x5
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lei 0x5
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nop ;
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nop ;
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nop ; ensure minimum '0' duration
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nop ; ensure minimum '0' duration
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nop ;
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nop ;
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xas
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xas
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;; check for 0x0
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;; check for 0x0
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xad 3, 15
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xad 3, 15
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clra
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clra
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x 0
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x 0
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xad 3, 15
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xad 3, 15
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ske
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ske
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jmp fail
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jmp fail
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;; -------------------------------------------------------------------
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;; -------------------------------------------------------------------
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;; step 2
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;; step 2
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;; decrement counter from 0 to 0xf
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;; decrement counter from 0 to 0xf
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;; test SKL by controlling SI via SK
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;; test SKL by controlling SI via SK
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;;
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;;
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;; set SKL to '1'
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;; set SKL to '1'
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sc ; SKL = '1'
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sc ; SKL = '1'
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xas
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xas
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;; load 0x0 to counter, decrement via SK
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;; load 0x0 to counter, decrement via SK
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clra
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clra
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rc
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rc
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xas
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xas
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nop ;
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nop ;
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nop ; ensure minimum '0' duration
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nop ; ensure minimum '0' duration
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nop ;
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nop ;
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xas
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xas
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;; check for 0xf
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;; check for 0xf
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xad 3, 15
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xad 3, 15
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clra
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clra
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aisc 0xf
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aisc 0xf
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x 0
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x 0
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xad 3, 15
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xad 3, 15
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ske
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ske
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jmp fail
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jmp fail
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;; -------------------------------------------------------------------
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;; -------------------------------------------------------------------
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;; step 3
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;; step 3
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;; check minimum high time on SI
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;; check minimum high time on SI
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;;
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;;
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;; load 0x0 to counter
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;; load 0x0 to counter
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clra
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clra
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xas
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xas
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;; clock on SI
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;; clock on SI
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lei 0xd
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lei 0xd
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lei 0x5 ; high time too short
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lei 0x5 ; high time too short
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nop ;
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nop ;
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nop ; ensure minimum '0' duration
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nop ; ensure minimum '0' duration
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nop ;
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nop ;
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xas
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xas
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;; check for 0x0
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;; check for 0x0
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xad 3, 15
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xad 3, 15
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clra
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clra
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x 0
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x 0
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xad 3, 15
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xad 3, 15
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ske
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ske
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jmp fail
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jmp fail
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;; -------------------------------------------------------------------
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;; -------------------------------------------------------------------
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;; step 4
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;; step 4
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;; check minimum low time on SI
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;; check minimum low time on SI
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;;
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;;
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;; load 0x0 to counter
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;; load 0x0 to counter
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clra
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clra
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xas
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xas
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;; clock on SI
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;; clock on SI
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lei 0xd
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lei 0xd
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nop ; ensure minimum '1' duration
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nop ; ensure minimum '1' duration
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lei 0x5
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lei 0x5
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lei 0xd ; low time too short
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lei 0xd ; low time too short
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xas
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xas
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;; check for 0x0
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;; check for 0x0
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xad 3, 15
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xad 3, 15
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clra
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clra
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x 0
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x 0
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xad 3, 15
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xad 3, 15
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ske
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ske
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jmp fail
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jmp fail
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;; *******************************************************************
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;; *******************************************************************
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;; Test shift register functionality
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;; Test shift register functionality
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;;
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;;
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lei 0xc ; SO = SIO output
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lei 0xc ; SO = SIO output
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;; enable shift register
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;; enable shift register
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aisc 0x1
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aisc 0x1
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camq
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camq
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;; shift out 0x5
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;; shift out 0x5
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aisc 0x4
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aisc 0x4
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sc
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sc
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xas
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xas
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;;
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;;
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nop ;
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nop ;
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nop ; shift for four clocks on SK
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nop ; shift for four clocks on SK
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rc ;
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rc ;
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xas ; stop SK
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xas ; stop SK
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;; check for 0x2
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;; check for 0x2
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xad 3, 15
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xad 3, 15
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clra
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clra
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aisc 0x2
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aisc 0x2
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x 0
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x 0
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xad 3, 15
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xad 3, 15
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ske
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ske
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jmp fail
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jmp fail
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;; shift out 0x0
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;; shift out 0x0
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clra
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clra
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sc
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sc
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xas
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xas
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;;
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;;
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nop ;
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nop ;
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nop ; shift for four clocks on SK
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nop ; shift for four clocks on SK
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rc ;
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rc ;
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xas ; stop SK
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xas ; stop SK
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;; check for 0x8
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;; check for 0x8
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xad 3, 15
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xad 3, 15
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clra
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clra
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aisc 0x8
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aisc 0x8
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x 0
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x 0
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xad 3, 15
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xad 3, 15
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ske
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ske
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jmp fail
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jmp fail
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;; now disable SO and check that only '0' is shifted in
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;; now disable SO and check that only '0' is shifted in
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lei 0x4 ; SO = '0'
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lei 0x4 ; SO = '0'
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;; shift out 0xf
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;; shift out 0xf
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clra
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clra
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aisc 0xf
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aisc 0xf
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sc
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sc
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xas
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xas
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;;
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;;
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nop ;
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nop ;
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nop ; shift for four clocks on SK
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nop ; shift for four clocks on SK
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rc ;
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rc ;
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xas ; stop SK
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xas ; stop SK
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;; check for 0x0
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;; check for 0x0
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xad 3, 15
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xad 3, 15
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clra
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clra
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x 0
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x 0
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xad 3, 15
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xad 3, 15
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ske
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ske
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jmp fail
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jmp fail
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;; enable SO
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;; enable SO
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lei 0xc
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lei 0xc
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;; shift out 0x1 to force SI to '1' via SO
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;; shift out 0x1 to force SI to '1' via SO
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clra
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clra
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aisc 0x1
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aisc 0x1
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sc
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sc
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xas
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xas
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;;
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;;
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nop ;
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nop ;
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nop ; shift for four clocks on SK
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nop ; shift for four clocks on SK
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rc ;
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rc ;
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xas ; stop SK
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xas ; stop SK
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;; shift out 0x0 with disabled SK
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;; shift out 0x0 with disabled SK
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clra
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clra
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xas
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xas
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;;
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;;
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nop ;
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nop ;
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nop ; shift for four clocks on SK
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nop ; shift for four clocks on SK
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nop ;
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nop ;
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xas
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xas
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;; check for 0xf
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;; check for 0xf
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xad 3, 15
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xad 3, 15
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clra
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clra
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aisc 0xf
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aisc 0xf
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x 0
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x 0
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xad 3, 15
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xad 3, 15
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ske
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ske
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jmp fail
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jmp fail
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jmp pass
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jmp pass
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org 0x100
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org 0x100
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include "pass_fail.asm"
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include "pass_fail.asm"
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