;; *******************************************************************
|
;; *******************************************************************
|
;; $Id: test.asm,v 1.1.1.1 2006-05-06 01:56:45 arniml Exp $
|
;; $Id: test.asm 179 2009-04-01 19:48:38Z arniml $
|
;;
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;;
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;; Checks the XDS instruction.
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;; Checks the XDS instruction.
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;;
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;;
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|
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;; the cpu type is defined on asl's command line
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;; the cpu type is defined on asl's command line
|
|
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org 0x00
|
org 0x00
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clra
|
clra
|
|
|
|
|
;; *******************************************************************
|
;; *******************************************************************
|
;; XOR 0
|
;; XOR 0
|
jsr init_ram
|
jsr init_ram
|
|
|
;; xor 0 in digit 0
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;; xor 0 in digit 0
|
lbi 0, 0
|
lbi 0, 0
|
jsr init_bd
|
jsr init_bd
|
;;
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;;
|
xds 0 ; 0, 3 = 0x3
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xds 0 ; 0, 3 = 0x3
|
;;
|
;;
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cba
|
cba
|
xds 0 ; 0, 2 = 0x2
|
xds 0 ; 0, 2 = 0x2
|
;;
|
;;
|
cba
|
cba
|
xds 0 ; 0, 1 = 0x1
|
xds 0 ; 0, 1 = 0x1
|
;;
|
;;
|
cba
|
cba
|
xds 0 ; 0, 0 = 0x0
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xds 0 ; 0, 0 = 0x0
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jmp fail
|
jmp fail
|
|
|
;; xor 0 in digit 1
|
;; xor 0 in digit 1
|
lbi 1, 0
|
lbi 1, 0
|
jsr init_bd
|
jsr init_bd
|
;;
|
;;
|
aisc 1 << 2
|
aisc 1 << 2
|
xds 0 ; 1, 3 = 0x7
|
xds 0 ; 1, 3 = 0x7
|
;;
|
;;
|
cba
|
cba
|
aisc 1 << 2
|
aisc 1 << 2
|
xds 0 ; 1, 2 = 0x6
|
xds 0 ; 1, 2 = 0x6
|
;;
|
;;
|
cba
|
cba
|
aisc 1 << 2
|
aisc 1 << 2
|
xds 0 ; 1, 1 = 0x5
|
xds 0 ; 1, 1 = 0x5
|
;;
|
;;
|
cba
|
cba
|
aisc 1 << 2
|
aisc 1 << 2
|
xds 0 ; 1, 0 = 0x4
|
xds 0 ; 1, 0 = 0x4
|
jmp fail
|
jmp fail
|
|
|
;; xor 0 in digit 2
|
;; xor 0 in digit 2
|
lbi 2, 0
|
lbi 2, 0
|
jsr init_bd
|
jsr init_bd
|
;;
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;;
|
aisc 2 << 2
|
aisc 2 << 2
|
xds 0 ; 2, 3 = 0xb
|
xds 0 ; 2, 3 = 0xb
|
;;
|
;;
|
cba
|
cba
|
aisc 2 << 2
|
aisc 2 << 2
|
xds 0 ; 2, 2 = 0xa
|
xds 0 ; 2, 2 = 0xa
|
;;
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;;
|
cba
|
cba
|
aisc 2 << 2
|
aisc 2 << 2
|
xds 0 ; 2, 1 = 0x9
|
xds 0 ; 2, 1 = 0x9
|
;;
|
;;
|
cba
|
cba
|
aisc 2 << 2
|
aisc 2 << 2
|
xds 0 ; 2, 0 = 0x8
|
xds 0 ; 2, 0 = 0x8
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jmp fail
|
jmp fail
|
|
|
;; xor 0 in digit 3
|
;; xor 0 in digit 3
|
lbi 3, 0
|
lbi 3, 0
|
jsr init_bd
|
jsr init_bd
|
;;
|
;;
|
aisc 3 << 2
|
aisc 3 << 2
|
xds 0 ; 3, 3 = 0xf
|
xds 0 ; 3, 3 = 0xf
|
;;
|
;;
|
cba
|
cba
|
aisc 3 << 2
|
aisc 3 << 2
|
xds 0 ; 3, 2 = 0xe
|
xds 0 ; 3, 2 = 0xe
|
;;
|
;;
|
cba
|
cba
|
aisc 3 << 2
|
aisc 3 << 2
|
xds 0 ; 3, 1 = 0xd
|
xds 0 ; 3, 1 = 0xd
|
;;
|
;;
|
cba
|
cba
|
aisc 3 << 2
|
aisc 3 << 2
|
xds 0 ; 3, 0 = 0xc
|
xds 0 ; 3, 0 = 0xc
|
jmp fail
|
jmp fail
|
;; check remaining Br == 3
|
;; check remaining Br == 3
|
clra
|
clra
|
cab
|
cab
|
aisc 0xc
|
aisc 0xc
|
ske
|
ske
|
jmp fail
|
jmp fail
|
|
|
jsr check_ram
|
jsr check_ram
|
|
|
|
|
;; *******************************************************************
|
;; *******************************************************************
|
;; XOR 1
|
;; XOR 1
|
jsr init_ram
|
jsr init_ram
|
|
|
;;
|
;;
|
;; xor 1 in digit 0 & 1
|
;; xor 1 in digit 0 & 1
|
;;
|
;;
|
lbi 0, 0
|
lbi 0, 0
|
jsr init_bd
|
jsr init_bd
|
;;
|
;;
|
xds 1 ; 0, 3 = 0x3
|
xds 1 ; 0, 3 = 0x3
|
;;
|
;;
|
cba
|
cba
|
aisc 1 << 2
|
aisc 1 << 2
|
xds 1 ; 1, 2 = 0x6
|
xds 1 ; 1, 2 = 0x6
|
;;
|
;;
|
cba
|
cba
|
xds 1 ; 0, 1 = 0x1
|
xds 1 ; 0, 1 = 0x1
|
;;
|
;;
|
cba
|
cba
|
aisc 1 << 2
|
aisc 1 << 2
|
xds 1 ; 1, 0 = 0x4
|
xds 1 ; 1, 0 = 0x4
|
jmp fail
|
jmp fail
|
;; check remaining Br == 0
|
;; check remaining Br == 0
|
clra
|
clra
|
cab
|
cab
|
aisc 0xf ; RAM init value
|
aisc 0xf ; RAM init value
|
ske
|
ske
|
jmp fail
|
jmp fail
|
;; reload to Br = 1
|
;; reload to Br = 1
|
lbi 1, 0
|
lbi 1, 0
|
jsr init_bd
|
jsr init_bd
|
;;
|
;;
|
aisc 1 << 2
|
aisc 1 << 2
|
xds 1 ; 1, 3 = 0x7
|
xds 1 ; 1, 3 = 0x7
|
;;
|
;;
|
cba
|
cba
|
xds 1 ; 0, 2 = 0x2
|
xds 1 ; 0, 2 = 0x2
|
;;
|
;;
|
cba
|
cba
|
aisc 1 << 2
|
aisc 1 << 2
|
xds 1 ; 1, 1 = 0x5
|
xds 1 ; 1, 1 = 0x5
|
;;
|
;;
|
cba
|
cba
|
xds 1 ; 0, 0 = 0x0
|
xds 1 ; 0, 0 = 0x0
|
jmp fail
|
jmp fail
|
;; check remaining Br == 1
|
;; check remaining Br == 1
|
clra
|
clra
|
cab
|
cab
|
aisc 0x4
|
aisc 0x4
|
ske
|
ske
|
jmp fail
|
jmp fail
|
|
|
;;
|
;;
|
;; xor 1 in digit 2 & 3
|
;; xor 1 in digit 2 & 3
|
;;
|
;;
|
lbi 2, 0
|
lbi 2, 0
|
jsr init_bd
|
jsr init_bd
|
;;
|
;;
|
aisc 2 << 2
|
aisc 2 << 2
|
xds 1 ; 2, 3 = 0xb
|
xds 1 ; 2, 3 = 0xb
|
;;
|
;;
|
cba
|
cba
|
aisc 3 << 2
|
aisc 3 << 2
|
xds 1 ; 3, 2 = 0xe
|
xds 1 ; 3, 2 = 0xe
|
;;
|
;;
|
cba
|
cba
|
aisc 2 << 2
|
aisc 2 << 2
|
xds 1 ; 2, 1 = 0x9
|
xds 1 ; 2, 1 = 0x9
|
;;
|
;;
|
cba
|
cba
|
aisc 3 << 2
|
aisc 3 << 2
|
xds 1 ; 3, 0 = 0xc
|
xds 1 ; 3, 0 = 0xc
|
jmp fail
|
jmp fail
|
;; check remaining Br == 2
|
;; check remaining Br == 2
|
clra
|
clra
|
cab
|
cab
|
aisc 0x7 ; RAM init value
|
aisc 0x7 ; RAM init value
|
ske
|
ske
|
jmp fail
|
jmp fail
|
;; reload to Br = 3
|
;; reload to Br = 3
|
lbi 3, 0
|
lbi 3, 0
|
jsr init_bd
|
jsr init_bd
|
;;
|
;;
|
aisc 3 << 2
|
aisc 3 << 2
|
xds 1 ; 3, 3 = 0xf
|
xds 1 ; 3, 3 = 0xf
|
;;
|
;;
|
cba
|
cba
|
aisc 2 << 2
|
aisc 2 << 2
|
xds 1 ; 2, 2 = 0xa
|
xds 1 ; 2, 2 = 0xa
|
;;
|
;;
|
cba
|
cba
|
aisc 3 << 2
|
aisc 3 << 2
|
xds 1 ; 3, 1 = 0xd
|
xds 1 ; 3, 1 = 0xd
|
;;
|
;;
|
cba
|
cba
|
aisc 2 << 2
|
aisc 2 << 2
|
xds 1 ; 2, 0 = 0x8
|
xds 1 ; 2, 0 = 0x8
|
jmp fail
|
jmp fail
|
;; check remaining Br == 3
|
;; check remaining Br == 3
|
clra
|
clra
|
cab
|
cab
|
aisc 0xc
|
aisc 0xc
|
ske
|
ske
|
jmp fail
|
jmp fail
|
|
|
jsr check_ram
|
jsr check_ram
|
|
|
|
|
;; *******************************************************************
|
;; *******************************************************************
|
;; XOR 2
|
;; XOR 2
|
jsr init_ram
|
jsr init_ram
|
|
|
;;
|
;;
|
;; xor 2 in digit 0 & 2
|
;; xor 2 in digit 0 & 2
|
;;
|
;;
|
lbi 0, 0
|
lbi 0, 0
|
jsr init_bd
|
jsr init_bd
|
;;
|
;;
|
xds 2 ; 0, 3 = 0x3
|
xds 2 ; 0, 3 = 0x3
|
;;
|
;;
|
cba
|
cba
|
aisc 2 << 2
|
aisc 2 << 2
|
xds 2 ; 2, 2 = 0xa
|
xds 2 ; 2, 2 = 0xa
|
;;
|
;;
|
cba
|
cba
|
xds 2 ; 0, 1 = 0x1
|
xds 2 ; 0, 1 = 0x1
|
;;
|
;;
|
cba
|
cba
|
aisc 2 << 2
|
aisc 2 << 2
|
xds 2 ; 2, 0 = 0x8
|
xds 2 ; 2, 0 = 0x8
|
jmp fail
|
jmp fail
|
;; check remainig Br == 0
|
;; check remainig Br == 0
|
clra
|
clra
|
cab
|
cab
|
aisc 0xf ; RAM init value
|
aisc 0xf ; RAM init value
|
ske
|
ske
|
jmp fail
|
jmp fail
|
;; reload to Br == 2
|
;; reload to Br == 2
|
lbi 2, 0
|
lbi 2, 0
|
jsr init_bd
|
jsr init_bd
|
;;
|
;;
|
aisc 2 << 2
|
aisc 2 << 2
|
xds 2 ; 2, 3 = 0xb
|
xds 2 ; 2, 3 = 0xb
|
;;
|
;;
|
cba
|
cba
|
xds 2 ; 0, 2 = 0x2
|
xds 2 ; 0, 2 = 0x2
|
;;
|
;;
|
cba
|
cba
|
aisc 2 << 2
|
aisc 2 << 2
|
xds 2 ; 2, 1 = 0x9
|
xds 2 ; 2, 1 = 0x9
|
;;
|
;;
|
cba
|
cba
|
xds 2 ; 0, 0 = 0x0
|
xds 2 ; 0, 0 = 0x0
|
jmp fail
|
jmp fail
|
;; check remainig Br == 2
|
;; check remainig Br == 2
|
clra
|
clra
|
cab
|
cab
|
aisc 0x8
|
aisc 0x8
|
ske
|
ske
|
jmp fail
|
jmp fail
|
|
|
;;
|
;;
|
;; xor 2 in digit 1 & 3
|
;; xor 2 in digit 1 & 3
|
;;
|
;;
|
lbi 1, 0
|
lbi 1, 0
|
jsr init_bd
|
jsr init_bd
|
;;
|
;;
|
aisc 1 << 2
|
aisc 1 << 2
|
xds 2 ; 1, 3 = 0x7
|
xds 2 ; 1, 3 = 0x7
|
;;
|
;;
|
cba
|
cba
|
aisc 3 << 2
|
aisc 3 << 2
|
xds 2 ; 3, 2 = 0xe
|
xds 2 ; 3, 2 = 0xe
|
;;
|
;;
|
cba
|
cba
|
aisc 1 << 2
|
aisc 1 << 2
|
xds 2 ; 1, 1 = 0x5
|
xds 2 ; 1, 1 = 0x5
|
;;
|
;;
|
cba
|
cba
|
aisc 3 << 2
|
aisc 3 << 2
|
xds 2 ; 3, 0 = 0xc
|
xds 2 ; 3, 0 = 0xc
|
jmp fail
|
jmp fail
|
;; check remaining Br == 1
|
;; check remaining Br == 1
|
clra
|
clra
|
cab
|
cab
|
aisc 0xc ; RAM init value
|
aisc 0xc ; RAM init value
|
ske
|
ske
|
jmp fail
|
jmp fail
|
;; reload to Br = 3
|
;; reload to Br = 3
|
lbi 3, 0
|
lbi 3, 0
|
jsr init_bd
|
jsr init_bd
|
;;
|
;;
|
aisc 3 << 2
|
aisc 3 << 2
|
xds 2 ; 3, 3 = 0xf
|
xds 2 ; 3, 3 = 0xf
|
;;
|
;;
|
cba
|
cba
|
aisc 1 << 2
|
aisc 1 << 2
|
xds 2 ; 1, 2 = 0x6
|
xds 2 ; 1, 2 = 0x6
|
;;
|
;;
|
cba
|
cba
|
aisc 3 << 2
|
aisc 3 << 2
|
xds 2 ; 3, 1 = 0xd
|
xds 2 ; 3, 1 = 0xd
|
;;
|
;;
|
cba
|
cba
|
aisc 1 << 2
|
aisc 1 << 2
|
xds 2 ; 1, 0 = 0x4
|
xds 2 ; 1, 0 = 0x4
|
jmp fail
|
jmp fail
|
;; check remaining Br == 3
|
;; check remaining Br == 3
|
clra
|
clra
|
cab
|
cab
|
aisc 0xc
|
aisc 0xc
|
ske
|
ske
|
jmp fail
|
jmp fail
|
|
|
jsr check_ram
|
jsr check_ram
|
|
|
|
|
;; *******************************************************************
|
;; *******************************************************************
|
;; XOR 3
|
;; XOR 3
|
jsr init_ram
|
jsr init_ram
|
|
|
;;
|
;;
|
;; xor 3 in digit 0 & 3
|
;; xor 3 in digit 0 & 3
|
;;
|
;;
|
lbi 0, 0
|
lbi 0, 0
|
jsr init_bd
|
jsr init_bd
|
;;
|
;;
|
xds 3 ; 0, 3 = 0x3
|
xds 3 ; 0, 3 = 0x3
|
;;
|
;;
|
cba
|
cba
|
aisc 3 << 2
|
aisc 3 << 2
|
xds 3 ; 3, 2 = 0xe
|
xds 3 ; 3, 2 = 0xe
|
;;
|
;;
|
cba
|
cba
|
xds 3 ; 0, 1 = 0x1
|
xds 3 ; 0, 1 = 0x1
|
;;
|
;;
|
cba
|
cba
|
aisc 3 << 2
|
aisc 3 << 2
|
xds 3 ; 3, 0 = 0xc
|
xds 3 ; 3, 0 = 0xc
|
jmp fail
|
jmp fail
|
;; check remaining BR == 0
|
;; check remaining BR == 0
|
clra
|
clra
|
cab
|
cab
|
aisc 0xf ; RAM init value
|
aisc 0xf ; RAM init value
|
ske
|
ske
|
jmp fail
|
jmp fail
|
;; reload BR = 3
|
;; reload BR = 3
|
lbi 3, 0
|
lbi 3, 0
|
jsr init_bd
|
jsr init_bd
|
;;
|
;;
|
aisc 3 << 2
|
aisc 3 << 2
|
xds 3 ; 3, 3 = 0xf
|
xds 3 ; 3, 3 = 0xf
|
;;
|
;;
|
cba
|
cba
|
xds 3 ; 0, 2 = 0x2
|
xds 3 ; 0, 2 = 0x2
|
;;
|
;;
|
cba
|
cba
|
aisc 3 << 2
|
aisc 3 << 2
|
xds 3 ; 3, 1 = 0xb
|
xds 3 ; 3, 1 = 0xb
|
;;
|
;;
|
cba
|
cba
|
xds 3 ; 0, 0 = 0x0
|
xds 3 ; 0, 0 = 0x0
|
jmp fail
|
jmp fail
|
;; check remaining BR == 3
|
;; check remaining BR == 3
|
clra
|
clra
|
cab
|
cab
|
aisc 0xc
|
aisc 0xc
|
ske
|
ske
|
jmp fail
|
jmp fail
|
|
|
;;
|
;;
|
;; xor 3 in digit 1 & 2
|
;; xor 3 in digit 1 & 2
|
;;
|
;;
|
lbi 1, 0
|
lbi 1, 0
|
jsr init_bd
|
jsr init_bd
|
;;
|
;;
|
aisc 1 << 2
|
aisc 1 << 2
|
xds 3 ; 1, 3 = 0x7
|
xds 3 ; 1, 3 = 0x7
|
;;
|
;;
|
cba
|
cba
|
aisc 2 << 2
|
aisc 2 << 2
|
xds 3 ; 2, 2 = 0xa
|
xds 3 ; 2, 2 = 0xa
|
;;
|
;;
|
cba
|
cba
|
aisc 1 << 2
|
aisc 1 << 2
|
xds 3 ; 1, 1 = 0x5
|
xds 3 ; 1, 1 = 0x5
|
;;
|
;;
|
cba
|
cba
|
aisc 2 << 2
|
aisc 2 << 2
|
xds 3 ; 2, 0 = 0x8
|
xds 3 ; 2, 0 = 0x8
|
jmp fail
|
jmp fail
|
;; check remaining BR == 1
|
;; check remaining BR == 1
|
clra
|
clra
|
cab
|
cab
|
aisc 0xc ; RAM init value
|
aisc 0xc ; RAM init value
|
ske
|
ske
|
jmp fail
|
jmp fail
|
;; reload BR = 2
|
;; reload BR = 2
|
lbi 2, 0
|
lbi 2, 0
|
jsr init_bd
|
jsr init_bd
|
;;
|
;;
|
aisc 2 << 2
|
aisc 2 << 2
|
xds 3 ; 2, 3 = 0xb
|
xds 3 ; 2, 3 = 0xb
|
;;
|
;;
|
cba
|
cba
|
aisc 1 << 2
|
aisc 1 << 2
|
xds 3 ; 1, 2 = 0x6
|
xds 3 ; 1, 2 = 0x6
|
;;
|
;;
|
cba
|
cba
|
aisc 2 << 2
|
aisc 2 << 2
|
xds 3 ; 2, 1 = 0x9
|
xds 3 ; 2, 1 = 0x9
|
;;
|
;;
|
cba
|
cba
|
aisc 1 << 2
|
aisc 1 << 2
|
xds 3 ; 1, 0 = 0x5
|
xds 3 ; 1, 0 = 0x5
|
jmp fail
|
jmp fail
|
;; check remaining BR == 2
|
;; check remaining BR == 2
|
clra
|
clra
|
cab
|
cab
|
aisc 0x8
|
aisc 0x8
|
ske
|
ske
|
jmp fail
|
jmp fail
|
|
|
jsr check_ram
|
jsr check_ram
|
|
|
|
|
jmp pass
|
jmp pass
|
|
|
|
|
|
|
|
|
org 0x158
|
org 0x158
|
|
|
;; initializes Bd to 3
|
;; initializes Bd to 3
|
init_bd:
|
init_bd:
|
clra
|
clra
|
aisc 0x3
|
aisc 0x3
|
cab
|
cab
|
ret
|
ret
|
|
|
|
|
;; preload digits of each data register
|
;; preload digits of each data register
|
init_ram:
|
init_ram:
|
;; Br = 0
|
;; Br = 0
|
lbi 0, 0
|
lbi 0, 0
|
stii 0xf
|
stii 0xf
|
stii 0xe
|
stii 0xe
|
stii 0xd
|
stii 0xd
|
stii 0xb
|
stii 0xb
|
;; Br = 1
|
;; Br = 1
|
lbi 1, 0
|
lbi 1, 0
|
stii 0xc
|
stii 0xc
|
stii 0xa
|
stii 0xa
|
stii 0x9
|
stii 0x9
|
stii 0x8
|
stii 0x8
|
;; Br = 2
|
;; Br = 2
|
lbi 2, 0
|
lbi 2, 0
|
stii 0x7
|
stii 0x7
|
stii 0x6
|
stii 0x6
|
stii 0x5
|
stii 0x5
|
stii 0x4
|
stii 0x4
|
;; Br = 3
|
;; Br = 3
|
lbi 3, 0
|
lbi 3, 0
|
stii 0x3
|
stii 0x3
|
stii 0x2
|
stii 0x2
|
stii 0x1
|
stii 0x1
|
stii 0x0
|
stii 0x0
|
ret
|
ret
|
|
|
|
|
check MACRO dig
|
check MACRO dig
|
;; check dig, 0
|
;; check dig, 0
|
clra
|
clra
|
IF dig > 0
|
IF dig > 0
|
aisc dig << 2
|
aisc dig << 2
|
ENDIF
|
ENDIF
|
ske
|
ske
|
jmp fail
|
jmp fail
|
;; check 0, 1
|
;; check 0, 1
|
clra
|
clra
|
aisc 0x1
|
aisc 0x1
|
cab
|
cab
|
IF dig > 0
|
IF dig > 0
|
aisc dig << 2
|
aisc dig << 2
|
ENDIF
|
ENDIF
|
ske
|
ske
|
jmp fail
|
jmp fail
|
;; check 0, 2
|
;; check 0, 2
|
clra
|
clra
|
aisc 0x2
|
aisc 0x2
|
cab
|
cab
|
IF dig > 0
|
IF dig > 0
|
aisc dig << 2
|
aisc dig << 2
|
ENDIF
|
ENDIF
|
ske
|
ske
|
jmp fail
|
jmp fail
|
;; check 0, 3
|
;; check 0, 3
|
clra
|
clra
|
aisc 0x3
|
aisc 0x3
|
cab
|
cab
|
IF dig > 0
|
IF dig > 0
|
aisc dig << 2
|
aisc dig << 2
|
ENDIF
|
ENDIF
|
ske
|
ske
|
jmp fail
|
jmp fail
|
ENDM
|
ENDM
|
|
|
;; check contents of RAM entries
|
;; check contents of RAM entries
|
check_ram:
|
check_ram:
|
;; check digit 0
|
;; check digit 0
|
lbi 0, 0
|
lbi 0, 0
|
check 0
|
check 0
|
|
|
;; check digit 1
|
;; check digit 1
|
lbi 1, 0
|
lbi 1, 0
|
check 1
|
check 1
|
|
|
;; check digit 2
|
;; check digit 2
|
lbi 2, 0
|
lbi 2, 0
|
check 2
|
check 2
|
|
|
;; check digit 3
|
;; check digit 3
|
lbi 3, 0
|
lbi 3, 0
|
check 3
|
check 3
|
|
|
ret
|
ret
|
|
|
include "pass_fail.asm"
|
include "pass_fail.asm"
|
|
|