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Chips-2.0 Demo for SP605 Development Card
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Chips-2.0 Demo for Atlys Development Card
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=========================================
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=========================================
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:Author: Jonathan P Dawson
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:Author: Jonathan P Dawson
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:Date: 2013-10-17
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:Date: 2013-10-17
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:email: chips@jondawson.org.uk
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:email: chips@jondawson.org.uk
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Stream Interconnect Conventions
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Stream Interconnect Conventions
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===============================
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===============================
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The main aims of the interface are:
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The interfaces are based on the Chips Physical Interface Convetions which are
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described in the Chips-2.0 `reference manual
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`_.
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- To be simple to implement.
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- Add little performance/logic overhead.
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- Allow designs to grow without adding extra levels of asynchronous logic.
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- Easy to interface with standard interconnects.
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::
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RST >-o-----------------------------+
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CLK >-+-o-------------------------+ |
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| | | |
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| | +-----------+ | | +--------------+
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| | | TX | | | | RX |
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| +---> | | +-----> |
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+-----> | +-------> |
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| | | |
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| | | |
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| out >=================> in |
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| | _STB | |
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| out >-----------------> in |
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| | _ACK | |
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| in <-----------------< out |
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| | | |
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+-----------+ +--------------+
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Global Signals
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--------------
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+------+-----------+------+-------------+
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| Name | Direction | Type | Description |
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+------+-----------+------+-------------+
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| CLK | input | bit | Clock |
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+------+-----------+------+-------------+
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| RST | input | bit | Reset |
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+------+-----------+------+-------------+
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Interconnect Signals
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--------------------
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+----------------+-----------+------+-----------------------------------------------------------+
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| Name | Direction | Type | Description |
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+----------------+-----------+------+-----------------------------------------------------------+
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| | TX to RX | bus | Payload Data |
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+----------------+-----------+------+-----------------------------------------------------------+
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| _STB | TX to RX | bit | '1' indicates that payload data is valid and TX is ready. |
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+----------------+-----------+------+-----------------------------------------------------------+
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| _ACK | TX to RX | bit | '1' indicates that RX is ready. |
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+----------------+-----------+------+-----------------------------------------------------------+
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Interconnect Bus Transaction
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----------------------------
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- Both transmitter and receiver shall be synchronised to the '0' -> '1' transition of CLK.
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- If RST is set to '1' upon the '0' -> '1' transition of clock the transmitter shall terminate any active bus transaction and set _STB to '0'.
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- If RST is set to '1' upon the '0' -> '1' transition of clock the receiver shall terminate any active bus transaction and set _ACK to '0'.
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- If RST is set to '0', normal operation shall commence as follows:
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- The transmitter may insert wait states on the bus by setting _STB '0'.
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- The transmitter shall set _STB to '1' to signify that data is valid.
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- Once _STB has been set to '1', it shall remain at '1' until the transaction completes.
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- The transmitter shall ensure that contains valid data for the entire period that _STB is '1'.
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- The transmitter may set to any value when _STB is '0'.
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- The receiver may insert wait states on the bus by setting _ACK to '0'.
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- The receiver shall set _ACK to '1' to signify that it is ready to receive data.
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- Once _ACK has been set to '1', it shall remain at '1' until the transaction completes.
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- Whenever _STB is '1' and _ACK are '1', a bus transaction shall complete on the following '0' -> '1' transition of CLK.
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::
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RST
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--------------------------------------------------------------
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- - - - - - - - - - - - - - -
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CLK | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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- - - - - - - - - - - - - - - -
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----- ------- ------------------------------------------------
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X VALID X
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----- ------- ------------------------------------------------
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-------
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_STB | |
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----- ------------------------------------------------
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---
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_ACK | |
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--------- ------------------------------------------------
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^^^^ RX adds wait states
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^^^^ Data transfers
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RST
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--------------------------------------------------------------
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- - - - - - - - - - - - - - -
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CLK | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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- - - - - - - - - - - - - - - -
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----- ------- ------------------------------------------------
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X VALID X
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----- ------- ------------------------------------------------
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---
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_STB | |
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--------- ------------------------------------------------
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-------
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_ACK | |
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----- ------------------------------------------------
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^^^^ TX adds wait states
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^^^^ Data transfers
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..
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- Both the transmitter and receiver may commence a new transaction without inserting any wait states.
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::
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RST
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--------------------------------------------------------------
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- - - - - - - - - - - - - - -
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CLK | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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- - - - - - - - - - - - - - - -
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----- ------- ---- ---- --------------------------------------
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X D0 X D1 X D2 X
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----- ------- ---- ---- --------------------------------------
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-------------
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_STB | |
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--------- --------------------------------------
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-----------------
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_ACK | |
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----- --------------------------------------
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^^^^ TX adds wait states
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^^^^ Data transfers
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^^^^ STB and ACK needn't return to 0 between data words
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..
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- The receiver may delay a transaction by inserting wait states until the transmitter indicates that data is available.
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- The transmitter shall not delay a transaction by inserting wait states until the receiver is ready to accept data.
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- Deadlock would occur if both the transmitter and receiver delayed a transaction until the other was ready.
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