| Line 12... |
Line 12... |
|
|
__author__ = "Jon Dawson"
|
__author__ = "Jon Dawson"
|
__copyright__ = "Copyright (C) 2013, Jonathan P Dawson"
|
__copyright__ = "Copyright (C) 2013, Jonathan P Dawson"
|
__version__ = "0.1"
|
__version__ = "0.1"
|
|
|
|
import fpu
|
|
|
def unique(l):
|
def unique(l):
|
|
|
"""In the absence of set in older python implementations, make list values unique"""
|
"""In the absence of set in older python implementations, make list values unique"""
|
|
|
return dict(zip(l, l)).keys()
|
return dict(zip(l, l)).keys()
|
| Line 82... |
Line 84... |
encoded_instruction = {}
|
encoded_instruction = {}
|
encoded_instruction["dest"] = 0
|
encoded_instruction["dest"] = 0
|
encoded_instruction["src"] = 0
|
encoded_instruction["src"] = 0
|
encoded_instruction["srcb"] = 0
|
encoded_instruction["srcb"] = 0
|
encoded_instruction["literal"] = 0
|
encoded_instruction["literal"] = 0
|
|
encoded_instruction["float"] = True
|
opcode["op"] = instruction["op"]
|
opcode["op"] = instruction["op"]
|
opcode["right"] = False
|
opcode["right"] = False
|
opcode["unsigned"] = False
|
opcode["unsigned"] = False
|
opcode["literal"] = False
|
opcode["literal"] = False
|
|
opcode["float"] = False
|
|
|
if "signed" in instruction:
|
if "signed" in instruction:
|
opcode["unsigned"] = not instruction["signed"]
|
opcode["unsigned"] = not instruction["signed"]
|
|
|
if "element_size" in instruction:
|
if "element_size" in instruction:
|
opcode["element_size"] = instruction["element_size"]
|
opcode["element_size"] = instruction["element_size"]
|
|
|
|
if "file_name" in instruction:
|
|
opcode["file_name"] = instruction["file_name"]
|
|
|
if "file" in instruction:
|
if "file" in instruction:
|
opcode["file_"] = instruction["file"]
|
opcode["file"] = instruction["file"]
|
|
|
if "line" in instruction:
|
if "line" in instruction:
|
opcode["line"] = instruction["line"]
|
opcode["line"] = instruction["line"]
|
|
|
if "input" in instruction:
|
if "input" in instruction:
|
| Line 123... |
Line 130... |
if "right" in instruction:
|
if "right" in instruction:
|
opcode["literal"] = True
|
opcode["literal"] = True
|
opcode["right"] = True
|
opcode["right"] = True
|
encoded_instruction["literal"] = instruction["right"]
|
encoded_instruction["literal"] = instruction["right"]
|
|
|
|
if "type" in instruction:
|
|
if instruction["type"] == "float":
|
|
opcode["float"] = True
|
|
encoded_instruction["float"] = True
|
|
|
if "literal" in instruction:
|
if "literal" in instruction:
|
opcode["literal"] = True
|
opcode["literal"] = True
|
encoded_instruction["literal"] = instruction["literal"]
|
encoded_instruction["literal"] = instruction["literal"]
|
|
|
if "label" in instruction:
|
if "label" in instruction:
|
| Line 243... |
Line 255... |
inports.append(("clk", 1))
|
inports.append(("clk", 1))
|
inports.append(("rst", 1))
|
inports.append(("rst", 1))
|
|
|
return inputs, outputs, input_files, output_files, testbench, inports, outports, signals
|
return inputs, outputs, input_files, output_files, testbench, inports, outports, signals
|
|
|
|
def floating_point_enables(instruction_set):
|
|
enable_adder = False
|
|
enable_multiplier = False
|
|
enable_divider = False
|
|
enable_int_to_float = False
|
|
enable_float_to_int = False
|
|
for i in instruction_set:
|
|
if i["op"] == "+" and i["float"]:
|
|
enable_adder = True
|
|
if i["op"] == "-" and i["float"]:
|
|
enable_adder = True
|
|
if i["op"] == "*" and i["float"]:
|
|
enable_multiplier = True
|
|
if i["op"] == "/" and i["float"]:
|
|
enable_divider = True
|
|
if i["op"] == "int_to_float":
|
|
enable_int_to_float = True
|
|
if i["op"] == "float_to_int":
|
|
enable_float_to_int = True
|
|
return (
|
|
enable_adder,
|
|
enable_multiplier,
|
|
enable_divider,
|
|
enable_int_to_float,
|
|
enable_float_to_int)
|
|
|
def generate_CHIP(input_file,
|
def generate_CHIP(input_file,
|
name,
|
name,
|
instructions,
|
instructions,
|
output_file,
|
output_file,
|
registers,
|
registers,
|
| Line 265... |
Line 303... |
register_bits = log2(len(registers));
|
register_bits = log2(len(registers));
|
opcode_bits = log2(len(instruction_set));
|
opcode_bits = log2(len(instruction_set));
|
instruction_bits = 32 + register_bits*2 + opcode_bits
|
instruction_bits = 32 + register_bits*2 + opcode_bits
|
declarations = generate_declarations(instructions, no_tb_mode, register_bits, opcode_bits)
|
declarations = generate_declarations(instructions, no_tb_mode, register_bits, opcode_bits)
|
inputs, outputs, input_files, output_files, testbench, inports, outports, signals = declarations
|
inputs, outputs, input_files, output_files, testbench, inports, outports, signals = declarations
|
|
enable_adder, enable_multiplier, enable_divider, enable_int_to_float, enable_float_to_int = floating_point_enables(instruction_set)
|
|
|
#output the code in verilog
|
#output the code in verilog
|
|
output_file.write("//////////////////////////////////////////////////////////////////////////////\n")
|
output_file.write("//name : %s\n"%name)
|
output_file.write("//name : %s\n"%name)
|
output_file.write("//tag : c components\n")
|
|
for i in inputs:
|
for i in inputs:
|
output_file.write("//input : input_%s:16\n"%i)
|
output_file.write("//input : input_%s:16\n"%i)
|
for i in outputs:
|
for i in outputs:
|
output_file.write("//output : output_%s:16\n"%i)
|
output_file.write("//output : output_%s:16\n"%i)
|
output_file.write("//source_file : %s\n"%input_file)
|
output_file.write("//source_file : %s\n"%input_file)
|
output_file.write("///%s\n"%"".join(["=" for i in name]))
|
output_file.write("///%s\n"%"".join(["=" for i in name]))
|
output_file.write("///\n")
|
output_file.write("///\n")
|
output_file.write("///*Created by C2CHIP*\n\n")
|
output_file.write("///Created by C2CHIP\n\n")
|
|
|
|
if enable_adder:
|
|
output_file.write(fpu.adder)
|
|
if enable_divider:
|
|
output_file.write(fpu.divider)
|
|
if enable_multiplier:
|
|
output_file.write(fpu.multiplier)
|
|
if enable_int_to_float:
|
|
output_file.write(fpu.int_to_float)
|
|
if enable_float_to_int:
|
|
output_file.write(fpu.float_to_int)
|
|
|
|
|
output_file.write("//////////////////////////////////////////////////////////////////////////////\n")
|
output_file.write("//////////////////////////////////////////////////////////////////////////////\n")
|
output_file.write("// Register Allocation\n")
|
output_file.write("// Register Allocation\n")
|
output_file.write("// ===================\n")
|
output_file.write("// ===================\n")
|
output_file.write("// %s %s %s \n"%("Register".center(20), "Name".center(20), "Size".center(20)))
|
output_file.write("// %s %s %s \n"%("Register".center(20), "Name".center(20), "Size".center(20)))
|
for register, definition in registers.iteritems():
|
for register, definition in registers.iteritems():
|
register_name, size = definition
|
register_name, size = definition
|
output_file.write("// %s %s %s \n"%(str(register).center(20), register_name.center(20), str(size).center(20)))
|
output_file.write("// %s %s %s \n"%(str(register).center(20), register_name.center(20), str(size).center(20)))
|
|
|
output_file.write(" \n`timescale 1ns/1ps\n")
|
|
output_file.write("module %s"%name)
|
output_file.write("module %s"%name)
|
|
|
all_ports = [name for name, size in inports + outports]
|
all_ports = [name for name, size in inports + outports]
|
if all_ports:
|
if all_ports:
|
output_file.write("(")
|
output_file.write("(")
|
| Line 300... |
Line 350... |
else:
|
else:
|
output_file.write(";\n")
|
output_file.write(";\n")
|
|
|
output_file.write(" integer file_count;\n")
|
output_file.write(" integer file_count;\n")
|
|
|
|
|
|
if enable_adder:
|
|
generate_adder_signals(output_file)
|
|
if enable_multiplier:
|
|
generate_multiplier_signals(output_file)
|
|
if enable_divider:
|
|
generate_divider_signals(output_file)
|
|
if enable_int_to_float:
|
|
generate_int_to_float_signals(output_file)
|
|
if enable_float_to_int:
|
|
generate_float_to_int_signals(output_file)
|
|
|
|
output_file.write(" real fp_value;\n")
|
|
if enable_adder or enable_multiplier or enable_divider or enable_int_to_float or enable_float_to_int:
|
|
output_file.write(" parameter wait_go = 2'd0,\n")
|
|
output_file.write(" write_a = 2'd1,\n")
|
|
output_file.write(" write_b = 2'd2,\n")
|
|
output_file.write(" read_z = 2'd3;\n")
|
|
|
|
|
input_files = dict(zip(input_files, ["input_file_%s"%i for i, j in enumerate(input_files)]))
|
input_files = dict(zip(input_files, ["input_file_%s"%i for i, j in enumerate(input_files)]))
|
for i in input_files.values():
|
for i in input_files.values():
|
output_file.write(" integer %s;\n"%i)
|
output_file.write(" integer %s;\n"%i)
|
|
|
output_files = dict(zip(output_files, ["output_file_%s"%i for i, j in enumerate(output_files)]))
|
output_files = dict(zip(output_files, ["output_file_%s"%i for i, j in enumerate(output_files)]))
|
| Line 372... |
Line 442... |
output_file.write(" while (1) begin\n")
|
output_file.write(" while (1) begin\n")
|
output_file.write(" #5 clk <= ~clk;\n")
|
output_file.write(" #5 clk <= ~clk;\n")
|
output_file.write(" end\n")
|
output_file.write(" end\n")
|
output_file.write(" end\n\n")
|
output_file.write(" end\n\n")
|
|
|
|
#Instance Floating Point Arithmetic
|
|
if enable_adder or enable_multiplier or enable_divider or enable_int_to_float or enable_float_to_int:
|
|
|
|
output_file.write("\n //////////////////////////////////////////////////////////////////////////////\n")
|
|
output_file.write(" // Floating Point Arithmetic \n")
|
|
output_file.write(" // \n")
|
|
output_file.write(" // Generate IEEE 754 single precision divider, adder and multiplier \n")
|
|
output_file.write(" // \n")
|
|
|
|
if enable_divider:
|
|
connect_divider(output_file)
|
|
if enable_multiplier:
|
|
connect_multiplier(output_file)
|
|
if enable_adder:
|
|
connect_adder(output_file)
|
|
if enable_int_to_float:
|
|
connect_int_to_float(output_file)
|
|
if enable_float_to_int:
|
|
connect_float_to_int(output_file)
|
|
|
|
|
|
|
#Generate a state machine to execute the instructions
|
#Generate a state machine to execute the instructions
|
binary_operators = ["+", "-", "*", "/", "|", "&", "^", "<<", ">>", "<",">", ">=",
|
binary_operators = ["+", "-", "*", "/", "|", "&", "^", "<<", ">>", "<",">", ">=",
|
"<=", "==", "!="]
|
"<=", "==", "!="]
|
|
|
|
|
| Line 462... |
Line 554... |
output_file.write(" data_out_4 <= memory_4[address_4];\n")
|
output_file.write(" data_out_4 <= memory_4[address_4];\n")
|
output_file.write(" memory_enable_4 <= 1'b0;\n\n")
|
output_file.write(" memory_enable_4 <= 1'b0;\n\n")
|
|
|
output_file.write(" write_enable_2 <= 0;\n")
|
output_file.write(" write_enable_2 <= 0;\n")
|
|
|
|
if enable_divider:
|
|
output_file.write(" divider_go <= 0;\n")
|
|
if enable_multiplier:
|
|
output_file.write(" multiplier_go <= 0;\n")
|
|
if enable_adder:
|
|
output_file.write(" adder_go <= 0;\n")
|
|
if enable_int_to_float:
|
|
output_file.write(" int_to_float_go <= 0;\n")
|
|
if enable_float_to_int:
|
|
output_file.write(" float_to_int_go <= 0;\n")
|
|
|
output_file.write(" //stage 0 instruction fetch\n")
|
output_file.write(" //stage 0 instruction fetch\n")
|
output_file.write(" if (stage_0_enable) begin\n")
|
output_file.write(" if (stage_0_enable) begin\n")
|
output_file.write(" stage_1_enable <= 1;\n")
|
output_file.write(" stage_1_enable <= 1;\n")
|
output_file.write(" instruction_0 <= instructions[program_counter];\n")
|
output_file.write(" instruction_0 <= instructions[program_counter];\n")
|
output_file.write(" opcode_0 = instruction_0[%s:%s];\n"%(
|
output_file.write(" opcode_0 = instruction_0[%s:%s];\n"%(
|
| Line 523... |
Line 626... |
output_file.write(" begin\n")
|
output_file.write(" begin\n")
|
output_file.write(" result_2 <= ~register_1;\n")
|
output_file.write(" result_2 <= ~register_1;\n")
|
output_file.write(" write_enable_2 <= 1;\n")
|
output_file.write(" write_enable_2 <= 1;\n")
|
output_file.write(" end\n\n")
|
output_file.write(" end\n\n")
|
|
|
|
elif instruction["op"] == "int_to_float":
|
|
output_file.write(" 16'd%s:\n"%(opcode))
|
|
output_file.write(" begin\n")
|
|
output_file.write(" int_to <= register_1;\n")
|
|
output_file.write(" int_to_float_go <= 1;\n")
|
|
output_file.write(" stage_0_enable <= 0;\n")
|
|
output_file.write(" stage_1_enable <= 0;\n")
|
|
output_file.write(" stage_2_enable <= 0;\n")
|
|
output_file.write(" end\n\n")
|
|
|
|
elif instruction["op"] == "float_to_int":
|
|
output_file.write(" 16'd%s:\n"%(opcode))
|
|
output_file.write(" begin\n")
|
|
output_file.write(" float_to <= register_1;\n")
|
|
output_file.write(" float_to_int_go <= 1;\n")
|
|
output_file.write(" stage_0_enable <= 0;\n")
|
|
output_file.write(" stage_1_enable <= 0;\n")
|
|
output_file.write(" stage_2_enable <= 0;\n")
|
|
output_file.write(" end\n\n")
|
|
|
elif instruction["op"] in binary_operators:
|
elif instruction["op"] in binary_operators:
|
if instruction["literal"]:
|
if instruction["literal"]:
|
if instruction["unsigned"]:
|
if instruction["float"]:
|
|
output_file.write(" 16'd%s:\n"%(opcode))
|
|
output_file.write(" begin\n")
|
|
if instruction["op"] == "/":
|
|
if instruction["right"]:
|
|
output_file.write(" divider_a <= register_1;\n")
|
|
output_file.write(" divider_b <= literal_1;\n")
|
|
else:
|
|
output_file.write(" divider_a <= literal_1;\n")
|
|
output_file.write(" divider_b <= register_1;\n")
|
|
output_file.write(" divider_go <= 1;\n")
|
|
elif instruction["op"] == "*":
|
|
if instruction["right"]:
|
|
output_file.write(" multiplier_a <= register_1;\n")
|
|
output_file.write(" multiplier_b <= literal_1;\n")
|
|
else:
|
|
output_file.write(" multiplier_a <= literal_1;\n")
|
|
output_file.write(" multiplier_b <= register_1;\n")
|
|
output_file.write(" multiplier_go <= 1;\n")
|
|
elif instruction["op"] == "+":
|
|
if instruction["right"]:
|
|
output_file.write(" adder_a <= register_1;\n")
|
|
output_file.write(" adder_b <= literal_1;\n")
|
|
else:
|
|
output_file.write(" adder_a <= literal_1;\n")
|
|
output_file.write(" adder_b <= register_1;\n")
|
|
output_file.write(" adder_go <= 1;\n")
|
|
elif instruction["op"] == "-":
|
|
if instruction["right"]:
|
|
output_file.write(" adder_a <= register_1;\n")
|
|
output_file.write(" adder_b <= {~literal_1[31], literal_1[30:0]};\n")
|
|
else:
|
|
output_file.write(" adder_a <= literal_1;\n")
|
|
output_file.write(" adder_b <= {~register_1[31], register_1[30:0]};\n")
|
|
output_file.write(" adder_go <= 1;\n")
|
|
output_file.write(" stage_0_enable <= 0;\n")
|
|
output_file.write(" stage_1_enable <= 0;\n")
|
|
output_file.write(" stage_2_enable <= 0;\n")
|
|
output_file.write(" end\n\n")
|
|
elif instruction["unsigned"]:
|
output_file.write(" 16'd%s:\n"%(opcode))
|
output_file.write(" 16'd%s:\n"%(opcode))
|
output_file.write(" begin\n")
|
output_file.write(" begin\n")
|
if instruction["right"]:
|
if instruction["right"]:
|
output_file.write(" result_2 <= $unsigned(register_1) %s $unsigned(literal_1);\n"%(instruction["op"]))
|
output_file.write(" result_2 <= $unsigned(register_1) %s $unsigned(literal_1);\n"%(instruction["op"]))
|
else:
|
else:
|
| Line 546... |
Line 708... |
else:
|
else:
|
output_file.write(" result_2 <= $signed(literal_1) %s $signed(register_1);\n"%(instruction["op"]))
|
output_file.write(" result_2 <= $signed(literal_1) %s $signed(register_1);\n"%(instruction["op"]))
|
output_file.write(" write_enable_2 <= 1;\n")
|
output_file.write(" write_enable_2 <= 1;\n")
|
output_file.write(" end\n\n")
|
output_file.write(" end\n\n")
|
else:
|
else:
|
if instruction["unsigned"]:
|
if instruction["float"]:
|
|
output_file.write(" 16'd%s:\n"%(opcode))
|
|
output_file.write(" begin\n")
|
|
if instruction["op"] == "/":
|
|
output_file.write(" divider_a <= register_1;\n")
|
|
output_file.write(" divider_b <= registerb_1;\n")
|
|
output_file.write(" divider_go <= 1;\n")
|
|
elif instruction["op"] == "*":
|
|
output_file.write(" multiplier_a <= register_1;\n")
|
|
output_file.write(" multiplier_b <= registerb_1;\n")
|
|
output_file.write(" multiplier_go <= 1;\n")
|
|
elif instruction["op"] == "+":
|
|
output_file.write(" adder_a <= register_1;\n")
|
|
output_file.write(" adder_b <= registerb_1;\n")
|
|
output_file.write(" adder_go <= 1;\n")
|
|
elif instruction["op"] == "-":
|
|
output_file.write(" adder_a <= register_1;\n")
|
|
output_file.write(" adder_b <= {~registerb_1[31], registerb_1[30:0]};\n")
|
|
output_file.write(" adder_go <= 1;\n")
|
|
output_file.write(" stage_0_enable <= 0;\n")
|
|
output_file.write(" stage_1_enable <= 0;\n")
|
|
output_file.write(" stage_2_enable <= 0;\n")
|
|
output_file.write(" end\n\n")
|
|
elif instruction["unsigned"]:
|
output_file.write(" 16'd%s:\n"%(opcode))
|
output_file.write(" 16'd%s:\n"%(opcode))
|
output_file.write(" begin\n")
|
output_file.write(" begin\n")
|
output_file.write(" result_2 <= $unsigned(register_1) %s $unsigned(registerb_1);\n"%(instruction["op"]))
|
output_file.write(" result_2 <= $unsigned(register_1) %s $unsigned(registerb_1);\n"%(instruction["op"]))
|
output_file.write(" write_enable_2 <= 1;\n")
|
output_file.write(" write_enable_2 <= 1;\n")
|
output_file.write(" end\n\n")
|
output_file.write(" end\n\n")
|
| Line 616... |
Line 801... |
|
|
elif instruction["op"] == "file_read":
|
elif instruction["op"] == "file_read":
|
output_file.write(" 16'd%s:\n"%(opcode))
|
output_file.write(" 16'd%s:\n"%(opcode))
|
output_file.write(" begin\n")
|
output_file.write(" begin\n")
|
output_file.write(" file_count = $fscanf(%s, \"%%d\\n\", result_2);\n"%(
|
output_file.write(" file_count = $fscanf(%s, \"%%d\\n\", result_2);\n"%(
|
input_files[instruction["file_"]]))
|
input_files[instruction["file_name"]]))
|
output_file.write(" write_enable_2 <= 1;\n")
|
output_file.write(" write_enable_2 <= 1;\n")
|
output_file.write(" end\n\n")
|
output_file.write(" end\n\n")
|
|
|
elif instruction["op"] == "file_write":
|
elif instruction["op"] == "file_write":
|
output_file.write(" 16'd%s:\n"%(opcode))
|
output_file.write(" 16'd%s:\n"%(opcode))
|
output_file.write(" begin\n")
|
output_file.write(" begin\n")
|
|
if instruction["float"]:
|
|
output_file.write(' fp_value = (register_1[31]?-1.0:1.0) *\n')
|
|
output_file.write(' (2.0 ** (register_1[30:23]-127.0)) *\n')
|
|
output_file.write(' ({1\'d1, register_1[22:0]} / (2.0**23));\n')
|
|
output_file.write(' $fdisplay (%s, "%%f", fp_value);\n'%(
|
|
output_files[instruction["file_name"]]))
|
|
else:
|
output_file.write(" $fdisplay(%s, \"%%d\", register_1);\n"%(
|
output_file.write(" $fdisplay(%s, \"%%d\", register_1);\n"%(
|
output_files[instruction["file_name"]]))
|
output_files[instruction["file_name"]]))
|
output_file.write(" end\n\n")
|
output_file.write(" end\n\n")
|
|
|
elif instruction["op"] == "read":
|
elif instruction["op"] == "read":
|
| Line 690... |
Line 882... |
output_file.write(" 16'd%s:\n"%(opcode))
|
output_file.write(" 16'd%s:\n"%(opcode))
|
output_file.write(" begin\n")
|
output_file.write(" begin\n")
|
output_file.write(" if (register_1 == 0) begin\n")
|
output_file.write(" if (register_1 == 0) begin\n")
|
output_file.write(" $display(\"Assertion failed at line: %s in file: %s\");\n"%(
|
output_file.write(" $display(\"Assertion failed at line: %s in file: %s\");\n"%(
|
instruction["line"],
|
instruction["line"],
|
instruction["file_"]))
|
instruction["file"]))
|
output_file.write(" $finish_and_return(1);\n")
|
output_file.write(" $finish_and_return(1);\n")
|
output_file.write(" end\n")
|
output_file.write(" end\n")
|
output_file.write(" end\n\n")
|
output_file.write(" end\n\n")
|
|
|
elif instruction["op"] == "wait_clocks":
|
elif instruction["op"] == "wait_clocks":
|
| Line 708... |
Line 900... |
output_file.write(" end\n\n")
|
output_file.write(" end\n\n")
|
|
|
elif instruction["op"] == "report":
|
elif instruction["op"] == "report":
|
output_file.write(" 16'd%s:\n"%(opcode))
|
output_file.write(" 16'd%s:\n"%(opcode))
|
output_file.write(" begin\n")
|
output_file.write(" begin\n")
|
if instruction["unsigned"]:
|
if instruction["float"]:
|
|
|
|
output_file.write(' fp_value = (register_1[31]?-1.0:1.0) *\n')
|
|
output_file.write(' (2.0 ** (register_1[30:23]-127.0)) *\n')
|
|
output_file.write(' ({1\'d1, register_1[22:0]} / (2.0**23));\n')
|
|
|
|
output_file.write(' $display ("%%f (report at line: %s in file: %s)", fp_value);\n'%(
|
|
instruction["line"],
|
|
instruction["file"]))
|
|
|
|
elif instruction["unsigned"]:
|
|
|
output_file.write(' $display ("%%d (report at line: %s in file: %s)", $unsigned(register_1));\n'%(
|
output_file.write(' $display ("%%d (report at line: %s in file: %s)", $unsigned(register_1));\n'%(
|
instruction["line"],
|
instruction["line"],
|
instruction["file_"]))
|
instruction["file"]))
|
|
|
else:
|
else:
|
|
|
output_file.write(' $display ("%%d (report at line: %s in file: %s)", $signed(register_1));\n'%(
|
output_file.write(' $display ("%%d (report at line: %s in file: %s)", $signed(register_1));\n'%(
|
instruction["line"],
|
instruction["line"],
|
instruction["file_"],))
|
instruction["file"],))
|
|
|
output_file.write(" end\n\n")
|
output_file.write(" end\n\n")
|
|
|
elif instruction["op"] == "stop":
|
elif instruction["op"] == "stop":
|
#If we are in testbench mode stop the simulation
|
#If we are in testbench mode stop the simulation
|
#If we are part of a larger design, other C programs may still be running
|
#If we are part of a larger design, other C programs may still be running
|
| Line 773... |
Line 979... |
output_file.write(" end\n")
|
output_file.write(" end\n")
|
output_file.write(" end else begin\n")
|
output_file.write(" end else begin\n")
|
output_file.write(" timer <= timer - 1;\n")
|
output_file.write(" timer <= timer - 1;\n")
|
output_file.write(" end\n\n")
|
output_file.write(" end\n\n")
|
|
|
|
|
|
if enable_adder:
|
|
output_file.write(" if (adder_done) begin\n")
|
|
output_file.write(" write_enable_2 <= 1;\n")
|
|
output_file.write(" stage_0_enable <= 1;\n")
|
|
output_file.write(" stage_1_enable <= 1;\n")
|
|
output_file.write(" stage_2_enable <= 1;\n")
|
|
output_file.write(" end\n\n")
|
|
|
|
if enable_multiplier:
|
|
output_file.write(" if (multiplier_done) begin\n")
|
|
output_file.write(" write_enable_2 <= 1;\n")
|
|
output_file.write(" stage_0_enable <= 1;\n")
|
|
output_file.write(" stage_1_enable <= 1;\n")
|
|
output_file.write(" stage_2_enable <= 1;\n")
|
|
output_file.write(" end\n\n")
|
|
|
|
if enable_divider:
|
|
output_file.write(" if (divider_done) begin\n")
|
|
output_file.write(" write_enable_2 <= 1;\n")
|
|
output_file.write(" stage_0_enable <= 1;\n")
|
|
output_file.write(" stage_1_enable <= 1;\n")
|
|
output_file.write(" stage_2_enable <= 1;\n")
|
|
output_file.write(" end\n\n")
|
|
|
|
if enable_int_to_float:
|
|
output_file.write(" if (int_to_float_done) begin\n")
|
|
output_file.write(" write_enable_2 <= 1;\n")
|
|
output_file.write(" stage_0_enable <= 1;\n")
|
|
output_file.write(" stage_1_enable <= 1;\n")
|
|
output_file.write(" stage_2_enable <= 1;\n")
|
|
output_file.write(" end\n\n")
|
|
|
|
if enable_float_to_int:
|
|
output_file.write(" if (float_to_int_done) begin\n")
|
|
output_file.write(" write_enable_2 <= 1;\n")
|
|
output_file.write(" stage_0_enable <= 1;\n")
|
|
output_file.write(" stage_1_enable <= 1;\n")
|
|
output_file.write(" stage_2_enable <= 1;\n")
|
|
output_file.write(" end\n\n")
|
|
|
#Reset program counter and control signals
|
#Reset program counter and control signals
|
output_file.write(" if (rst == 1'b1) begin\n")
|
output_file.write(" if (rst == 1'b1) begin\n")
|
output_file.write(" stage_0_enable <= 1;\n")
|
output_file.write(" stage_0_enable <= 1;\n")
|
output_file.write(" stage_1_enable <= 0;\n")
|
output_file.write(" stage_1_enable <= 0;\n")
|
output_file.write(" stage_2_enable <= 0;\n")
|
output_file.write(" stage_2_enable <= 0;\n")
|
| Line 796... |
Line 1043... |
output_file.write(" assign output_%s = s_output_%s;\n"%(i, i))
|
output_file.write(" assign output_%s = s_output_%s;\n"%(i, i))
|
output_file.write("\nendmodule\n")
|
output_file.write("\nendmodule\n")
|
|
|
return inputs, outputs
|
return inputs, outputs
|
|
|
No newline at end of file
|
No newline at end of file
|
|
def connect_float_to_int(output_file):
|
|
output_file.write(" \n float_to_int float_to_int_1(\n")
|
|
output_file.write(" .clk(clk),\n")
|
|
output_file.write(" .rst(rst),\n")
|
|
output_file.write(" .input_a(float_to),\n")
|
|
output_file.write(" .input_a_stb(float_to_stb),\n")
|
|
output_file.write(" .input_a_ack(float_to_ack),\n")
|
|
output_file.write(" .output_z(to_int),\n")
|
|
output_file.write(" .output_z_stb(to_int_stb),\n")
|
|
output_file.write(" .output_z_ack(to_int_ack)\n")
|
|
output_file.write(" );\n\n")
|
|
output_file.write(" \n always @(posedge clk)\n")
|
|
output_file.write(" begin\n\n")
|
|
output_file.write(" float_to_int_done <= 0;\n")
|
|
output_file.write(" case(float_to_int_state)\n\n")
|
|
output_file.write(" wait_go:\n")
|
|
output_file.write(" begin\n")
|
|
output_file.write(" if (float_to_int_go) begin\n")
|
|
output_file.write(" float_to_int_state <= write_a;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n\n")
|
|
output_file.write(" write_a:\n")
|
|
output_file.write(" begin\n")
|
|
output_file.write(" float_to_stb <= 1;\n")
|
|
output_file.write(" if (float_to_stb && float_to_ack) begin\n")
|
|
output_file.write(" float_to_stb <= 0;\n")
|
|
output_file.write(" float_to_int_state <= read_z;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n\n")
|
|
output_file.write(" read_z:\n")
|
|
output_file.write(" begin\n")
|
|
output_file.write(" to_int_ack <= 1;\n")
|
|
output_file.write(" if (to_int_stb && to_int_ack) begin\n")
|
|
output_file.write(" to_int_ack <= 0;\n")
|
|
output_file.write(" result_2 <= to_int;\n")
|
|
output_file.write(" float_to_int_state <= wait_go;\n")
|
|
output_file.write(" float_to_int_done <= 1;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" endcase\n")
|
|
output_file.write(" if (rst) begin\n")
|
|
output_file.write(" float_to_int_state <= wait_go;\n")
|
|
output_file.write(" float_to_stb <= 0;\n")
|
|
output_file.write(" to_int_ack <= 0;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n\n")
|
|
|
|
def connect_int_to_float(output_file):
|
|
output_file.write(" \n int_to_float int_to_float_1(\n")
|
|
output_file.write(" .clk(clk),\n")
|
|
output_file.write(" .rst(rst),\n")
|
|
output_file.write(" .input_a(int_to),\n")
|
|
output_file.write(" .input_a_stb(int_to_stb),\n")
|
|
output_file.write(" .input_a_ack(int_to_ack),\n")
|
|
output_file.write(" .output_z(to_float),\n")
|
|
output_file.write(" .output_z_stb(to_float_stb),\n")
|
|
output_file.write(" .output_z_ack(to_float_ack)\n")
|
|
output_file.write(" );\n\n")
|
|
output_file.write(" \n always @(posedge clk)\n")
|
|
output_file.write(" begin\n\n")
|
|
output_file.write(" int_to_float_done <= 0;\n")
|
|
output_file.write(" case(int_to_float_state)\n\n")
|
|
output_file.write(" wait_go:\n")
|
|
output_file.write(" begin\n")
|
|
output_file.write(" if (int_to_float_go) begin\n")
|
|
output_file.write(" int_to_float_state <= write_a;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n\n")
|
|
output_file.write(" write_a:\n")
|
|
output_file.write(" begin\n")
|
|
output_file.write(" int_to_stb <= 1;\n")
|
|
output_file.write(" if (int_to_stb && int_to_ack) begin\n")
|
|
output_file.write(" int_to_stb <= 0;\n")
|
|
output_file.write(" int_to_float_state <= read_z;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n\n")
|
|
output_file.write(" read_z:\n")
|
|
output_file.write(" begin\n")
|
|
output_file.write(" to_float_ack <= 1;\n")
|
|
output_file.write(" if (to_float_stb && to_float_ack) begin\n")
|
|
output_file.write(" to_float_ack <= 0;\n")
|
|
output_file.write(" result_2 <= to_float;\n")
|
|
output_file.write(" int_to_float_state <= wait_go;\n")
|
|
output_file.write(" int_to_float_done <= 1;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" endcase\n")
|
|
output_file.write(" if (rst) begin\n")
|
|
output_file.write(" int_to_float_state <= wait_go;\n")
|
|
output_file.write(" int_to_stb <= 0;\n")
|
|
output_file.write(" to_float_ack <= 0;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n\n")
|
|
|
|
def connect_divider(output_file):
|
|
output_file.write(" \n divider divider_1(\n")
|
|
output_file.write(" .clk(clk),\n")
|
|
output_file.write(" .rst(rst),\n")
|
|
output_file.write(" .input_a(divider_a),\n")
|
|
output_file.write(" .input_a_stb(divider_a_stb),\n")
|
|
output_file.write(" .input_a_ack(divider_a_ack),\n")
|
|
output_file.write(" .input_b(divider_b),\n")
|
|
output_file.write(" .input_b_stb(divider_b_stb),\n")
|
|
output_file.write(" .input_b_ack(divider_b_ack),\n")
|
|
output_file.write(" .output_z(divider_z),\n")
|
|
output_file.write(" .output_z_stb(divider_z_stb),\n")
|
|
output_file.write(" .output_z_ack(divider_z_ack)\n")
|
|
output_file.write(" );\n\n")
|
|
output_file.write(" \n always @(posedge clk)\n")
|
|
output_file.write(" begin\n\n")
|
|
output_file.write(" divider_done <= 0;\n")
|
|
output_file.write(" case(div_state)\n\n")
|
|
output_file.write(" wait_go:\n")
|
|
output_file.write(" begin\n")
|
|
output_file.write(" if (divider_go) begin\n")
|
|
output_file.write(" div_state <= write_a;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n\n")
|
|
output_file.write(" write_a:\n")
|
|
output_file.write(" begin\n")
|
|
output_file.write(" divider_a_stb <= 1;\n")
|
|
output_file.write(" if (divider_a_stb && divider_a_ack) begin\n")
|
|
output_file.write(" divider_a_stb <= 0;\n")
|
|
output_file.write(" div_state <= write_b;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n\n")
|
|
output_file.write(" write_b:\n")
|
|
output_file.write(" begin\n")
|
|
output_file.write(" divider_b_stb <= 1;\n")
|
|
output_file.write(" if (divider_b_stb && divider_b_ack) begin\n")
|
|
output_file.write(" divider_b_stb <= 0;\n")
|
|
output_file.write(" div_state <= read_z;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n\n")
|
|
output_file.write(" read_z:\n")
|
|
output_file.write(" begin\n")
|
|
output_file.write(" divider_z_ack <= 1;\n")
|
|
output_file.write(" if (divider_z_stb && divider_z_ack) begin\n")
|
|
output_file.write(" divider_z_ack <= 0;\n")
|
|
output_file.write(" result_2 <= divider_z;\n")
|
|
output_file.write(" div_state <= wait_go;\n")
|
|
output_file.write(" divider_done <= 1;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" endcase\n")
|
|
output_file.write(" if (rst) begin\n")
|
|
output_file.write(" div_state <= wait_go;\n")
|
|
output_file.write(" divider_a_stb <= 0;\n")
|
|
output_file.write(" divider_b_stb <= 0;\n")
|
|
output_file.write(" divider_z_ack <= 0;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n\n")
|
|
|
|
def connect_multiplier(output_file):
|
|
output_file.write(" \n multiplier multiplier_1(\n")
|
|
output_file.write(" .clk(clk),\n")
|
|
output_file.write(" .rst(rst),\n")
|
|
output_file.write(" .input_a(multiplier_a),\n")
|
|
output_file.write(" .input_a_stb(multiplier_a_stb),\n")
|
|
output_file.write(" .input_a_ack(multiplier_a_ack),\n")
|
|
output_file.write(" .input_b(multiplier_b),\n")
|
|
output_file.write(" .input_b_stb(multiplier_b_stb),\n")
|
|
output_file.write(" .input_b_ack(multiplier_b_ack),\n")
|
|
output_file.write(" .output_z(multiplier_z),\n")
|
|
output_file.write(" .output_z_stb(multiplier_z_stb),\n")
|
|
output_file.write(" .output_z_ack(multiplier_z_ack)\n")
|
|
output_file.write(" );\n\n")
|
|
output_file.write(" \n always @(posedge clk)\n")
|
|
output_file.write(" begin\n\n")
|
|
output_file.write(" multiplier_done <= 0;\n")
|
|
output_file.write(" case(mul_state)\n\n")
|
|
output_file.write(" wait_go:\n")
|
|
output_file.write(" begin\n")
|
|
output_file.write(" if (multiplier_go) begin\n")
|
|
output_file.write(" mul_state <= write_a;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n\n")
|
|
output_file.write(" write_a:\n")
|
|
output_file.write(" begin\n")
|
|
output_file.write(" multiplier_a_stb <= 1;\n")
|
|
output_file.write(" if (multiplier_a_stb && multiplier_a_ack) begin\n")
|
|
output_file.write(" multiplier_a_stb <= 0;\n")
|
|
output_file.write(" mul_state <= write_b;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n\n")
|
|
output_file.write(" write_b:\n")
|
|
output_file.write(" begin\n")
|
|
output_file.write(" multiplier_b_stb <= 1;\n")
|
|
output_file.write(" if (multiplier_b_stb && multiplier_b_ack) begin\n")
|
|
output_file.write(" multiplier_b_stb <= 0;\n")
|
|
output_file.write(" mul_state <= read_z;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n\n")
|
|
output_file.write(" read_z:\n")
|
|
output_file.write(" begin\n")
|
|
output_file.write(" multiplier_z_ack <= 1;\n")
|
|
output_file.write(" if (multiplier_z_stb && multiplier_z_ack) begin\n")
|
|
output_file.write(" multiplier_z_ack <= 0;\n")
|
|
output_file.write(" result_2 <= multiplier_z;\n")
|
|
output_file.write(" mul_state <= wait_go;\n")
|
|
output_file.write(" multiplier_done <= 1;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n\n")
|
|
output_file.write(" endcase\n\n")
|
|
output_file.write(" if (rst) begin\n")
|
|
output_file.write(" mul_state <= wait_go;\n")
|
|
output_file.write(" multiplier_a_stb <= 0;\n")
|
|
output_file.write(" multiplier_b_stb <= 0;\n")
|
|
output_file.write(" multiplier_z_ack <= 0;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n\n")
|
|
|
|
def connect_adder(output_file):
|
|
output_file.write(" \n adder adder_1(\n")
|
|
output_file.write(" .clk(clk),\n")
|
|
output_file.write(" .rst(rst),\n")
|
|
output_file.write(" .input_a(adder_a),\n")
|
|
output_file.write(" .input_a_stb(adder_a_stb),\n")
|
|
output_file.write(" .input_a_ack(adder_a_ack),\n")
|
|
output_file.write(" .input_b(adder_b),\n")
|
|
output_file.write(" .input_b_stb(adder_b_stb),\n")
|
|
output_file.write(" .input_b_ack(adder_b_ack),\n")
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output_file.write(" .output_z(adder_z),\n")
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output_file.write(" .output_z_stb(adder_z_stb),\n")
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output_file.write(" .output_z_ack(adder_z_ack)\n")
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output_file.write(" );\n\n")
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output_file.write(" \n always @(posedge clk)\n")
|
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output_file.write(" begin\n\n")
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output_file.write(" adder_done <= 0;\n")
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output_file.write(" case(add_state)\n\n")
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output_file.write(" wait_go:\n")
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output_file.write(" begin\n")
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output_file.write(" if (adder_go) begin\n")
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output_file.write(" add_state <= write_a;\n")
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output_file.write(" end\n")
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output_file.write(" end\n\n")
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output_file.write(" write_a:\n")
|
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output_file.write(" begin\n")
|
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output_file.write(" adder_a_stb <= 1;\n")
|
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output_file.write(" if (adder_a_stb && adder_a_ack) begin\n")
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output_file.write(" adder_a_stb <= 0;\n")
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output_file.write(" add_state <= write_b;\n")
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output_file.write(" end\n")
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|
output_file.write(" end\n\n")
|
|
output_file.write(" write_b:\n")
|
|
output_file.write(" begin\n")
|
|
output_file.write(" adder_b_stb <= 1;\n")
|
|
output_file.write(" if (adder_b_stb && adder_b_ack) begin\n")
|
|
output_file.write(" adder_b_stb <= 0;\n")
|
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output_file.write(" add_state <= read_z;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n\n")
|
|
output_file.write(" read_z:\n")
|
|
output_file.write(" begin\n")
|
|
output_file.write(" adder_z_ack <= 1;\n")
|
|
output_file.write(" if (adder_z_stb && adder_z_ack) begin\n")
|
|
output_file.write(" adder_z_ack <= 0;\n")
|
|
output_file.write(" result_2 <= adder_z;\n")
|
|
output_file.write(" add_state <= wait_go;\n")
|
|
output_file.write(" adder_done <= 1;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" endcase\n")
|
|
output_file.write(" if (rst) begin\n")
|
|
output_file.write(" add_state <= wait_go;\n")
|
|
output_file.write(" adder_a_stb <= 0;\n")
|
|
output_file.write(" adder_b_stb <= 0;\n")
|
|
output_file.write(" adder_z_ack <= 0;\n")
|
|
output_file.write(" end\n")
|
|
output_file.write(" end\n\n")
|
|
|
|
def generate_float_to_int_signals(output_file):
|
|
output_file.write(" reg [31:0] float_to;\n")
|
|
output_file.write(" reg float_to_stb;\n")
|
|
output_file.write(" wire float_to_ack;\n")
|
|
output_file.write(" wire [31:0] to_int;\n")
|
|
output_file.write(" wire to_int_stb;\n")
|
|
output_file.write(" reg to_int_ack;\n")
|
|
output_file.write(" reg [1:0] float_to_int_state;\n")
|
|
output_file.write(" reg float_to_int_go;\n")
|
|
output_file.write(" reg float_to_int_done;\n")
|
|
|
|
def generate_int_to_float_signals(output_file):
|
|
output_file.write(" reg [31:0] int_to;\n")
|
|
output_file.write(" reg int_to_stb;\n")
|
|
output_file.write(" wire int_to_ack;\n")
|
|
output_file.write(" wire [31:0] to_float;\n")
|
|
output_file.write(" wire to_float_stb;\n")
|
|
output_file.write(" reg to_float_ack;\n")
|
|
output_file.write(" reg [1:0] int_to_float_state;\n")
|
|
output_file.write(" reg int_to_float_go;\n")
|
|
output_file.write(" reg int_to_float_done;\n")
|
|
|
|
def generate_divider_signals(output_file):
|
|
output_file.write(" reg [31:0] divider_a;\n")
|
|
output_file.write(" reg divider_a_stb;\n")
|
|
output_file.write(" wire divider_a_ack;\n")
|
|
output_file.write(" reg [31:0] divider_b;\n")
|
|
output_file.write(" reg divider_b_stb;\n")
|
|
output_file.write(" wire divider_b_ack;\n")
|
|
output_file.write(" wire [31:0] divider_z;\n")
|
|
output_file.write(" wire divider_z_stb;\n")
|
|
output_file.write(" reg divider_z_ack;\n")
|
|
output_file.write(" reg [1:0] div_state;\n")
|
|
output_file.write(" reg divider_go;\n")
|
|
output_file.write(" reg divider_done;\n")
|
|
|
|
def generate_multiplier_signals(output_file):
|
|
output_file.write(" reg [31:0] multiplier_a;\n")
|
|
output_file.write(" reg multiplier_a_stb;\n")
|
|
output_file.write(" wire multiplier_a_ack;\n")
|
|
output_file.write(" reg [31:0] multiplier_b;\n")
|
|
output_file.write(" reg multiplier_b_stb;\n")
|
|
output_file.write(" wire multiplier_b_ack;\n")
|
|
output_file.write(" wire [31:0] multiplier_z;\n")
|
|
output_file.write(" wire multiplier_z_stb;\n")
|
|
output_file.write(" reg multiplier_z_ack;\n")
|
|
output_file.write(" reg [1:0] mul_state;\n")
|
|
output_file.write(" reg multiplier_go;\n")
|
|
output_file.write(" reg multiplier_done;\n")
|
|
|
|
def generate_adder_signals(output_file):
|
|
output_file.write(" reg [31:0] adder_a;\n")
|
|
output_file.write(" reg adder_a_stb;\n")
|
|
output_file.write(" wire adder_a_ack;\n")
|
|
output_file.write(" reg [31:0] adder_b;\n")
|
|
output_file.write(" reg adder_b_stb;\n")
|
|
output_file.write(" wire adder_b_ack;\n")
|
|
output_file.write(" wire [31:0] adder_z;\n")
|
|
output_file.write(" wire adder_z_stb;\n")
|
|
output_file.write(" reg adder_z_ack;\n")
|
|
output_file.write(" reg [1:0] add_state;\n")
|
|
output_file.write(" reg adder_go;\n")
|
|
output_file.write(" reg adder_done;\n")
|
|
|
No newline at end of file
|
No newline at end of file
|
