------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- --
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-- --
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-- This is the 68000 software compatible Kernal of TG68 --
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-- This is the 68000 software compatible Kernal of TG68 --
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-- --
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-- --
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-- Copyright (c) 2007 Tobias Gubener <tobiflex@opencores.org> --
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-- Copyright (c) 2007-2010 Tobias Gubener <tobiflex@opencores.org> --
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-- --
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-- --
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-- This source file is free software: you can redistribute it and/or modify --
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-- This source file is free software: you can redistribute it and/or modify --
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-- it under the terms of the GNU Lesser General Public License as published --
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-- it under the terms of the GNU Lesser General Public License as published --
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-- by the Free Software Foundation, either version 3 of the License, or --
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-- by the Free Software Foundation, either version 3 of the License, or --
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-- (at your option) any later version. --
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-- (at your option) any later version. --
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-- --
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-- --
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-- This source file is distributed in the hope that it will be useful, --
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-- This source file is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License for more details. --
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-- GNU General Public License for more details. --
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-- --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-- --
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-- --
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--
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--
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-- Revision 1.08 2010/06/14
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-- Bugfix Movem with regmask==xFFFF
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-- Add missing Illegal $4AFC
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--
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-- Revision 1.07 2009/10/02
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-- Bugfix Movem with regmask==x0000
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--
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-- Revision 1.06 2009/02/10
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-- Revision 1.06 2009/02/10
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-- Bugfix shift and rotations opcodes when the bitcount and the data are in the same register:
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-- Bugfix shift and rotations opcodes when the bitcount and the data are in the same register:
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-- Example lsr.l D2,D2
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-- Example lsr.l D2,D2
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-- Thanks to Peter Graf for report
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-- Thanks to Peter Graf for report
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--
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--
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-- Revision 1.05 2009/01/26
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-- Revision 1.05 2009/01/26
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-- Implement missing RTR
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-- Implement missing RTR
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-- Thanks to Peter Graf for report
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-- Thanks to Peter Graf for report
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--
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--
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-- Revision 1.04 2007/12/29
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-- Revision 1.04 2007/12/29
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-- size improvement
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-- size improvement
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-- change signal "microaddr" to one hot state machine
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-- change signal "microaddr" to one hot state machine
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--
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--
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-- Revision 1.03 2007/12/21
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-- Revision 1.03 2007/12/21
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-- Thanks to Andreas Ehliar
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-- Thanks to Andreas Ehliar
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-- Split regfile to use blockram for registers
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-- Split regfile to use blockram for registers
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-- insert "WHEN OTHERS => null;" on END CASE;
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-- insert "WHEN OTHERS => null;" on END CASE;
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--
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--
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-- Revision 1.02 2007/12/17
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-- Revision 1.02 2007/12/17
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-- Bugfix jsr nn.w
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-- Bugfix jsr nn.w
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--
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--
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-- Revision 1.01 2007/11/28
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-- Revision 1.01 2007/11/28
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-- add MOVEP
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-- add MOVEP
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-- Bugfix Interrupt in MOVEQ
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-- Bugfix Interrupt in MOVEQ
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--
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--
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-- Revision 1.0 2007/11/05
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-- Revision 1.0 2007/11/05
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-- Clean up code and first release
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-- Clean up code and first release
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--
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--
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-- known bugs/todo:
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-- known bugs/todo:
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-- Add CHK INSTRUCTION
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-- Add CHK INSTRUCTION
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-- full decode ILLEGAL INSTRUCTIONS
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-- full decode ILLEGAL INSTRUCTIONS
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-- Add FC Output
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-- Add FC Output
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-- add odd Address test
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-- add odd Address test
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-- add TRACE
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-- add TRACE
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-- Movem with regmask==x0000
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity TG68_fast is
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entity TG68_fast is
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset : in std_logic; --low active
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reset : in std_logic; --low active
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clkena_in : in std_logic:='1';
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clkena_in : in std_logic:='1';
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data_in : in std_logic_vector(15 downto 0);
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data_in : in std_logic_vector(15 downto 0);
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IPL : in std_logic_vector(2 downto 0):="111";
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IPL : in std_logic_vector(2 downto 0):="111";
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test_IPL : in std_logic:='0'; --only for debugging
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test_IPL : in std_logic:='0'; --only for debugging
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address : out std_logic_vector(31 downto 0);
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address : out std_logic_vector(31 downto 0);
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data_write : out std_logic_vector(15 downto 0);
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data_write : out std_logic_vector(15 downto 0);
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state_out : out std_logic_vector(1 downto 0);
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state_out : out std_logic_vector(1 downto 0);
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LDS, UDS : out std_logic;
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LDS, UDS : out std_logic;
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decodeOPC : buffer std_logic;
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decodeOPC : buffer std_logic;
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wr : out std_logic
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wr : out std_logic
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);
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);
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end TG68_fast;
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end TG68_fast;
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architecture logic of TG68_fast is
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architecture logic of TG68_fast is
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signal state : std_logic_vector(1 downto 0);
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signal state : std_logic_vector(1 downto 0);
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signal clkena : std_logic;
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signal clkena : std_logic;
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signal TG68_PC : std_logic_vector(31 downto 0);
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signal TG68_PC : std_logic_vector(31 downto 0);
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signal TG68_PC_add : std_logic_vector(31 downto 0);
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signal TG68_PC_add : std_logic_vector(31 downto 0);
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signal memaddr : std_logic_vector(31 downto 0);
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signal memaddr : std_logic_vector(31 downto 0);
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signal memaddr_in : std_logic_vector(31 downto 0);
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signal memaddr_in : std_logic_vector(31 downto 0);
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signal ea_data : std_logic_vector(31 downto 0);
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signal ea_data : std_logic_vector(31 downto 0);
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signal ea_data_OP1 : std_logic;
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signal ea_data_OP1 : std_logic;
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signal setaddrlong : std_logic;
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signal setaddrlong : std_logic;
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signal OP1out, OP2out : std_logic_vector(31 downto 0);
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signal OP1out, OP2out : std_logic_vector(31 downto 0);
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signal OP1outbrief : std_logic_vector(15 downto 0);
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signal OP1outbrief : std_logic_vector(15 downto 0);
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signal OP1in : std_logic_vector(31 downto 0);
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signal OP1in : std_logic_vector(31 downto 0);
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signal data_write_tmp : std_logic_vector(31 downto 0);
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signal data_write_tmp : std_logic_vector(31 downto 0);
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signal Xtmp : std_logic_vector(31 downto 0);
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signal Xtmp : std_logic_vector(31 downto 0);
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signal PC_dataa, PC_datab, PC_result : std_logic_vector(31 downto 0);
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signal PC_dataa, PC_datab, PC_result : std_logic_vector(31 downto 0);
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signal setregstore : std_logic;
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signal setregstore : std_logic;
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signal datatype : std_logic_vector(1 downto 0);
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signal datatype : std_logic_vector(1 downto 0);
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signal longread : std_logic;
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signal longread : std_logic;
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signal longreaddirect : std_logic;
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signal longreaddirect : std_logic;
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signal long_done : std_logic;
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signal long_done : std_logic;
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signal nextpass : std_logic;
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signal nextpass : std_logic;
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signal setnextpass : std_logic;
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signal setnextpass : std_logic;
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signal setdispbyte : std_logic;
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signal setdispbyte : std_logic;
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signal setdisp : std_logic;
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signal setdisp : std_logic;
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signal setdispbrief : std_logic;
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signal setdispbrief : std_logic;
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signal regdirectsource : std_logic;
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signal regdirectsource : std_logic;
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signal endOPC : std_logic;
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signal endOPC : std_logic;
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signal postadd : std_logic;
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signal postadd : std_logic;
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signal presub : std_logic;
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signal presub : std_logic;
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signal addsub_a : std_logic_vector(31 downto 0);
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signal addsub_a : std_logic_vector(31 downto 0);
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signal addsub_b : std_logic_vector(31 downto 0);
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signal addsub_b : std_logic_vector(31 downto 0);
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signal addsub_q : std_logic_vector(31 downto 0);
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signal addsub_q : std_logic_vector(31 downto 0);
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signal briefext : std_logic_vector(31 downto 0);
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signal briefext : std_logic_vector(31 downto 0);
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signal setbriefext : std_logic;
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signal setbriefext : std_logic;
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signal addsub : std_logic;
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signal addsub : std_logic;
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signal c_in : std_logic_vector(3 downto 0);
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signal c_in : std_logic_vector(3 downto 0);
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signal c_out : std_logic_vector(2 downto 0);
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signal c_out : std_logic_vector(2 downto 0);
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signal add_result : std_logic_vector(33 downto 0);
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signal add_result : std_logic_vector(33 downto 0);
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signal addsub_ofl : std_logic_vector(2 downto 0);
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signal addsub_ofl : std_logic_vector(2 downto 0);
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signal flag_z : std_logic_vector(2 downto 0);
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signal flag_z : std_logic_vector(2 downto 0);
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signal last_data_read : std_logic_vector(15 downto 0);
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signal last_data_read : std_logic_vector(15 downto 0);
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signal data_read : std_logic_vector(31 downto 0);
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signal data_read : std_logic_vector(31 downto 0);
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signal registerin : std_logic_vector(31 downto 0);
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signal registerin : std_logic_vector(31 downto 0);
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signal reg_QA : std_logic_vector(31 downto 0);
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signal reg_QA : std_logic_vector(31 downto 0);
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signal reg_QB : std_logic_vector(31 downto 0);
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signal reg_QB : std_logic_vector(31 downto 0);
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signal Hwrena,Lwrena : std_logic;
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signal Hwrena,Lwrena : std_logic;
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signal Regwrena : std_logic;
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signal Regwrena : std_logic;
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signal rf_dest_addr : std_logic_vector(6 downto 0);
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signal rf_dest_addr : std_logic_vector(6 downto 0);
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signal rf_source_addr : std_logic_vector(6 downto 0);
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signal rf_source_addr : std_logic_vector(6 downto 0);
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signal rf_dest_addr_tmp : std_logic_vector(6 downto 0);
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signal rf_dest_addr_tmp : std_logic_vector(6 downto 0);
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signal rf_source_addr_tmp : std_logic_vector(6 downto 0);
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signal rf_source_addr_tmp : std_logic_vector(6 downto 0);
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signal opcode : std_logic_vector(15 downto 0);
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signal opcode : std_logic_vector(15 downto 0);
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signal laststate : std_logic_vector(1 downto 0);
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signal laststate : std_logic_vector(1 downto 0);
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signal setstate : std_logic_vector(1 downto 0);
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signal setstate : std_logic_vector(1 downto 0);
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signal mem_address : std_logic_vector(31 downto 0);
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signal mem_address : std_logic_vector(31 downto 0);
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signal memaddr_a : std_logic_vector(31 downto 0);
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signal memaddr_a : std_logic_vector(31 downto 0);
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signal mem_data_read : std_logic_vector(31 downto 0);
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signal mem_data_read : std_logic_vector(31 downto 0);
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signal mem_data_write : std_logic_vector(31 downto 0);
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signal mem_data_write : std_logic_vector(31 downto 0);
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signal set_mem_rega : std_logic;
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signal set_mem_rega : std_logic;
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signal data_read_ram : std_logic_vector(31 downto 0);
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signal data_read_ram : std_logic_vector(31 downto 0);
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signal data_read_uart : std_logic_vector(7 downto 0);
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signal data_read_uart : std_logic_vector(7 downto 0);
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signal counter_reg : std_logic_vector(31 downto 0);
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signal counter_reg : std_logic_vector(31 downto 0);
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signal TG68_PC_br8 : std_logic;
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signal TG68_PC_br8 : std_logic;
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signal TG68_PC_brw : std_logic;
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signal TG68_PC_brw : std_logic;
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signal TG68_PC_nop : std_logic;
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signal TG68_PC_nop : std_logic;
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signal setgetbrief : std_logic;
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signal setgetbrief : std_logic;
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signal getbrief : std_logic;
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signal getbrief : std_logic;
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signal brief : std_logic_vector(15 downto 0);
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signal brief : std_logic_vector(15 downto 0);
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signal dest_areg : std_logic;
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signal dest_areg : std_logic;
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signal source_areg : std_logic;
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signal source_areg : std_logic;
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signal data_is_source : std_logic;
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signal data_is_source : std_logic;
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signal set_store_in_tmp : std_logic;
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signal set_store_in_tmp : std_logic;
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signal store_in_tmp : std_logic;
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signal store_in_tmp : std_logic;
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signal write_back : std_logic;
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signal write_back : std_logic;
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signal setaddsub : std_logic;
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signal setaddsub : std_logic;
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signal setstackaddr : std_logic;
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signal setstackaddr : std_logic;
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signal writePC : std_logic;
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signal writePC : std_logic;
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signal writePC_add : std_logic;
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signal writePC_add : std_logic;
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signal set_TG68_PC_dec: std_logic;
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signal set_TG68_PC_dec: std_logic;
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signal TG68_PC_dec : std_logic_vector(1 downto 0);
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signal TG68_PC_dec : std_logic_vector(1 downto 0);
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signal directPC : std_logic;
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signal directPC : std_logic;
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signal set_directPC : std_logic;
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signal set_directPC : std_logic;
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signal execOPC : std_logic;
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signal execOPC : std_logic;
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signal fetchOPC : std_logic;
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signal fetchOPC : std_logic;
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signal Flags : std_logic_vector(15 downto 0); --T.S..III ...XNZVC
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signal Flags : std_logic_vector(15 downto 0); --T.S..III ...XNZVC
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signal set_Flags : std_logic_vector(3 downto 0); --NZVC
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signal set_Flags : std_logic_vector(3 downto 0); --NZVC
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signal exec_ADD : std_logic;
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signal exec_ADD : std_logic;
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signal exec_OR : std_logic;
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signal exec_OR : std_logic;
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signal exec_AND : std_logic;
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signal exec_AND : std_logic;
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signal exec_EOR : std_logic;
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signal exec_EOR : std_logic;
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signal exec_MOVE : std_logic;
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signal exec_MOVE : std_logic;
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signal exec_MOVEQ : std_logic;
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signal exec_MOVEQ : std_logic;
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signal exec_MOVESR : std_logic;
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signal exec_MOVESR : std_logic;
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signal exec_DIRECT : std_logic;
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signal exec_DIRECT : std_logic;
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signal exec_ADDQ : std_logic;
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signal exec_ADDQ : std_logic;
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signal exec_CMP : std_logic;
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signal exec_CMP : std_logic;
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signal exec_ROT : std_logic;
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signal exec_ROT : std_logic;
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signal exec_exg : std_logic;
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signal exec_exg : std_logic;
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signal exec_swap : std_logic;
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signal exec_swap : std_logic;
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signal exec_write_back: std_logic;
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signal exec_write_back: std_logic;
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signal exec_tas : std_logic;
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signal exec_tas : std_logic;
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signal exec_EXT : std_logic;
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signal exec_EXT : std_logic;
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signal exec_ABCD : std_logic;
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signal exec_ABCD : std_logic;
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signal exec_SBCD : std_logic;
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signal exec_SBCD : std_logic;
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signal exec_MULU : std_logic;
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signal exec_MULU : std_logic;
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signal exec_DIVU : std_logic;
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signal exec_DIVU : std_logic;
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signal exec_Scc : std_logic;
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signal exec_Scc : std_logic;
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signal exec_CPMAW : std_logic;
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signal exec_CPMAW : std_logic;
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signal set_exec_ADD : std_logic;
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signal set_exec_ADD : std_logic;
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signal set_exec_OR : std_logic;
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signal set_exec_OR : std_logic;
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signal set_exec_AND : std_logic;
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signal set_exec_AND : std_logic;
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signal set_exec_EOR : std_logic;
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signal set_exec_EOR : std_logic;
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signal set_exec_MOVE : std_logic;
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signal set_exec_MOVE : std_logic;
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signal set_exec_MOVEQ : std_logic;
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signal set_exec_MOVEQ : std_logic;
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signal set_exec_MOVESR: std_logic;
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signal set_exec_MOVESR: std_logic;
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signal set_exec_ADDQ : std_logic;
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signal set_exec_ADDQ : std_logic;
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signal set_exec_CMP : std_logic;
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signal set_exec_CMP : std_logic;
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signal set_exec_ROT : std_logic;
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signal set_exec_ROT : std_logic;
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signal set_exec_tas : std_logic;
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signal set_exec_tas : std_logic;
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signal set_exec_EXT : std_logic;
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signal set_exec_EXT : std_logic;
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signal set_exec_ABCD : std_logic;
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signal set_exec_ABCD : std_logic;
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signal set_exec_SBCD : std_logic;
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signal set_exec_SBCD : std_logic;
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signal set_exec_MULU : std_logic;
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signal set_exec_MULU : std_logic;
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signal set_exec_DIVU : std_logic;
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signal set_exec_DIVU : std_logic;
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signal set_exec_Scc : std_logic;
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signal set_exec_Scc : std_logic;
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signal set_exec_CPMAW : std_logic;
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signal set_exec_CPMAW : std_logic;
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signal condition : std_logic;
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signal condition : std_logic;
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signal OP2out_one : std_logic;
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signal OP2out_one : std_logic;
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signal OP1out_zero : std_logic;
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signal OP1out_zero : std_logic;
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signal ea_to_pc : std_logic;
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signal ea_to_pc : std_logic;
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signal ea_build : std_logic;
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signal ea_build : std_logic;
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signal ea_only : std_logic;
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signal ea_only : std_logic;
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signal get_ea_now : std_logic;
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signal get_ea_now : std_logic;
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signal source_lowbits : std_logic;
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signal source_lowbits : std_logic;
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signal dest_hbits : std_logic;
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signal dest_hbits : std_logic;
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signal rot_rot : std_logic;
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signal rot_rot : std_logic;
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signal rot_lsb : std_logic;
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signal rot_lsb : std_logic;
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signal rot_msb : std_logic;
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signal rot_msb : std_logic;
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signal rot_XC : std_logic;
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signal rot_XC : std_logic;
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signal set_rot_nop : std_logic;
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signal set_rot_nop : std_logic;
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signal rot_nop : std_logic;
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signal rot_nop : std_logic;
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signal rot_out : std_logic_vector(31 downto 0);
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signal rot_out : std_logic_vector(31 downto 0);
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signal rot_bits : std_logic_vector(1 downto 0);
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signal rot_bits : std_logic_vector(1 downto 0);
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signal rot_cnt : std_logic_vector(5 downto 0);
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signal rot_cnt : std_logic_vector(5 downto 0);
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signal set_rot_cnt : std_logic_vector(5 downto 0);
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signal set_rot_cnt : std_logic_vector(5 downto 0);
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signal movem_busy : std_logic;
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signal movem_busy : std_logic;
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signal set_movem_busy : std_logic;
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signal set_movem_busy : std_logic;
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signal movem_addr : std_logic;
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signal movem_addr : std_logic;
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signal movem_regaddr : std_logic_vector(3 downto 0);
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signal movem_regaddr : std_logic_vector(3 downto 0);
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signal movem_mask : std_logic_vector(15 downto 0);
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signal movem_mask : std_logic_vector(15 downto 0);
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signal set_get_movem_mask : std_logic;
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signal set_get_movem_mask : std_logic;
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signal get_movem_mask : std_logic;
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signal get_movem_mask : std_logic;
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signal maskzero : std_logic;
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signal test_maskzero : std_logic;
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signal movem_muxa : std_logic_vector(7 downto 0);
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signal movem_muxa : std_logic_vector(7 downto 0);
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signal movem_muxb : std_logic_vector(3 downto 0);
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signal movem_muxb : std_logic_vector(3 downto 0);
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signal movem_muxc : std_logic_vector(1 downto 0);
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signal movem_muxc : std_logic_vector(1 downto 0);
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signal movem_presub : std_logic;
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signal movem_presub : std_logic;
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signal save_memaddr : std_logic;
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signal save_memaddr : std_logic;
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signal movem_bits : std_logic_vector(4 downto 0);
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signal movem_bits : std_logic_vector(4 downto 0);
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signal ea_calc_b : std_logic_vector(31 downto 0);
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signal ea_calc_b : std_logic_vector(31 downto 0);
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signal set_mem_addsub : std_logic;
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signal set_mem_addsub : std_logic;
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signal bit_bits : std_logic_vector(1 downto 0);
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signal bit_bits : std_logic_vector(1 downto 0);
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signal bit_number_reg : std_logic_vector(4 downto 0);
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signal bit_number_reg : std_logic_vector(4 downto 0);
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signal bit_number : std_logic_vector(4 downto 0);
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signal bit_number : std_logic_vector(4 downto 0);
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signal exec_Bits : std_logic;
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signal exec_Bits : std_logic;
|
signal bits_out : std_logic_vector(31 downto 0);
|
signal bits_out : std_logic_vector(31 downto 0);
|
signal one_bit_in : std_logic;
|
signal one_bit_in : std_logic;
|
signal one_bit_out : std_logic;
|
signal one_bit_out : std_logic;
|
signal set_get_bitnumber : std_logic;
|
signal set_get_bitnumber : std_logic;
|
signal get_bitnumber : std_logic;
|
signal get_bitnumber : std_logic;
|
signal mem_byte : std_logic;
|
signal mem_byte : std_logic;
|
signal wait_mem_byte : std_logic;
|
signal wait_mem_byte : std_logic;
|
signal movepl : std_logic;
|
signal movepl : std_logic;
|
signal movepw : std_logic;
|
signal movepw : std_logic;
|
signal set_movepl : std_logic;
|
signal set_movepl : std_logic;
|
signal set_movepw : std_logic;
|
signal set_movepw : std_logic;
|
signal set_direct_data: std_logic;
|
signal set_direct_data: std_logic;
|
signal use_direct_data: std_logic;
|
signal use_direct_data: std_logic;
|
signal direct_data : std_logic;
|
signal direct_data : std_logic;
|
signal set_get_extendedOPC : std_logic;
|
signal set_get_extendedOPC : std_logic;
|
signal get_extendedOPC: std_logic;
|
signal get_extendedOPC: std_logic;
|
signal setstate_delay : std_logic_vector(1 downto 0);
|
signal setstate_delay : std_logic_vector(1 downto 0);
|
signal setstate_mux : std_logic_vector(1 downto 0);
|
signal setstate_mux : std_logic_vector(1 downto 0);
|
signal use_XZFlag : std_logic;
|
signal use_XZFlag : std_logic;
|
signal use_XFlag : std_logic;
|
signal use_XFlag : std_logic;
|
|
|
signal dummy_a : std_logic_vector(8 downto 0);
|
signal dummy_a : std_logic_vector(8 downto 0);
|
signal niba_l : std_logic_vector(5 downto 0);
|
signal niba_l : std_logic_vector(5 downto 0);
|
signal niba_h : std_logic_vector(5 downto 0);
|
signal niba_h : std_logic_vector(5 downto 0);
|
signal niba_lc : std_logic;
|
signal niba_lc : std_logic;
|
signal niba_hc : std_logic;
|
signal niba_hc : std_logic;
|
signal bcda_lc : std_logic;
|
signal bcda_lc : std_logic;
|
signal bcda_hc : std_logic;
|
signal bcda_hc : std_logic;
|
signal dummy_s : std_logic_vector(8 downto 0);
|
signal dummy_s : std_logic_vector(8 downto 0);
|
signal nibs_l : std_logic_vector(5 downto 0);
|
signal nibs_l : std_logic_vector(5 downto 0);
|
signal nibs_h : std_logic_vector(5 downto 0);
|
signal nibs_h : std_logic_vector(5 downto 0);
|
signal nibs_lc : std_logic;
|
signal nibs_lc : std_logic;
|
signal nibs_hc : std_logic;
|
signal nibs_hc : std_logic;
|
signal dummy_mulu : std_logic_vector(31 downto 0);
|
signal dummy_mulu : std_logic_vector(31 downto 0);
|
signal dummy_div : std_logic_vector(31 downto 0);
|
signal dummy_div : std_logic_vector(31 downto 0);
|
signal dummy_div_sub : std_logic_vector(16 downto 0);
|
signal dummy_div_sub : std_logic_vector(16 downto 0);
|
signal dummy_div_over : std_logic_vector(16 downto 0);
|
signal dummy_div_over : std_logic_vector(16 downto 0);
|
signal set_V_Flag : std_logic;
|
signal set_V_Flag : std_logic;
|
signal OP1sign : std_logic;
|
signal OP1sign : std_logic;
|
signal set_sign : std_logic;
|
signal set_sign : std_logic;
|
signal sign : std_logic;
|
signal sign : std_logic;
|
signal sign2 : std_logic;
|
signal sign2 : std_logic;
|
signal muls_msb : std_logic;
|
signal muls_msb : std_logic;
|
signal mulu_reg : std_logic_vector(31 downto 0);
|
signal mulu_reg : std_logic_vector(31 downto 0);
|
signal div_reg : std_logic_vector(31 downto 0);
|
signal div_reg : std_logic_vector(31 downto 0);
|
signal div_sign : std_logic;
|
signal div_sign : std_logic;
|
signal div_quot : std_logic_vector(31 downto 0);
|
signal div_quot : std_logic_vector(31 downto 0);
|
signal div_ovl : std_logic;
|
signal div_ovl : std_logic;
|
signal pre_V_Flag : std_logic;
|
signal pre_V_Flag : std_logic;
|
signal set_vectoraddr : std_logic;
|
signal set_vectoraddr : std_logic;
|
signal writeSR : std_logic;
|
signal writeSR : std_logic;
|
signal trap_illegal : std_logic;
|
signal trap_illegal : std_logic;
|
signal trap_priv : std_logic;
|
signal trap_priv : std_logic;
|
signal trap_1010 : std_logic;
|
signal trap_1010 : std_logic;
|
signal trap_1111 : std_logic;
|
signal trap_1111 : std_logic;
|
signal trap_trap : std_logic;
|
signal trap_trap : std_logic;
|
signal trap_trapv : std_logic;
|
signal trap_trapv : std_logic;
|
signal trap_interrupt : std_logic;
|
signal trap_interrupt : std_logic;
|
signal trapmake : std_logic;
|
signal trapmake : std_logic;
|
signal trapd : std_logic;
|
signal trapd : std_logic;
|
-- signal trap_PC : std_logic_vector(31 downto 0);
|
-- signal trap_PC : std_logic_vector(31 downto 0);
|
signal trap_SR : std_logic_vector(15 downto 0);
|
signal trap_SR : std_logic_vector(15 downto 0);
|
|
|
signal set_directSR : std_logic;
|
signal set_directSR : std_logic;
|
signal directSR : std_logic;
|
signal directSR : std_logic;
|
signal set_directCCR : std_logic;
|
signal set_directCCR : std_logic;
|
signal directCCR : std_logic;
|
signal directCCR : std_logic;
|
signal set_stop : std_logic;
|
signal set_stop : std_logic;
|
signal stop : std_logic;
|
signal stop : std_logic;
|
signal trap_vector : std_logic_vector(31 downto 0);
|
signal trap_vector : std_logic_vector(31 downto 0);
|
signal to_USP : std_logic;
|
signal to_USP : std_logic;
|
signal from_USP : std_logic;
|
signal from_USP : std_logic;
|
signal to_SR : std_logic;
|
signal to_SR : std_logic;
|
signal from_SR : std_logic;
|
signal from_SR : std_logic;
|
signal illegal_write_mode : std_logic;
|
signal illegal_write_mode : std_logic;
|
signal illegal_read_mode : std_logic;
|
signal illegal_read_mode : std_logic;
|
signal illegal_byteaddr : std_logic;
|
signal illegal_byteaddr : std_logic;
|
signal use_SP : std_logic;
|
signal use_SP : std_logic;
|
|
|
signal no_Flags : std_logic;
|
signal no_Flags : std_logic;
|
signal IPL_nr : std_logic_vector(2 downto 0);
|
signal IPL_nr : std_logic_vector(2 downto 0);
|
signal rIPL_nr : std_logic_vector(2 downto 0);
|
signal rIPL_nr : std_logic_vector(2 downto 0);
|
signal interrupt : std_logic;
|
signal interrupt : std_logic;
|
signal SVmode : std_logic;
|
signal SVmode : std_logic;
|
signal trap_chk : std_logic;
|
signal trap_chk : std_logic;
|
signal test_delay : std_logic_vector(2 downto 0);
|
signal test_delay : std_logic_vector(2 downto 0);
|
signal set_PCmarker : std_logic;
|
signal set_PCmarker : std_logic;
|
signal PCmarker : std_logic;
|
signal PCmarker : std_logic;
|
signal set_Z_error : std_logic;
|
signal set_Z_error : std_logic;
|
signal Z_error : std_logic;
|
signal Z_error : std_logic;
|
|
|
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_dAn2, ld_AnXn1, ld_AnXn2, ld_AnXn3, st_dAn1, st_dAn2,
|
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_dAn2, ld_AnXn1, ld_AnXn2, ld_AnXn3, st_dAn1, st_dAn2,
|
st_AnXn1, st_AnXn2, st_AnXn3, bra1, bra2, bsr1, bsr2, dbcc1, dbcc2,
|
st_AnXn1, st_AnXn2, st_AnXn3, bra1, bra2, bsr1, bsr2, dbcc1, dbcc2,
|
movem, andi, op_AxAy, cmpm, link, int1, int2, int3, int4, rte, trap1, trap2, trap3,
|
movem, andi, op_AxAy, cmpm, link, int1, int2, int3, int4, rte, trap1, trap2, trap3,
|
movep1, movep2, movep3, movep4, movep5, init1, init2,
|
movep1, movep2, movep3, movep4, movep5, init1, init2,
|
mul1, mul2, mul3, mul4, mul5, mul6, mul7, mul8, mul9, mul10, mul11, mul12, mul13, mul14, mul15,
|
mul1, mul2, mul3, mul4, mul5, mul6, mul7, mul8, mul9, mul10, mul11, mul12, mul13, mul14, mul15,
|
div1, div2, div3, div4, div5, div6, div7, div8, div9, div10, div11, div12, div13, div14, div15 );
|
div1, div2, div3, div4, div5, div6, div7, div8, div9, div10, div11, div12, div13, div14, div15 );
|
signal micro_state : micro_states;
|
signal micro_state : micro_states;
|
signal next_micro_state : micro_states;
|
signal next_micro_state : micro_states;
|
|
|
type regfile_t is array(0 to 16) of std_logic_vector(15 downto 0);
|
type regfile_t is array(0 to 16) of std_logic_vector(15 downto 0);
|
signal regfile_low : regfile_t;
|
signal regfile_low : regfile_t;
|
signal regfile_high : regfile_t;
|
signal regfile_high : regfile_t;
|
signal RWindex_A : integer range 0 to 16;
|
signal RWindex_A : integer range 0 to 16;
|
signal RWindex_B : integer range 0 to 16;
|
signal RWindex_B : integer range 0 to 16;
|
|
|
|
|
BEGIN
|
BEGIN
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Registerfile
|
-- Registerfile
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
RWindex_A <= conv_integer(rf_dest_addr(4)&(rf_dest_addr(3 downto 0) XOR "1111"));
|
RWindex_A <= conv_integer(rf_dest_addr(4)&(rf_dest_addr(3 downto 0) XOR "1111"));
|
RWindex_B <= conv_integer(rf_source_addr(4)&(rf_source_addr(3 downto 0) XOR "1111"));
|
RWindex_B <= conv_integer(rf_source_addr(4)&(rf_source_addr(3 downto 0) XOR "1111"));
|
|
|
PROCESS (clk)
|
PROCESS (clk)
|
BEGIN
|
BEGIN
|
IF falling_edge(clk) THEN
|
IF falling_edge(clk) THEN
|
IF clkena='1' THEN
|
IF clkena='1' THEN
|
reg_QA <= regfile_high(RWindex_A) & regfile_low(RWindex_A);
|
reg_QA <= regfile_high(RWindex_A) & regfile_low(RWindex_A);
|
reg_QB <= regfile_high(RWindex_B) & regfile_low(RWindex_B);
|
reg_QB <= regfile_high(RWindex_B) & regfile_low(RWindex_B);
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF rising_edge(clk) THEN
|
IF rising_edge(clk) THEN
|
IF clkena='1' THEN
|
IF clkena='1' THEN
|
IF Lwrena='1' THEN
|
IF Lwrena='1' THEN
|
regfile_low(RWindex_A) <= registerin(15 downto 0);
|
regfile_low(RWindex_A) <= registerin(15 downto 0);
|
END IF;
|
END IF;
|
IF Hwrena='1' THEN
|
IF Hwrena='1' THEN
|
regfile_high(RWindex_A) <= registerin(31 downto 16);
|
regfile_high(RWindex_A) <= registerin(31 downto 16);
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
|
|
|
|
address <= TG68_PC when state="00" else X"ffffffff" when state="01" else memaddr;
|
address <= TG68_PC when state="00" else X"ffffffff" when state="01" else memaddr;
|
LDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='1') AND state/="01" ELSE '1';
|
LDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='1') AND state/="01" ELSE '1';
|
UDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='0') AND state/="01" ELSE '1';
|
UDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='0') AND state/="01" ELSE '1';
|
state_out <= state;
|
state_out <= state;
|
wr <= '0' WHEN state="11" ELSE '1';
|
wr <= '0' WHEN state="11" ELSE '1';
|
IPL_nr <= NOT IPL;
|
IPL_nr <= NOT IPL;
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- "ALU"
|
-- "ALU"
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (addsub_a, addsub_b, addsub, add_result, c_in)
|
PROCESS (addsub_a, addsub_b, addsub, add_result, c_in)
|
BEGIN
|
BEGIN
|
IF addsub='1' THEN --ADD
|
IF addsub='1' THEN --ADD
|
add_result <= (('0'&addsub_a&c_in(0))+('0'&addsub_b&c_in(0)));
|
add_result <= (('0'&addsub_a&c_in(0))+('0'&addsub_b&c_in(0)));
|
ELSE --SUB
|
ELSE --SUB
|
add_result <= (('0'&addsub_a&'0')-('0'&addsub_b&c_in(0)));
|
add_result <= (('0'&addsub_a&'0')-('0'&addsub_b&c_in(0)));
|
END IF;
|
END IF;
|
addsub_q <= add_result(32 downto 1);
|
addsub_q <= add_result(32 downto 1);
|
c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
|
c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
|
c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
|
c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
|
c_in(3) <= add_result(33);
|
c_in(3) <= add_result(33);
|
addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte
|
addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte
|
addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word
|
addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word
|
addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long
|
addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long
|
c_out <= c_in(3 downto 1);
|
c_out <= c_in(3 downto 1);
|
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- MEM_IO
|
-- MEM_IO
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, memaddr, memaddr_a, set_mem_addsub, movem_presub,
|
PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, memaddr, memaddr_a, set_mem_addsub, movem_presub,
|
movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
|
movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
|
set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
|
set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
|
data_write_tmp, addsub_q, set_vectoraddr, trap_vector, interrupt)
|
data_write_tmp, addsub_q, set_vectoraddr, trap_vector, interrupt)
|
BEGIN
|
BEGIN
|
clkena <= clkena_in AND NOT longread AND NOT get_extendedOPC;
|
clkena <= clkena_in AND NOT longread AND NOT get_extendedOPC;
|
|
|
IF rising_edge(clk) THEN
|
IF rising_edge(clk) THEN
|
IF clkena='1' THEN
|
IF clkena='1' THEN
|
trap_vector(31 downto 8) <= (others => '0');
|
trap_vector(31 downto 8) <= (others => '0');
|
-- IF trap_addr_fault='1' THEN
|
-- IF trap_addr_fault='1' THEN
|
-- trap_vector(7 downto 0) <= X"08";
|
-- trap_vector(7 downto 0) <= X"08";
|
-- END IF;
|
-- END IF;
|
-- IF trap_addr_error='1' THEN
|
-- IF trap_addr_error='1' THEN
|
-- trap_vector(7 downto 0) <= X"0C";
|
-- trap_vector(7 downto 0) <= X"0C";
|
-- END IF;
|
-- END IF;
|
IF trap_illegal='1' THEN
|
IF trap_illegal='1' THEN
|
trap_vector(7 downto 0) <= X"10";
|
trap_vector(7 downto 0) <= X"10";
|
END IF;
|
END IF;
|
IF z_error='1' THEN
|
IF z_error='1' THEN
|
trap_vector(7 downto 0) <= X"14";
|
trap_vector(7 downto 0) <= X"14";
|
END IF;
|
END IF;
|
-- IF trap_chk='1' THEN
|
-- IF trap_chk='1' THEN
|
-- trap_vector(7 downto 0) <= X"18";
|
-- trap_vector(7 downto 0) <= X"18";
|
-- END IF;
|
-- END IF;
|
IF trap_trapv='1' THEN
|
IF trap_trapv='1' THEN
|
trap_vector(7 downto 0) <= X"1C";
|
trap_vector(7 downto 0) <= X"1C";
|
END IF;
|
END IF;
|
IF trap_priv='1' THEN
|
IF trap_priv='1' THEN
|
trap_vector(7 downto 0) <= X"20";
|
trap_vector(7 downto 0) <= X"20";
|
END IF;
|
END IF;
|
-- IF trap_trace='1' THEN
|
-- IF trap_trace='1' THEN
|
-- trap_vector(7 downto 0) <= X"24";
|
-- trap_vector(7 downto 0) <= X"24";
|
-- END IF;
|
-- END IF;
|
IF trap_1010='1' THEN
|
IF trap_1010='1' THEN
|
trap_vector(7 downto 0) <= X"28";
|
trap_vector(7 downto 0) <= X"28";
|
END IF;
|
END IF;
|
IF trap_1111='1' THEN
|
IF trap_1111='1' THEN
|
trap_vector(7 downto 0) <= X"2C";
|
trap_vector(7 downto 0) <= X"2C";
|
END IF;
|
END IF;
|
IF trap_trap='1' THEN
|
IF trap_trap='1' THEN
|
trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
|
trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
|
END IF;
|
END IF;
|
IF interrupt='1' THEN
|
IF interrupt='1' THEN
|
trap_vector(7 downto 2) <= "011"&rIPL_nr;
|
trap_vector(7 downto 2) <= "011"&rIPL_nr;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
memaddr_a(3 downto 0) <= "0000";
|
memaddr_a(3 downto 0) <= "0000";
|
memaddr_a(7 downto 4) <= (OTHERS=>memaddr_a(3));
|
memaddr_a(7 downto 4) <= (OTHERS=>memaddr_a(3));
|
memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
|
memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
|
memaddr_a(31 downto 16) <= (OTHERS=>memaddr_a(15));
|
memaddr_a(31 downto 16) <= (OTHERS=>memaddr_a(15));
|
IF movem_presub='1' THEN
|
IF movem_presub='1' THEN
|
IF movem_busy='1' OR longread='1' THEN
|
IF movem_busy='1' OR longread='1' THEN
|
memaddr_a(3 downto 0) <= "1110";
|
memaddr_a(3 downto 0) <= "1110";
|
END IF;
|
END IF;
|
ELSIF state(1)='1' OR (get_extendedOPC='1' AND PCmarker='1') THEN
|
ELSIF state(1)='1' OR (get_extendedOPC='1' AND PCmarker='1') THEN
|
memaddr_a(1) <= '1';
|
memaddr_a(1) <= '1';
|
ELSIF execOPC='1' THEN
|
ELSIF execOPC='1' THEN
|
IF datatype="10" THEN
|
IF datatype="10" THEN
|
memaddr_a(3 downto 0) <= "1100";
|
memaddr_a(3 downto 0) <= "1100";
|
ELSE
|
ELSE
|
memaddr_a(3 downto 0) <= "1110";
|
memaddr_a(3 downto 0) <= "1110";
|
END IF;
|
END IF;
|
ELSIF setdisp='1' THEN
|
ELSIF setdisp='1' THEN
|
IF setdispbrief='1' THEN
|
IF setdispbrief='1' THEN
|
memaddr_a <= briefext;
|
memaddr_a <= briefext;
|
ELSIF setdispbyte='1' THEN
|
ELSIF setdispbyte='1' THEN
|
memaddr_a(7 downto 0) <= brief(7 downto 0);
|
memaddr_a(7 downto 0) <= brief(7 downto 0);
|
ELSE
|
ELSE
|
memaddr_a(15 downto 0) <= brief;
|
memaddr_a(15 downto 0) <= brief;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
memaddr_in <= memaddr+memaddr_a;
|
memaddr_in <= memaddr+memaddr_a;
|
IF longread='0' THEN
|
IF longread='0' THEN
|
IF set_mem_addsub='1' THEN
|
IF set_mem_addsub='1' THEN
|
memaddr_in <= addsub_q;
|
memaddr_in <= addsub_q;
|
ELSIF set_vectoraddr='1' THEN
|
ELSIF set_vectoraddr='1' THEN
|
memaddr_in <= trap_vector;
|
memaddr_in <= trap_vector;
|
ELSIF interrupt='1' THEN
|
ELSIF interrupt='1' THEN
|
memaddr_in <= "1111111111111111111111111111"&rIPL_nr&'0';
|
memaddr_in <= "1111111111111111111111111111"&rIPL_nr&'0';
|
ELSIF set_mem_rega='1' THEN
|
ELSIF set_mem_rega='1' THEN
|
memaddr_in <= reg_QA;
|
memaddr_in <= reg_QA;
|
ELSIF setaddrlong='1' AND longread='0' THEN
|
ELSIF setaddrlong='1' AND longread='0' THEN
|
memaddr_in <= data_read;
|
memaddr_in <= data_read;
|
ELSIF decodeOPC='1' THEN
|
ELSIF decodeOPC='1' THEN
|
memaddr_in <= TG68_PC;
|
memaddr_in <= TG68_PC;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
data_read(15 downto 0) <= data_in;
|
data_read(15 downto 0) <= data_in;
|
data_read(31 downto 16) <= (OTHERS=>data_in(15));
|
data_read(31 downto 16) <= (OTHERS=>data_in(15));
|
IF long_done='1' THEN
|
IF long_done='1' THEN
|
data_read(31 downto 16) <= last_data_read;
|
data_read(31 downto 16) <= last_data_read;
|
END IF;
|
END IF;
|
IF mem_byte='1' AND memaddr(0)='0' THEN
|
IF mem_byte='1' AND memaddr(0)='0' THEN
|
data_read(7 downto 0) <= data_in(15 downto 8);
|
data_read(7 downto 0) <= data_in(15 downto 8);
|
END IF;
|
END IF;
|
|
|
IF longread='1' THEN
|
IF longread='1' THEN
|
data_write <= data_write_tmp(31 downto 16);
|
data_write <= data_write_tmp(31 downto 16);
|
ELSE
|
ELSE
|
data_write(7 downto 0) <= data_write_tmp(7 downto 0);
|
data_write(7 downto 0) <= data_write_tmp(7 downto 0);
|
IF mem_byte='1' THEN
|
IF mem_byte='1' THEN
|
data_write(15 downto 8) <= data_write_tmp(7 downto 0);
|
data_write(15 downto 8) <= data_write_tmp(7 downto 0);
|
ELSE
|
ELSE
|
data_write(15 downto 8) <= data_write_tmp(15 downto 8);
|
data_write(15 downto 8) <= data_write_tmp(15 downto 8);
|
IF datatype="00" THEN
|
IF datatype="00" THEN
|
data_write(7 downto 0) <= data_write_tmp(15 downto 8);
|
data_write(7 downto 0) <= data_write_tmp(15 downto 8);
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
IF reset='0' THEN
|
IF reset='0' THEN
|
longread <= '0';
|
longread <= '0';
|
long_done <= '0';
|
long_done <= '0';
|
ELSIF rising_edge(clk) THEN
|
ELSIF rising_edge(clk) THEN
|
IF clkena_in='1' THEN
|
IF clkena_in='1' THEN
|
last_data_read <= data_in;
|
last_data_read <= data_in;
|
long_done <= longread;
|
long_done <= longread;
|
IF get_extendedOPC='0' OR (get_extendedOPC='1' AND PCmarker='1') THEN
|
IF get_extendedOPC='0' OR (get_extendedOPC='1' AND PCmarker='1') THEN
|
memaddr <= memaddr_in;
|
memaddr <= memaddr_in;
|
END IF;
|
END IF;
|
IF get_extendedOPC='0' THEN
|
IF get_extendedOPC='0' THEN
|
|
|
IF ((setstate_mux(1)='1' AND datatype="10") OR longreaddirect='1') AND longread='0' AND interrupt='0' THEN
|
IF ((setstate_mux(1)='1' AND datatype="10") OR longreaddirect='1') AND longread='0' AND interrupt='0' THEN
|
longread <= '1';
|
longread <= '1';
|
ELSE
|
ELSE
|
longread <= '0';
|
longread <= '0';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- brief
|
-- brief
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
process (clk, brief, OP1out)
|
process (clk, brief, OP1out)
|
begin
|
begin
|
IF brief(11)='1' THEN
|
IF brief(11)='1' THEN
|
OP1outbrief <= OP1out(31 downto 16);
|
OP1outbrief <= OP1out(31 downto 16);
|
ELSE
|
ELSE
|
OP1outbrief <= (OTHERS=>OP1out(15));
|
OP1outbrief <= (OTHERS=>OP1out(15));
|
END IF;
|
END IF;
|
IF rising_edge(clk) THEN
|
IF rising_edge(clk) THEN
|
IF clkena='1' THEN
|
IF clkena='1' THEN
|
briefext <= OP1outbrief&OP1out(15 downto 0);
|
briefext <= OP1outbrief&OP1out(15 downto 0);
|
-- CASE brief(10 downto 9) IS
|
-- CASE brief(10 downto 9) IS
|
-- WHEN "00" => briefext <= OP1outbrief&OP1out(15 downto 0);
|
-- WHEN "00" => briefext <= OP1outbrief&OP1out(15 downto 0);
|
-- WHEN "01" => briefext <= OP1outbrief(14 downto 0)&OP1out(15 downto 0)&'0';
|
-- WHEN "01" => briefext <= OP1outbrief(14 downto 0)&OP1out(15 downto 0)&'0';
|
-- WHEN "10" => briefext <= OP1outbrief(13 downto 0)&OP1out(15 downto 0)&"00";
|
-- WHEN "10" => briefext <= OP1outbrief(13 downto 0)&OP1out(15 downto 0)&"00";
|
-- WHEN "11" => briefext <= OP1outbrief(12 downto 0)&OP1out(15 downto 0)&"000";
|
-- WHEN "11" => briefext <= OP1outbrief(12 downto 0)&OP1out(15 downto 0)&"000";
|
-- END CASE;
|
-- END CASE;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- PC Calc + fetch opcode
|
-- PC Calc + fetch opcode
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
process (clk, reset, opcode, TG68_PC, TG68_PC_dec, TG68_PC_br8, TG68_PC_brw, PC_dataa, PC_datab, execOPC, last_data_read, get_extendedOPC,
|
process (clk, reset, opcode, TG68_PC, TG68_PC_dec, TG68_PC_br8, TG68_PC_brw, PC_dataa, PC_datab, execOPC, last_data_read, get_extendedOPC,
|
setstate_delay, setstate)
|
setstate_delay, setstate)
|
begin
|
begin
|
PC_dataa <= TG68_PC;
|
PC_dataa <= TG68_PC;
|
PC_datab(2 downto 0) <= "010";
|
PC_datab(2 downto 0) <= "010";
|
PC_datab(7 downto 3) <= (others => PC_datab(2));
|
PC_datab(7 downto 3) <= (others => PC_datab(2));
|
PC_datab(15 downto 8) <= (others => PC_datab(7));
|
PC_datab(15 downto 8) <= (others => PC_datab(7));
|
PC_datab(31 downto 16) <= (others => PC_datab(15));
|
PC_datab(31 downto 16) <= (others => PC_datab(15));
|
IF execOPC='0' THEN
|
IF execOPC='0' THEN
|
IF TG68_PC_br8='1' THEN
|
IF TG68_PC_br8='1' THEN
|
PC_datab(7 downto 0) <= opcode(7 downto 0);
|
PC_datab(7 downto 0) <= opcode(7 downto 0);
|
END IF;
|
END IF;
|
IF TG68_PC_dec(1)='1' THEN
|
IF TG68_PC_dec(1)='1' THEN
|
PC_datab(2) <= '1';
|
PC_datab(2) <= '1';
|
END IF;
|
END IF;
|
IF TG68_PC_brw = '1' THEN
|
IF TG68_PC_brw = '1' THEN
|
PC_datab(15 downto 0) <= last_data_read(15 downto 0);
|
PC_datab(15 downto 0) <= last_data_read(15 downto 0);
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
TG68_PC_add <= PC_dataa+PC_datab;
|
TG68_PC_add <= PC_dataa+PC_datab;
|
|
|
IF get_extendedOPC='1' THEN
|
IF get_extendedOPC='1' THEN
|
setstate_mux <= setstate_delay;
|
setstate_mux <= setstate_delay;
|
ELSE
|
ELSE
|
setstate_mux <= setstate;
|
setstate_mux <= setstate;
|
END IF;
|
END IF;
|
|
|
|
|
IF reset = '0' THEN
|
IF reset = '0' THEN
|
opcode(15 downto 12) <= X"7"; --moveq
|
opcode(15 downto 12) <= X"7"; --moveq
|
opcode(8 downto 6) <= "010"; --long
|
opcode(8 downto 6) <= "010"; --long
|
TG68_PC <= (others =>'0');
|
TG68_PC <= (others =>'0');
|
state <= "01";
|
state <= "01";
|
decodeOPC <= '0';
|
decodeOPC <= '0';
|
fetchOPC <= '0';
|
fetchOPC <= '0';
|
endOPC <= '0';
|
endOPC <= '0';
|
interrupt <= '0';
|
interrupt <= '0';
|
trap_interrupt <= '1';
|
trap_interrupt <= '1';
|
execOPC <= '0';
|
execOPC <= '0';
|
getbrief <= '0';
|
getbrief <= '0';
|
TG68_PC_dec <= "00";
|
TG68_PC_dec <= "00";
|
directPC <= '0';
|
directPC <= '0';
|
directSR <= '0';
|
directSR <= '0';
|
directCCR <= '0';
|
directCCR <= '0';
|
stop <= '0';
|
stop <= '0';
|
exec_ADD <= '0';
|
exec_ADD <= '0';
|
exec_OR <= '0';
|
exec_OR <= '0';
|
exec_AND <= '0';
|
exec_AND <= '0';
|
exec_EOR <= '0';
|
exec_EOR <= '0';
|
exec_MOVE <= '0';
|
exec_MOVE <= '0';
|
exec_MOVEQ <= '0';
|
exec_MOVEQ <= '0';
|
exec_MOVESR <= '0';
|
exec_MOVESR <= '0';
|
exec_ADDQ <= '0';
|
exec_ADDQ <= '0';
|
exec_CMP <= '0';
|
exec_CMP <= '0';
|
exec_ROT <= '0';
|
exec_ROT <= '0';
|
exec_EXT <= '0';
|
exec_EXT <= '0';
|
exec_ABCD <= '0';
|
exec_ABCD <= '0';
|
exec_SBCD <= '0';
|
exec_SBCD <= '0';
|
exec_MULU <= '0';
|
exec_MULU <= '0';
|
exec_DIVU <= '0';
|
exec_DIVU <= '0';
|
exec_Scc <= '0';
|
exec_Scc <= '0';
|
exec_CPMAW <= '0';
|
exec_CPMAW <= '0';
|
mem_byte <= '0';
|
mem_byte <= '0';
|
rot_cnt <="000001";
|
rot_cnt <="000001";
|
rot_nop <= '0';
|
rot_nop <= '0';
|
get_extendedOPC <= '0';
|
get_extendedOPC <= '0';
|
get_bitnumber <= '0';
|
get_bitnumber <= '0';
|
get_movem_mask <= '0';
|
get_movem_mask <= '0';
|
|
test_maskzero <= '0';
|
movepl <= '0';
|
movepl <= '0';
|
movepw <= '0';
|
movepw <= '0';
|
test_delay <= "000";
|
test_delay <= "000";
|
PCmarker <= '0';
|
PCmarker <= '0';
|
ELSIF rising_edge(clk) THEN
|
ELSIF rising_edge(clk) THEN
|
IF clkena_in='1' THEN
|
IF clkena_in='1' THEN
|
get_extendedOPC <= set_get_extendedOPC;
|
get_extendedOPC <= set_get_extendedOPC;
|
get_bitnumber <= set_get_bitnumber;
|
get_bitnumber <= set_get_bitnumber;
|
get_movem_mask <= set_get_movem_mask;
|
get_movem_mask <= set_get_movem_mask;
|
|
test_maskzero <= get_movem_mask;
|
setstate_delay <= setstate;
|
setstate_delay <= setstate;
|
|
|
TG68_PC_dec <= TG68_PC_dec(0)&set_TG68_PC_dec;
|
TG68_PC_dec <= TG68_PC_dec(0)&set_TG68_PC_dec;
|
IF directPC='1' AND clkena='1' THEN
|
IF directPC='1' AND clkena='1' THEN
|
TG68_PC <= data_read;
|
TG68_PC <= data_read;
|
ELSIF ea_to_pc='1' AND longread='0' THEN
|
ELSIF ea_to_pc='1' AND longread='0' THEN
|
TG68_PC <= memaddr_in;
|
TG68_PC <= memaddr_in;
|
ELSIF (state ="00" AND TG68_PC_nop='0') OR TG68_PC_br8='1' OR TG68_PC_brw='1' OR TG68_PC_dec(1)='1' THEN
|
ELSIF (state ="00" AND TG68_PC_nop='0') OR TG68_PC_br8='1' OR TG68_PC_brw='1' OR TG68_PC_dec(1)='1' THEN
|
TG68_PC <= TG68_PC_add;
|
TG68_PC <= TG68_PC_add;
|
END IF;
|
END IF;
|
|
|
IF get_bitnumber='1' THEN
|
IF get_bitnumber='1' THEN
|
bit_number_reg <= data_read(4 downto 0);
|
bit_number_reg <= data_read(4 downto 0);
|
END IF;
|
END IF;
|
|
|
IF clkena='1' OR get_extendedOPC='1' THEN
|
IF clkena='1' OR get_extendedOPC='1' THEN
|
IF set_get_extendedOPC='1' THEN
|
IF set_get_extendedOPC='1' THEN
|
state <= "00";
|
state <= "00";
|
ELSIF get_extendedOPC='1' THEN
|
ELSIF get_extendedOPC='1' THEN
|
state <= setstate_mux;
|
state <= setstate_mux;
|
ELSIF fetchOPC='1' OR (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR stop='1' THEN
|
ELSIF fetchOPC='1' OR (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR stop='1' THEN
|
state <= "01"; --decode cycle, execute cycle
|
state <= "01"; --decode cycle, execute cycle
|
ELSE
|
ELSE
|
state <= setstate_mux;
|
state <= setstate_mux;
|
END IF;
|
END IF;
|
IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' AND wait_mem_byte='0' THEN
|
IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' AND wait_mem_byte='0' THEN
|
mem_byte <= '1';
|
mem_byte <= '1';
|
ELSE
|
ELSE
|
mem_byte <= '0';
|
mem_byte <= '0';
|
END IF;
|
END IF;
|
|
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
IF clkena='1' THEN
|
IF clkena='1' THEN
|
exec_ADD <= '0';
|
exec_ADD <= '0';
|
exec_OR <= '0';
|
exec_OR <= '0';
|
exec_AND <= '0';
|
exec_AND <= '0';
|
exec_EOR <= '0';
|
exec_EOR <= '0';
|
exec_MOVE <= '0';
|
exec_MOVE <= '0';
|
exec_MOVEQ <= '0';
|
exec_MOVEQ <= '0';
|
exec_MOVESR <= '0';
|
exec_MOVESR <= '0';
|
exec_ADDQ <= '0';
|
exec_ADDQ <= '0';
|
exec_CMP <= '0';
|
exec_CMP <= '0';
|
exec_ROT <= '0';
|
exec_ROT <= '0';
|
exec_ABCD <= '0';
|
exec_ABCD <= '0';
|
exec_SBCD <= '0';
|
exec_SBCD <= '0';
|
fetchOPC <= '0';
|
fetchOPC <= '0';
|
exec_CPMAW <= '0';
|
exec_CPMAW <= '0';
|
endOPC <= '0';
|
endOPC <= '0';
|
interrupt <= '0';
|
interrupt <= '0';
|
execOPC <= '0';
|
execOPC <= '0';
|
exec_EXT <= '0';
|
exec_EXT <= '0';
|
exec_Scc <= '0';
|
exec_Scc <= '0';
|
rot_nop <= '0';
|
rot_nop <= '0';
|
decodeOPC <= fetchOPC;
|
decodeOPC <= fetchOPC;
|
directPC <= set_directPC;
|
directPC <= set_directPC;
|
directSR <= set_directSR;
|
directSR <= set_directSR;
|
directCCR <= set_directCCR;
|
directCCR <= set_directCCR;
|
exec_MULU <= set_exec_MULU;
|
exec_MULU <= set_exec_MULU;
|
exec_DIVU <= set_exec_DIVU;
|
exec_DIVU <= set_exec_DIVU;
|
movepl <= '0';
|
movepl <= '0';
|
movepw <= '0';
|
movepw <= '0';
|
|
|
stop <= set_stop OR (stop AND NOT interrupt);
|
stop <= set_stop OR (stop AND NOT interrupt);
|
IF set_PCmarker='1' THEN
|
IF set_PCmarker='1' THEN
|
PCmarker <= '1';
|
PCmarker <= '1';
|
ELSIF (state="10" AND longread='0') OR (ea_only='1' AND get_ea_now='1') THEN
|
ELSIF (state="10" AND longread='0') OR (ea_only='1' AND get_ea_now='1') THEN
|
PCmarker <= '0';
|
PCmarker <= '0';
|
END IF;
|
END IF;
|
IF (decodeOPC OR execOPC)='1' THEN
|
IF (decodeOPC OR execOPC)='1' THEN
|
rot_cnt <= set_rot_cnt;
|
rot_cnt <= set_rot_cnt;
|
END IF;
|
END IF;
|
IF next_micro_state=idle AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
|
IF next_micro_state=idle AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
|
nextpass <= '0';
|
nextpass <= '0';
|
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
|
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
|
endOPC <= '1';
|
endOPC <= '1';
|
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
|
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
|
interrupt <= '1';
|
interrupt <= '1';
|
rIPL_nr <= IPL_nr;
|
rIPL_nr <= IPL_nr;
|
ELSE
|
ELSE
|
IF stop='0' THEN
|
IF stop='0' THEN
|
fetchOPC <= '1';
|
fetchOPC <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF exec_write_back='0' OR state/="11" THEN
|
IF exec_write_back='0' OR state/="11" THEN
|
IF stop='0' THEN
|
IF stop='0' THEN
|
execOPC <= '1';
|
execOPC <= '1';
|
END IF;
|
END IF;
|
exec_ADD <= set_exec_ADD;
|
exec_ADD <= set_exec_ADD;
|
exec_OR <= set_exec_OR;
|
exec_OR <= set_exec_OR;
|
exec_AND <= set_exec_AND;
|
exec_AND <= set_exec_AND;
|
exec_EOR <= set_exec_EOR;
|
exec_EOR <= set_exec_EOR;
|
exec_MOVE <= set_exec_MOVE;
|
exec_MOVE <= set_exec_MOVE;
|
exec_MOVEQ <= set_exec_MOVEQ;
|
exec_MOVEQ <= set_exec_MOVEQ;
|
exec_MOVESR <= set_exec_MOVESR;
|
exec_MOVESR <= set_exec_MOVESR;
|
exec_ADDQ <= set_exec_ADDQ;
|
exec_ADDQ <= set_exec_ADDQ;
|
exec_CMP <= set_exec_CMP;
|
exec_CMP <= set_exec_CMP;
|
exec_ROT <= set_exec_ROT;
|
exec_ROT <= set_exec_ROT;
|
exec_tas <= set_exec_tas;
|
exec_tas <= set_exec_tas;
|
exec_EXT <= set_exec_EXT;
|
exec_EXT <= set_exec_EXT;
|
exec_ABCD <= set_exec_ABCD;
|
exec_ABCD <= set_exec_ABCD;
|
exec_SBCD <= set_exec_SBCD;
|
exec_SBCD <= set_exec_SBCD;
|
exec_Scc <= set_exec_Scc;
|
exec_Scc <= set_exec_Scc;
|
exec_CPMAW <= set_exec_CPMAW;
|
exec_CPMAW <= set_exec_CPMAW;
|
rot_nop <= set_rot_nop;
|
rot_nop <= set_rot_nop;
|
|
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
IF endOPC='0' AND (setnextpass='1' OR (regdirectsource='1' AND decodeOPC='1')) THEN
|
IF endOPC='0' AND (setnextpass='1' OR (regdirectsource='1' AND decodeOPC='1')) THEN
|
nextpass <= '1';
|
nextpass <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF interrupt='1' THEN
|
IF interrupt='1' THEN
|
opcode(15 downto 12) <= X"7"; --moveq
|
opcode(15 downto 12) <= X"7"; --moveq
|
opcode(8 downto 6) <= "010"; --long
|
opcode(8 downto 6) <= "010"; --long
|
-- trap_PC <= TG68_PC;
|
-- trap_PC <= TG68_PC;
|
trap_interrupt <= '1';
|
trap_interrupt <= '1';
|
END IF;
|
END IF;
|
IF fetchOPC='1' THEN
|
IF fetchOPC='1' THEN
|
trap_interrupt <= '0';
|
trap_interrupt <= '0';
|
IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' THEN
|
IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' THEN
|
-- IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' OR opcode(15 downto 6)="0100111011" THEN --nur für Validator
|
-- IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' OR opcode(15 downto 6)="0100111011" THEN --nur für Validator
|
opcode <= X"60FE";
|
opcode <= X"60FE";
|
IF to_SR='0' THEN
|
IF to_SR='0' THEN
|
test_delay <= "001";
|
test_delay <= "001";
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
opcode <= data_read(15 downto 0);
|
opcode <= data_read(15 downto 0);
|
END IF;
|
END IF;
|
getbrief <= '0';
|
getbrief <= '0';
|
-- trap_PC <= TG68_PC;
|
-- trap_PC <= TG68_PC;
|
ELSE
|
ELSE
|
test_delay <= test_delay(1 downto 0)&'0';
|
test_delay <= test_delay(1 downto 0)&'0';
|
getbrief <= setgetbrief;
|
getbrief <= setgetbrief;
|
movepl <= set_movepl;
|
movepl <= set_movepl;
|
movepw <= set_movepw;
|
movepw <= set_movepw;
|
END IF;
|
END IF;
|
IF decodeOPC='1' OR interrupt='1' THEN
|
IF decodeOPC='1' OR interrupt='1' THEN
|
trap_SR <= Flags;
|
trap_SR <= Flags;
|
END IF;
|
END IF;
|
|
|
IF getbrief='1' THEN
|
IF getbrief='1' THEN
|
brief <= data_read(15 downto 0);
|
brief <= data_read(15 downto 0);
|
END IF;
|
END IF;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- handle EA_data, data_write_tmp
|
-- handle EA_data, data_write_tmp
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (clk, reset, opcode)
|
PROCESS (clk, reset, opcode)
|
BEGIN
|
BEGIN
|
IF reset = '0' THEN
|
IF reset = '0' THEN
|
set_store_in_tmp <='0';
|
set_store_in_tmp <='0';
|
exec_DIRECT <= '0';
|
exec_DIRECT <= '0';
|
exec_write_back <= '0';
|
exec_write_back <= '0';
|
direct_data <= '0';
|
direct_data <= '0';
|
use_direct_data <= '0';
|
use_direct_data <= '0';
|
Z_error <= '0';
|
Z_error <= '0';
|
ELSIF rising_edge(clk) THEN
|
ELSIF rising_edge(clk) THEN
|
IF clkena='1' THEN
|
IF clkena='1' THEN
|
direct_data <= '0';
|
direct_data <= '0';
|
IF endOPC='1' THEN
|
IF endOPC='1' THEN
|
set_store_in_tmp <='0';
|
set_store_in_tmp <='0';
|
exec_DIRECT <= '0';
|
exec_DIRECT <= '0';
|
exec_write_back <= '0';
|
exec_write_back <= '0';
|
use_direct_data <= '0';
|
use_direct_data <= '0';
|
Z_error <= '0';
|
Z_error <= '0';
|
ELSE
|
ELSE
|
IF set_Z_error='1' THEN
|
IF set_Z_error='1' THEN
|
Z_error <= '1';
|
Z_error <= '1';
|
END IF;
|
END IF;
|
exec_DIRECT <= set_exec_MOVE;
|
exec_DIRECT <= set_exec_MOVE;
|
IF setstate_mux="10" AND write_back='1' THEN
|
IF setstate_mux="10" AND write_back='1' THEN
|
exec_write_back <= '1';
|
exec_write_back <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF set_direct_data='1' THEN
|
IF set_direct_data='1' THEN
|
direct_data <= '1';
|
direct_data <= '1';
|
use_direct_data <= '1';
|
use_direct_data <= '1';
|
END IF;
|
END IF;
|
IF set_exec_MOVE='1' AND state="11" THEN
|
IF set_exec_MOVE='1' AND state="11" THEN
|
use_direct_data <= '1';
|
use_direct_data <= '1';
|
END IF;
|
END IF;
|
|
|
IF (exec_DIRECT='1' AND state="00" AND getbrief='0' AND endOPC='0') OR state="10" THEN
|
IF (exec_DIRECT='1' AND state="00" AND getbrief='0' AND endOPC='0') OR state="10" THEN
|
set_store_in_tmp <= '1';
|
set_store_in_tmp <= '1';
|
ea_data <= data_read;
|
ea_data <= data_read;
|
END IF;
|
END IF;
|
|
|
IF writePC_add='1' THEN
|
IF writePC_add='1' THEN
|
data_write_tmp <= TG68_PC_add;
|
data_write_tmp <= TG68_PC_add;
|
ELSIF writePC='1' OR fetchOPC='1' OR interrupt='1' OR (trap_trap='1' AND decodeOPC='1') THEN --fetchOPC für Trap
|
ELSIF writePC='1' OR fetchOPC='1' OR interrupt='1' OR (trap_trap='1' AND decodeOPC='1') THEN --fetchOPC für Trap
|
data_write_tmp <= TG68_PC;
|
data_write_tmp <= TG68_PC;
|
ELSIF execOPC='1' OR (get_ea_now='1' AND ea_only='1') THEN --get_ea_now='1' AND ea_only='1' ist für pea
|
ELSIF execOPC='1' OR (get_ea_now='1' AND ea_only='1') THEN --get_ea_now='1' AND ea_only='1' ist für pea
|
data_write_tmp <= registerin(31 downto 8)&(registerin(7)OR exec_tas)®isterin(6 downto 0);
|
data_write_tmp <= registerin(31 downto 8)&(registerin(7)OR exec_tas)®isterin(6 downto 0);
|
ELSIF (exec_DIRECT='1' AND state="10") OR direct_data='1' THEN
|
ELSIF (exec_DIRECT='1' AND state="10") OR direct_data='1' THEN
|
data_write_tmp <= data_read;
|
data_write_tmp <= data_read;
|
IF movepl='1' THEN
|
IF movepl='1' THEN
|
data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0);
|
data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0);
|
END IF;
|
END IF;
|
ELSIF (movem_busy='1' AND datatype="10" AND movem_presub='1') OR movepl='1' THEN
|
ELSIF (movem_busy='1' AND datatype="10" AND movem_presub='1') OR movepl='1' THEN
|
data_write_tmp <= OP2out(15 downto 0)&OP2out(31 downto 16);
|
data_write_tmp <= OP2out(15 downto 0)&OP2out(31 downto 16);
|
ELSIF (NOT trapmake AND decodeOPC)='1' OR movem_busy='1' OR movepw='1' THEN
|
ELSIF (NOT trapmake AND decodeOPC)='1' OR movem_busy='1' OR movepw='1' THEN
|
data_write_tmp <= OP2out;
|
data_write_tmp <= OP2out;
|
ELSIF writeSR='1'THEN
|
ELSIF writeSR='1'THEN
|
data_write_tmp(15 downto 0) <= trap_SR(15 downto 8)& Flags(7 downto 0);
|
data_write_tmp(15 downto 0) <= trap_SR(15 downto 8)& Flags(7 downto 0);
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- set dest regaddr
|
-- set dest regaddr
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (opcode, rf_dest_addr_tmp, to_USP, Flags, trapmake, movem_addr, movem_presub, movem_regaddr, setbriefext, brief, setstackaddr, dest_hbits, dest_areg, data_is_source)
|
PROCESS (opcode, rf_dest_addr_tmp, to_USP, Flags, trapmake, movem_addr, movem_presub, movem_regaddr, setbriefext, brief, setstackaddr, dest_hbits, dest_areg, data_is_source)
|
BEGIN
|
BEGIN
|
rf_dest_addr <= rf_dest_addr_tmp;
|
rf_dest_addr <= rf_dest_addr_tmp;
|
IF rf_dest_addr_tmp(3 downto 0)="1111" AND to_USP='0' THEN
|
IF rf_dest_addr_tmp(3 downto 0)="1111" AND to_USP='0' THEN
|
rf_dest_addr(4) <= Flags(13) OR trapmake;
|
rf_dest_addr(4) <= Flags(13) OR trapmake;
|
END IF;
|
END IF;
|
IF movem_addr='1' THEN
|
IF movem_addr='1' THEN
|
IF movem_presub='1' THEN
|
IF movem_presub='1' THEN
|
rf_dest_addr_tmp <= "000"&(movem_regaddr XOR "1111");
|
rf_dest_addr_tmp <= "000"&(movem_regaddr XOR "1111");
|
ELSE
|
ELSE
|
rf_dest_addr_tmp <= "000"&movem_regaddr;
|
rf_dest_addr_tmp <= "000"&movem_regaddr;
|
END IF;
|
END IF;
|
ELSIF setbriefext='1' THEN
|
ELSIF setbriefext='1' THEN
|
rf_dest_addr_tmp <= ("000"&brief(15 downto 12));
|
rf_dest_addr_tmp <= ("000"&brief(15 downto 12));
|
ELSIF setstackaddr='1' THEN
|
ELSIF setstackaddr='1' THEN
|
rf_dest_addr_tmp <= "0001111";
|
rf_dest_addr_tmp <= "0001111";
|
ELSIF dest_hbits='1' THEN
|
ELSIF dest_hbits='1' THEN
|
rf_dest_addr_tmp <= "000"&dest_areg&opcode(11 downto 9);
|
rf_dest_addr_tmp <= "000"&dest_areg&opcode(11 downto 9);
|
ELSE
|
ELSE
|
IF opcode(5 downto 3)="000" OR data_is_source='1' THEN
|
IF opcode(5 downto 3)="000" OR data_is_source='1' THEN
|
rf_dest_addr_tmp <= "000"&dest_areg&opcode(2 downto 0);
|
rf_dest_addr_tmp <= "000"&dest_areg&opcode(2 downto 0);
|
ELSE
|
ELSE
|
rf_dest_addr_tmp <= "0001"&opcode(2 downto 0);
|
rf_dest_addr_tmp <= "0001"&opcode(2 downto 0);
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- set OP1
|
-- set OP1
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (reg_QA, OP1out_zero, from_SR, Flags, ea_data_OP1, set_store_in_tmp, ea_data)
|
PROCESS (reg_QA, OP1out_zero, from_SR, Flags, ea_data_OP1, set_store_in_tmp, ea_data)
|
BEGIN
|
BEGIN
|
OP1out <= reg_QA;
|
OP1out <= reg_QA;
|
IF OP1out_zero='1' THEN
|
IF OP1out_zero='1' THEN
|
OP1out <= (OTHERS => '0');
|
OP1out <= (OTHERS => '0');
|
ELSIF from_SR='1' THEN
|
ELSIF from_SR='1' THEN
|
OP1out(15 downto 0) <= Flags;
|
OP1out(15 downto 0) <= Flags;
|
ELSIF ea_data_OP1='1' AND set_store_in_tmp='1' THEN
|
ELSIF ea_data_OP1='1' AND set_store_in_tmp='1' THEN
|
OP1out <= ea_data;
|
OP1out <= ea_data;
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- set source regaddr
|
-- set source regaddr
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (opcode, Flags, movem_addr, movem_presub, movem_regaddr, source_lowbits, source_areg, from_USP, rf_source_addr_tmp)
|
PROCESS (opcode, Flags, movem_addr, movem_presub, movem_regaddr, source_lowbits, source_areg, from_USP, rf_source_addr_tmp)
|
BEGIN
|
BEGIN
|
rf_source_addr <= rf_source_addr_tmp;
|
rf_source_addr <= rf_source_addr_tmp;
|
IF rf_source_addr_tmp(3 downto 0)="1111" AND from_USP='0' THEN
|
IF rf_source_addr_tmp(3 downto 0)="1111" AND from_USP='0' THEN
|
rf_source_addr(4) <= Flags(13);
|
rf_source_addr(4) <= Flags(13);
|
END IF;
|
END IF;
|
IF movem_addr='1' THEN
|
IF movem_addr='1' THEN
|
IF movem_presub='1' THEN
|
IF movem_presub='1' THEN
|
rf_source_addr_tmp <= "000"&(movem_regaddr XOR "1111");
|
rf_source_addr_tmp <= "000"&(movem_regaddr XOR "1111");
|
ELSE
|
ELSE
|
rf_source_addr_tmp <= "000"&movem_regaddr;
|
rf_source_addr_tmp <= "000"&movem_regaddr;
|
END IF;
|
END IF;
|
ELSIF from_USP='1' THEN
|
ELSIF from_USP='1' THEN
|
rf_source_addr_tmp <= "0001111";
|
rf_source_addr_tmp <= "0001111";
|
ELSIF source_lowbits='1' THEN
|
ELSIF source_lowbits='1' THEN
|
rf_source_addr_tmp <= "000"&source_areg&opcode(2 downto 0);
|
rf_source_addr_tmp <= "000"&source_areg&opcode(2 downto 0);
|
ELSE
|
ELSE
|
rf_source_addr_tmp <= "000"&source_areg&opcode(11 downto 9);
|
rf_source_addr_tmp <= "000"&source_areg&opcode(11 downto 9);
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- set OP2
|
-- set OP2
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (OP2out, reg_QB, opcode, datatype, OP2out_one, exec_EXT, exec_MOVEQ, EXEC_ADDQ, use_direct_data, data_write_tmp,
|
PROCESS (OP2out, reg_QB, opcode, datatype, OP2out_one, exec_EXT, exec_MOVEQ, EXEC_ADDQ, use_direct_data, data_write_tmp,
|
ea_data_OP1, set_store_in_tmp, ea_data, movepl)
|
ea_data_OP1, set_store_in_tmp, ea_data, movepl)
|
BEGIN
|
BEGIN
|
OP2out(15 downto 0) <= reg_QB(15 downto 0);
|
OP2out(15 downto 0) <= reg_QB(15 downto 0);
|
OP2out(31 downto 16) <= (OTHERS => OP2out(15));
|
OP2out(31 downto 16) <= (OTHERS => OP2out(15));
|
IF OP2out_one='1' THEN
|
IF OP2out_one='1' THEN
|
OP2out(15 downto 0) <= "1111111111111111";
|
OP2out(15 downto 0) <= "1111111111111111";
|
ELSIF exec_EXT='1' THEN
|
ELSIF exec_EXT='1' THEN
|
IF opcode(6)='0' THEN --ext.w
|
IF opcode(6)='0' THEN --ext.w
|
OP2out(15 downto 8) <= (OTHERS => OP2out(7));
|
OP2out(15 downto 8) <= (OTHERS => OP2out(7));
|
END IF;
|
END IF;
|
ELSIF use_direct_data='1' THEN
|
ELSIF use_direct_data='1' THEN
|
OP2out <= data_write_tmp;
|
OP2out <= data_write_tmp;
|
ELSIF ea_data_OP1='0' AND set_store_in_tmp='1' THEN
|
ELSIF ea_data_OP1='0' AND set_store_in_tmp='1' THEN
|
OP2out <= ea_data;
|
OP2out <= ea_data;
|
ELSIF exec_MOVEQ='1' THEN
|
ELSIF exec_MOVEQ='1' THEN
|
OP2out(7 downto 0) <= opcode(7 downto 0);
|
OP2out(7 downto 0) <= opcode(7 downto 0);
|
OP2out(15 downto 8) <= (OTHERS => opcode(7));
|
OP2out(15 downto 8) <= (OTHERS => opcode(7));
|
ELSIF exec_ADDQ='1' THEN
|
ELSIF exec_ADDQ='1' THEN
|
OP2out(2 downto 0) <= opcode(11 downto 9);
|
OP2out(2 downto 0) <= opcode(11 downto 9);
|
IF opcode(11 downto 9)="000" THEN
|
IF opcode(11 downto 9)="000" THEN
|
OP2out(3) <='1';
|
OP2out(3) <='1';
|
ELSE
|
ELSE
|
OP2out(3) <='0';
|
OP2out(3) <='0';
|
END IF;
|
END IF;
|
OP2out(15 downto 4) <= (OTHERS => '0');
|
OP2out(15 downto 4) <= (OTHERS => '0');
|
ELSIF datatype="10" OR movepl='1' THEN
|
ELSIF datatype="10" OR movepl='1' THEN
|
OP2out(31 downto 16) <= reg_QB(31 downto 16);
|
OP2out(31 downto 16) <= reg_QB(31 downto 16);
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- addsub
|
-- addsub
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (OP1out, OP2out, presub, postadd, execOPC, OP2out_one, datatype, use_SP, use_XZFlag, use_XFlag, Flags, setaddsub)
|
PROCESS (OP1out, OP2out, presub, postadd, execOPC, OP2out_one, datatype, use_SP, use_XZFlag, use_XFlag, Flags, setaddsub)
|
BEGIN
|
BEGIN
|
addsub_a <= OP1out;
|
addsub_a <= OP1out;
|
addsub_b <= OP2out;
|
addsub_b <= OP2out;
|
addsub <= NOT presub;
|
addsub <= NOT presub;
|
c_in(0) <='0';
|
c_in(0) <='0';
|
IF execOPC='0' AND OP2out_one='0' THEN
|
IF execOPC='0' AND OP2out_one='0' THEN
|
IF datatype="00" AND use_SP='0' THEN
|
IF datatype="00" AND use_SP='0' THEN
|
addsub_b <= "00000000000000000000000000000001";
|
addsub_b <= "00000000000000000000000000000001";
|
ELSIF datatype="10" AND (presub OR postadd)='1' THEN
|
ELSIF datatype="10" AND (presub OR postadd)='1' THEN
|
addsub_b <= "00000000000000000000000000000100";
|
addsub_b <= "00000000000000000000000000000100";
|
ELSE
|
ELSE
|
addsub_b <= "00000000000000000000000000000010";
|
addsub_b <= "00000000000000000000000000000010";
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
IF (use_XZFlag='1' OR use_XFlag='1') AND Flags(4)='1' THEN
|
IF (use_XZFlag='1' OR use_XFlag='1') AND Flags(4)='1' THEN
|
c_in(0) <= '1';
|
c_in(0) <= '1';
|
END IF;
|
END IF;
|
addsub <= setaddsub;
|
addsub <= setaddsub;
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Write Reg
|
-- Write Reg
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (clkena, OP1in, datatype, presub, postadd, endOPC, regwrena, state, execOPC, last_data_read, movem_addr, rf_dest_addr, reg_QA)
|
PROCESS (clkena, OP1in, datatype, presub, postadd, endOPC, regwrena, state, execOPC, last_data_read, movem_addr, rf_dest_addr, reg_QA, maskzero)
|
BEGIN
|
BEGIN
|
Lwrena <= '0';
|
Lwrena <= '0';
|
Hwrena <= '0';
|
Hwrena <= '0';
|
registerin <= OP1in;
|
registerin <= OP1in;
|
|
|
IF (presub='1' OR postadd='1') AND endOPC='0' THEN -- -(An)+
|
IF (presub='1' OR postadd='1') AND endOPC='0' THEN -- -(An)+
|
Hwrena <= '1';
|
Hwrena <= '1';
|
Lwrena <= '1';
|
Lwrena <= '1';
|
ELSIF Regwrena='1' THEN --read (mem)
|
ELSIF Regwrena='1' AND maskzero='0' THEN --read (mem)
|
Lwrena <= '1';
|
Lwrena <= '1';
|
CASE datatype IS
|
CASE datatype IS
|
WHEN "00" => --BYTE
|
WHEN "00" => --BYTE
|
registerin(15 downto 8) <= reg_QA(15 downto 8);
|
registerin(15 downto 8) <= reg_QA(15 downto 8);
|
WHEN "01" => --WORD
|
WHEN "01" => --WORD
|
IF rf_dest_addr(3)='1' OR movem_addr='1' THEN
|
IF rf_dest_addr(3)='1' OR movem_addr='1' THEN
|
Hwrena <='1';
|
Hwrena <='1';
|
END IF;
|
END IF;
|
WHEN OTHERS => --LONG
|
WHEN OTHERS => --LONG
|
Hwrena <= '1';
|
Hwrena <= '1';
|
END CASE;
|
END CASE;
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
--ALU
|
--ALU
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
PROCESS (opcode, OP1in, OP1out, OP2out, datatype, c_out, exec_ABCD, exec_SBCD, exec_CPMAW, exec_MOVESR, bits_out, Flags, flag_z, use_XZFlag, addsub_ofl,
|
PROCESS (opcode, OP1in, OP1out, OP2out, datatype, c_out, exec_ABCD, exec_SBCD, exec_CPMAW, exec_MOVESR, bits_out, Flags, flag_z, use_XZFlag, addsub_ofl,
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dummy_s, dummy_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, addsub_q, movem_addr, data_read, exec_MULU, exec_DIVU, exec_OR,
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dummy_s, dummy_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, addsub_q, movem_addr, data_read, exec_MULU, exec_DIVU, exec_OR,
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exec_AND, exec_Scc, exec_EOR, exec_MOVE, exec_exg, exec_ROT, execOPC, exec_swap, exec_Bits, rot_out, dummy_mulu, dummy_div, save_memaddr, memaddr,
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exec_AND, exec_Scc, exec_EOR, exec_MOVE, exec_exg, exec_ROT, execOPC, exec_swap, exec_Bits, rot_out, dummy_mulu, dummy_div, save_memaddr, memaddr,
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memaddr_in, ea_only, get_ea_now)
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memaddr_in, ea_only, get_ea_now)
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BEGIN
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BEGIN
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--BCD_ARITH-------------------------------------------------------------------
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--BCD_ARITH-------------------------------------------------------------------
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--ADC
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--ADC
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dummy_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0'));
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dummy_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0'));
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niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4));
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niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4));
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niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
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niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
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niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc);
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niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc);
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niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
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niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
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--SBC
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--SBC
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dummy_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0'));
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dummy_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0'));
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nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4));
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nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4));
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nibs_lc <= nibs_l(5);
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nibs_lc <= nibs_l(5);
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nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc);
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nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc);
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nibs_hc <= nibs_h(5);
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nibs_hc <= nibs_h(5);
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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flag_z <= "000";
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flag_z <= "000";
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OP1in <= addsub_q;
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OP1in <= addsub_q;
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IF movem_addr='1' THEN
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IF movem_addr='1' THEN
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OP1in <= data_read;
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OP1in <= data_read;
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ELSIF exec_ABCD='1' THEN
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ELSIF exec_ABCD='1' THEN
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OP1in(7 downto 0) <= dummy_a(7 downto 0);
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OP1in(7 downto 0) <= dummy_a(7 downto 0);
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ELSIF exec_SBCD='1' THEN
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ELSIF exec_SBCD='1' THEN
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OP1in(7 downto 0) <= dummy_s(7 downto 0);
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OP1in(7 downto 0) <= dummy_s(7 downto 0);
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ELSIF exec_MULU='1' THEN
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ELSIF exec_MULU='1' THEN
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OP1in <= dummy_mulu;
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OP1in <= dummy_mulu;
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ELSIF exec_DIVU='1' AND execOPC='1' THEN
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ELSIF exec_DIVU='1' AND execOPC='1' THEN
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OP1in <= dummy_div;
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OP1in <= dummy_div;
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ELSIF exec_OR='1' THEN
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ELSIF exec_OR='1' THEN
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OP1in <= OP2out OR OP1out;
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OP1in <= OP2out OR OP1out;
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ELSIF exec_AND='1' OR exec_Scc='1' THEN
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ELSIF exec_AND='1' OR exec_Scc='1' THEN
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OP1in <= OP2out AND OP1out;
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OP1in <= OP2out AND OP1out;
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ELSIF exec_EOR='1' THEN
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ELSIF exec_EOR='1' THEN
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OP1in <= OP2out XOR OP1out;
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OP1in <= OP2out XOR OP1out;
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ELSIF exec_MOVE='1' OR exec_exg='1' THEN
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ELSIF exec_MOVE='1' OR exec_exg='1' THEN
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OP1in <= OP2out;
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OP1in <= OP2out;
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ELSIF exec_ROT='1' THEN
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ELSIF exec_ROT='1' THEN
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OP1in <= rot_out;
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OP1in <= rot_out;
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ELSIF save_memaddr='1' THEN
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ELSIF save_memaddr='1' THEN
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OP1in <= memaddr;
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OP1in <= memaddr;
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ELSIF get_ea_now='1' AND ea_only='1' THEN
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ELSIF get_ea_now='1' AND ea_only='1' THEN
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OP1in <= memaddr_in;
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OP1in <= memaddr_in;
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ELSIF exec_swap='1' THEN
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ELSIF exec_swap='1' THEN
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OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
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OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
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ELSIF exec_bits='1' THEN
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ELSIF exec_bits='1' THEN
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OP1in <= bits_out;
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OP1in <= bits_out;
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ELSIF exec_MOVESR='1' THEN
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ELSIF exec_MOVESR='1' THEN
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OP1in(15 downto 0) <= Flags;
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OP1in(15 downto 0) <= Flags;
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END IF;
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END IF;
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IF use_XZFlag='1' AND flags(2)='0' THEN
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IF use_XZFlag='1' AND flags(2)='0' THEN
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flag_z <= "000";
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flag_z <= "000";
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ELSIF OP1in(7 downto 0)="00000000" THEN
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ELSIF OP1in(7 downto 0)="00000000" THEN
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flag_z(0) <= '1';
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flag_z(0) <= '1';
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IF OP1in(15 downto 8)="00000000" THEN
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IF OP1in(15 downto 8)="00000000" THEN
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flag_z(1) <= '1';
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flag_z(1) <= '1';
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IF OP1in(31 downto 16)="0000000000000000" THEN
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IF OP1in(31 downto 16)="0000000000000000" THEN
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flag_z(2) <= '1';
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flag_z(2) <= '1';
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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-- --Flags NZVC
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-- --Flags NZVC
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IF datatype="00" THEN --Byte
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IF datatype="00" THEN --Byte
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set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
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set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
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IF exec_ABCD='1' THEN
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IF exec_ABCD='1' THEN
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set_flags(0) <= dummy_a(8);
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set_flags(0) <= dummy_a(8);
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ELSIF exec_SBCD='1' THEN
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ELSIF exec_SBCD='1' THEN
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set_flags(0) <= dummy_s(8);
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set_flags(0) <= dummy_s(8);
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END IF;
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END IF;
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ELSIF datatype="10" OR exec_CPMAW='1' THEN --Long
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ELSIF datatype="10" OR exec_CPMAW='1' THEN --Long
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set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
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set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
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ELSE --Word
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ELSE --Word
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set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
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set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--Flags
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--Flags
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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PROCESS (clk, reset, opcode)
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PROCESS (clk, reset, opcode)
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BEGIN
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BEGIN
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IF reset='0' THEN
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IF reset='0' THEN
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Flags(13) <= '1';
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Flags(13) <= '1';
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SVmode <= '1';
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SVmode <= '1';
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Flags(10 downto 8) <= "111";
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Flags(10 downto 8) <= "111";
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ELSIF rising_edge(clk) THEN
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ELSIF rising_edge(clk) THEN
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IF clkena = '1' THEN
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IF clkena = '1' THEN
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IF directSR='1' THEN
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IF directSR='1' THEN
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Flags <= data_read(15 downto 0);
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Flags <= data_read(15 downto 0);
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END IF;
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END IF;
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IF directCCR='1' THEN
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IF directCCR='1' THEN
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Flags(7 downto 0) <= data_read(7 downto 0);
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Flags(7 downto 0) <= data_read(7 downto 0);
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END IF;
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END IF;
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IF interrupt='1' THEN
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IF interrupt='1' THEN
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Flags(10 downto 8) <=rIPL_nr;
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Flags(10 downto 8) <=rIPL_nr;
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SVmode <= '1';
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SVmode <= '1';
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END IF;
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END IF;
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IF writeSR='1' OR interrupt='1' THEN
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IF writeSR='1' OR interrupt='1' THEN
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Flags(13) <='1';
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Flags(13) <='1';
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END IF;
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END IF;
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IF endOPC='1' AND to_SR='0' THEN
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IF endOPC='1' AND to_SR='0' THEN
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SVmode <= Flags(13);
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SVmode <= Flags(13);
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END IF;
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END IF;
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IF execOPC='1' AND to_SR='1' THEN
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IF execOPC='1' AND to_SR='1' THEN
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Flags(7 downto 0) <= OP1in(7 downto 0); --CCR
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Flags(7 downto 0) <= OP1in(7 downto 0); --CCR
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IF datatype="01" AND (opcode(14)='0' OR opcode(9)='1') THEN --move to CCR wird als word gespeichert
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IF datatype="01" AND (opcode(14)='0' OR opcode(9)='1') THEN --move to CCR wird als word gespeichert
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Flags(15 downto 8) <= OP1in(15 downto 8); --SR
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Flags(15 downto 8) <= OP1in(15 downto 8); --SR
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SVmode <= OP1in(13);
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SVmode <= OP1in(13);
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END IF;
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END IF;
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ELSIF Z_error='1' THEN
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ELSIF Z_error='1' THEN
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IF opcode(8)='0' THEN
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IF opcode(8)='0' THEN
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Flags(3 downto 0) <= "1000";
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Flags(3 downto 0) <= "1000";
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ELSE
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ELSE
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Flags(3 downto 0) <= "0100";
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Flags(3 downto 0) <= "0100";
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END IF;
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END IF;
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ELSIF no_Flags='0' AND trapmake='0' THEN
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ELSIF no_Flags='0' AND trapmake='0' THEN
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IF exec_ADD='1' THEN
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IF exec_ADD='1' THEN
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Flags(4) <= set_flags(0);
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Flags(4) <= set_flags(0);
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ELSIF exec_ROT='1' AND rot_bits/="11" AND rot_nop='0' THEN
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ELSIF exec_ROT='1' AND rot_bits/="11" AND rot_nop='0' THEN
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Flags(4) <= rot_XC;
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Flags(4) <= rot_XC;
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END IF;
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END IF;
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IF (exec_ADD OR exec_CMP)='1' THEN
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IF (exec_ADD OR exec_CMP)='1' THEN
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Flags(3 downto 0) <= set_flags;
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Flags(3 downto 0) <= set_flags;
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ELSIF decodeOPC='1' and set_exec_ROT='1' THEN
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ELSIF decodeOPC='1' and set_exec_ROT='1' THEN
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Flags(1) <= '0';
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Flags(1) <= '0';
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ELSIF exec_DIVU='1' THEN
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ELSIF exec_DIVU='1' THEN
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IF set_V_Flag='1' THEN
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IF set_V_Flag='1' THEN
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Flags(3 downto 0) <= "1010";
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Flags(3 downto 0) <= "1010";
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ELSE
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ELSE
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Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
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Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
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END IF;
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END IF;
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ELSIF exec_OR='1' OR exec_AND='1' OR exec_EOR='1' OR exec_MOVE='1' OR exec_swap='1' OR exec_MULU='1' THEN
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ELSIF exec_OR='1' OR exec_AND='1' OR exec_EOR='1' OR exec_MOVE='1' OR exec_swap='1' OR exec_MULU='1' THEN
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Flags(3 downto 0) <= set_flags(3 downto 2)&"00";
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Flags(3 downto 0) <= set_flags(3 downto 2)&"00";
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ELSIF exec_ROT='1' THEN
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ELSIF exec_ROT='1' THEN
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Flags(3 downto 2) <= set_flags(3 downto 2);
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Flags(3 downto 2) <= set_flags(3 downto 2);
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Flags(0) <= rot_XC;
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Flags(0) <= rot_XC;
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IF rot_bits="00" THEN --ASL/ASR
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IF rot_bits="00" THEN --ASL/ASR
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Flags(1) <= ((set_flags(3) XOR rot_rot) OR Flags(1));
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Flags(1) <= ((set_flags(3) XOR rot_rot) OR Flags(1));
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END IF;
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END IF;
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ELSIF exec_bits='1' THEN
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ELSIF exec_bits='1' THEN
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Flags(2) <= NOT one_bit_in;
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Flags(2) <= NOT one_bit_in;
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- execute opcode
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-- execute opcode
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt,
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PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt, rot_nop,
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Z_error, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
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Z_error, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
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Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec, c_out, OP1out, micro_state)
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Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec, c_out, OP1out, micro_state)
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BEGIN
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BEGIN
|
TG68_PC_br8 <= '0';
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TG68_PC_br8 <= '0';
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TG68_PC_brw <= '0';
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TG68_PC_brw <= '0';
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TG68_PC_nop <= '0';
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TG68_PC_nop <= '0';
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setstate <= "00";
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setstate <= "00";
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Regwrena <= '0';
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Regwrena <= '0';
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postadd <= '0';
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postadd <= '0';
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presub <= '0';
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presub <= '0';
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movem_presub <= '0';
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movem_presub <= '0';
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setaddsub <= '1';
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setaddsub <= '1';
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setaddrlong <= '0';
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setaddrlong <= '0';
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setnextpass <= '0';
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setnextpass <= '0';
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regdirectsource <= '0';
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regdirectsource <= '0';
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setdisp <= '0';
|
setdisp <= '0';
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setdispbyte <= '0';
|
setdispbyte <= '0';
|
setdispbrief <= '0';
|
setdispbrief <= '0';
|
setbriefext <= '0';
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setbriefext <= '0';
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setgetbrief <= '0';
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setgetbrief <= '0';
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longreaddirect <= '0';
|
longreaddirect <= '0';
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dest_areg <= '0';
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dest_areg <= '0';
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source_areg <= '0';
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source_areg <= '0';
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data_is_source <= '0';
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data_is_source <= '0';
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write_back <= '0';
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write_back <= '0';
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setstackaddr <= '0';
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setstackaddr <= '0';
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writePC <= '0';
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writePC <= '0';
|
writePC_add <= '0';
|
writePC_add <= '0';
|
set_TG68_PC_dec <= '0';
|
set_TG68_PC_dec <= '0';
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set_directPC <= '0';
|
set_directPC <= '0';
|
set_exec_ADD <= '0';
|
set_exec_ADD <= '0';
|
set_exec_OR <= '0';
|
set_exec_OR <= '0';
|
set_exec_AND <= '0';
|
set_exec_AND <= '0';
|
set_exec_EOR <= '0';
|
set_exec_EOR <= '0';
|
set_exec_MOVE <= '0';
|
set_exec_MOVE <= '0';
|
set_exec_MOVEQ <= '0';
|
set_exec_MOVEQ <= '0';
|
set_exec_MOVESR <= '0';
|
set_exec_MOVESR <= '0';
|
set_exec_ADDQ <= '0';
|
set_exec_ADDQ <= '0';
|
set_exec_CMP <= '0';
|
set_exec_CMP <= '0';
|
set_exec_ROT <= '0';
|
set_exec_ROT <= '0';
|
set_exec_EXT <= '0';
|
set_exec_EXT <= '0';
|
set_exec_CPMAW <= '0';
|
set_exec_CPMAW <= '0';
|
OP2out_one <= '0';
|
OP2out_one <= '0';
|
ea_to_pc <= '0';
|
ea_to_pc <= '0';
|
ea_build <= '0';
|
ea_build <= '0';
|
get_ea_now <= '0';
|
get_ea_now <= '0';
|
rot_bits <= "XX";
|
rot_bits <= "XX";
|
set_rot_nop <= '0';
|
set_rot_nop <= '0';
|
set_rot_cnt <= "000001";
|
set_rot_cnt <= "000001";
|
set_movem_busy <= '0';
|
set_movem_busy <= '0';
|
set_get_movem_mask <= '0';
|
set_get_movem_mask <= '0';
|
save_memaddr <= '0';
|
save_memaddr <= '0';
|
set_mem_addsub <= '0';
|
set_mem_addsub <= '0';
|
exec_exg <= '0';
|
exec_exg <= '0';
|
exec_swap <= '0';
|
exec_swap <= '0';
|
exec_Bits <= '0';
|
exec_Bits <= '0';
|
set_get_bitnumber <= '0';
|
set_get_bitnumber <= '0';
|
dest_hbits <= '0';
|
dest_hbits <= '0';
|
source_lowbits <= '0';
|
source_lowbits <= '0';
|
set_mem_rega <= '0';
|
set_mem_rega <= '0';
|
ea_data_OP1 <= '0';
|
ea_data_OP1 <= '0';
|
ea_only <= '0';
|
ea_only <= '0';
|
set_direct_data <= '0';
|
set_direct_data <= '0';
|
set_get_extendedOPC <= '0';
|
set_get_extendedOPC <= '0';
|
set_exec_tas <= '0';
|
set_exec_tas <= '0';
|
OP1out_zero <= '0';
|
OP1out_zero <= '0';
|
use_XZFlag <= '0';
|
use_XZFlag <= '0';
|
use_XFlag <= '0';
|
use_XFlag <= '0';
|
set_exec_ABCD <= '0';
|
set_exec_ABCD <= '0';
|
set_exec_SBCD <= '0';
|
set_exec_SBCD <= '0';
|
set_exec_MULU <= '0';
|
set_exec_MULU <= '0';
|
set_exec_DIVU <= '0';
|
set_exec_DIVU <= '0';
|
set_exec_Scc <= '0';
|
set_exec_Scc <= '0';
|
trap_illegal <='0';
|
trap_illegal <='0';
|
trap_priv <='0';
|
trap_priv <='0';
|
trap_1010 <='0';
|
trap_1010 <='0';
|
trap_1111 <='0';
|
trap_1111 <='0';
|
trap_trap <='0';
|
trap_trap <='0';
|
trap_trapv <= '0';
|
trap_trapv <= '0';
|
trapmake <='0';
|
trapmake <='0';
|
set_vectoraddr <='0';
|
set_vectoraddr <='0';
|
writeSR <= '0';
|
writeSR <= '0';
|
set_directSR <= '0';
|
set_directSR <= '0';
|
set_directCCR <= '0';
|
set_directCCR <= '0';
|
set_stop <= '0';
|
set_stop <= '0';
|
from_SR <= '0';
|
from_SR <= '0';
|
to_SR <= '0';
|
to_SR <= '0';
|
from_USP <= '0';
|
from_USP <= '0';
|
to_USP <= '0';
|
to_USP <= '0';
|
illegal_write_mode <= '0';
|
illegal_write_mode <= '0';
|
illegal_read_mode <= '0';
|
illegal_read_mode <= '0';
|
illegal_byteaddr <= '0';
|
illegal_byteaddr <= '0';
|
no_Flags <= '0';
|
no_Flags <= '0';
|
set_PCmarker <= '0';
|
set_PCmarker <= '0';
|
use_SP <= '0';
|
use_SP <= '0';
|
set_Z_error <= '0';
|
set_Z_error <= '0';
|
wait_mem_byte <= '0';
|
wait_mem_byte <= '0';
|
set_movepl <= '0';
|
set_movepl <= '0';
|
set_movepw <= '0';
|
set_movepw <= '0';
|
|
|
trap_chk <= '0';
|
trap_chk <= '0';
|
next_micro_state <= idle;
|
next_micro_state <= idle;
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
--Sourcepass
|
--Sourcepass
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
IF ea_only='0' AND get_ea_now='1' THEN
|
IF ea_only='0' AND get_ea_now='1' THEN
|
setstate <= "10";
|
setstate <= "10";
|
END IF;
|
END IF;
|
|
|
IF ea_build='1' THEN
|
IF ea_build='1' THEN
|
CASE opcode(5 downto 3) IS --source
|
CASE opcode(5 downto 3) IS --source
|
WHEN "010"|"011"|"100" => -- -(An)+
|
WHEN "010"|"011"|"100" => -- -(An)+
|
get_ea_now <='1';
|
get_ea_now <='1';
|
setnextpass <= '1';
|
setnextpass <= '1';
|
IF opcode(4)='1' THEN
|
IF opcode(4)='1' THEN
|
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
ELSE
|
ELSE
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
END IF;
|
END IF;
|
IF opcode(3)='1' THEN --(An)+
|
IF opcode(3)='1' THEN --(An)+
|
postadd <= '1';
|
postadd <= '1';
|
IF opcode(2 downto 0)="111" THEN
|
IF opcode(2 downto 0)="111" THEN
|
use_SP <= '1';
|
use_SP <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF opcode(5)='1' THEN -- -(An)
|
IF opcode(5)='1' THEN -- -(An)
|
presub <= '1';
|
presub <= '1';
|
IF opcode(2 downto 0)="111" THEN
|
IF opcode(2 downto 0)="111" THEN
|
use_SP <= '1';
|
use_SP <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF opcode(4 downto 3)/="10" THEN
|
IF opcode(4 downto 3)/="10" THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
WHEN "101" => --(d16,An)
|
WHEN "101" => --(d16,An)
|
next_micro_state <= ld_dAn1;
|
next_micro_state <= ld_dAn1;
|
setgetbrief <='1';
|
setgetbrief <='1';
|
set_mem_regA <= '1';
|
set_mem_regA <= '1';
|
WHEN "110" => --(d8,An,Xn)
|
WHEN "110" => --(d8,An,Xn)
|
next_micro_state <= ld_AnXn1;
|
next_micro_state <= ld_AnXn1;
|
setgetbrief <='1';
|
setgetbrief <='1';
|
set_mem_regA <= '1';
|
set_mem_regA <= '1';
|
WHEN "111" =>
|
WHEN "111" =>
|
CASE opcode(2 downto 0) IS
|
CASE opcode(2 downto 0) IS
|
WHEN "000" => --(xxxx).w
|
WHEN "000" => --(xxxx).w
|
next_micro_state <= ld_nn;
|
next_micro_state <= ld_nn;
|
WHEN "001" => --(xxxx).l
|
WHEN "001" => --(xxxx).l
|
longreaddirect <= '1';
|
longreaddirect <= '1';
|
next_micro_state <= ld_nn;
|
next_micro_state <= ld_nn;
|
WHEN "010" => --(d16,PC)
|
WHEN "010" => --(d16,PC)
|
next_micro_state <= ld_dAn1;
|
next_micro_state <= ld_dAn1;
|
setgetbrief <= '1';
|
setgetbrief <= '1';
|
set_PCmarker <= '1';
|
set_PCmarker <= '1';
|
WHEN "011" => --(d8,PC,Xn)
|
WHEN "011" => --(d8,PC,Xn)
|
next_micro_state <= ld_AnXn1;
|
next_micro_state <= ld_AnXn1;
|
setgetbrief <= '1';
|
setgetbrief <= '1';
|
set_PCmarker <= '1';
|
set_PCmarker <= '1';
|
WHEN "100" => --#data
|
WHEN "100" => --#data
|
setnextpass <= '1';
|
setnextpass <= '1';
|
set_direct_data <= '1';
|
set_direct_data <= '1';
|
IF datatype="10" THEN
|
IF datatype="10" THEN
|
longreaddirect <= '1';
|
longreaddirect <= '1';
|
END IF;
|
END IF;
|
WHEN OTHERS =>
|
WHEN OTHERS =>
|
END CASE;
|
END CASE;
|
WHEN OTHERS =>
|
WHEN OTHERS =>
|
END CASE;
|
END CASE;
|
END IF;
|
END IF;
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
--prepere opcode
|
--prepere opcode
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
CASE opcode(7 downto 6) IS
|
CASE opcode(7 downto 6) IS
|
WHEN "00" => datatype <= "00"; --Byte
|
WHEN "00" => datatype <= "00"; --Byte
|
WHEN "01" => datatype <= "01"; --Word
|
WHEN "01" => datatype <= "01"; --Word
|
WHEN OTHERS => datatype <= "10"; --Long
|
WHEN OTHERS => datatype <= "10"; --Long
|
END CASE;
|
END CASE;
|
|
|
IF execOPC='1' AND endOPC='0' AND exec_write_back='1' THEN
|
IF execOPC='1' AND endOPC='0' AND exec_write_back='1' THEN
|
setstate <="11";
|
setstate <="11";
|
END IF;
|
END IF;
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
--test illegal mode
|
--test illegal mode
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
IF (opcode(5 downto 3)="111" AND opcode(2 downto 1)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
|
IF (opcode(5 downto 3)="111" AND opcode(2 downto 1)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
|
illegal_write_mode <= '1';
|
illegal_write_mode <= '1';
|
END IF;
|
END IF;
|
IF (opcode(5 downto 2)="1111" AND opcode(1 downto 0)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
|
IF (opcode(5 downto 2)="1111" AND opcode(1 downto 0)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
|
illegal_read_mode <= '1';
|
illegal_read_mode <= '1';
|
END IF;
|
END IF;
|
IF opcode(5 downto 3)="001" AND datatype="00" THEN
|
IF opcode(5 downto 3)="001" AND datatype="00" THEN
|
illegal_byteaddr <= '1';
|
illegal_byteaddr <= '1';
|
END IF;
|
END IF;
|
|
|
|
|
CASE opcode(15 downto 12) IS
|
CASE opcode(15 downto 12) IS
|
-- 0000 ----------------------------------------------------------------------------
|
-- 0000 ----------------------------------------------------------------------------
|
WHEN "0000" =>
|
WHEN "0000" =>
|
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
|
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
|
datatype <= "00"; --Byte
|
datatype <= "00"; --Byte
|
use_SP <= '1';
|
use_SP <= '1';
|
no_Flags <='1';
|
no_Flags <='1';
|
IF opcode(7)='0' THEN
|
IF opcode(7)='0' THEN
|
set_exec_move <= '1';
|
set_exec_move <= '1';
|
set_movepl <= '1';
|
set_movepl <= '1';
|
END IF;
|
END IF;
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
IF opcode(7)='0' THEN
|
IF opcode(7)='0' THEN
|
set_direct_data <= '1';
|
set_direct_data <= '1';
|
END IF;
|
END IF;
|
next_micro_state <= movep1;
|
next_micro_state <= movep1;
|
setgetbrief <='1';
|
setgetbrief <='1';
|
set_mem_regA <= '1';
|
set_mem_regA <= '1';
|
END IF;
|
END IF;
|
IF opcode(7)='0' AND endOPC='1' THEN
|
IF opcode(7)='0' AND endOPC='1' THEN
|
IF opcode(6)='1' THEN
|
IF opcode(6)='1' THEN
|
datatype <= "10"; --Long
|
datatype <= "10"; --Long
|
ELSE
|
ELSE
|
datatype <= "01"; --Word
|
datatype <= "01"; --Word
|
END IF;
|
END IF;
|
dest_hbits <='1';
|
dest_hbits <='1';
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
IF opcode(8)='1' OR opcode(11 downto 8)="1000" THEN --Bits
|
IF opcode(8)='1' OR opcode(11 downto 8)="1000" THEN --Bits
|
IF execOPC='1' AND get_extendedOPC='0' THEN
|
IF execOPC='1' AND get_extendedOPC='0' THEN
|
IF opcode(7 downto 6)/="00" AND endOPC='1' THEN
|
IF opcode(7 downto 6)/="00" AND endOPC='1' THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
exec_Bits <= '1';
|
exec_Bits <= '1';
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
END IF;
|
END IF;
|
-- IF get_extendedOPC='1' THEN
|
-- IF get_extendedOPC='1' THEN
|
-- datatype <= "01"; --Word
|
-- datatype <= "01"; --Word
|
-- ELS
|
-- ELS
|
IF opcode(5 downto 4)="00" THEN
|
IF opcode(5 downto 4)="00" THEN
|
datatype <= "10"; --Long
|
datatype <= "10"; --Long
|
ELSE
|
ELSE
|
datatype <= "00"; --Byte
|
datatype <= "00"; --Byte
|
IF opcode(7 downto 6)/="00" THEN
|
IF opcode(7 downto 6)/="00" THEN
|
write_back <= '1';
|
write_back <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
IF opcode(8)='0' THEN
|
IF opcode(8)='0' THEN
|
IF opcode(5 downto 4)/="00" THEN --Dn, An
|
IF opcode(5 downto 4)/="00" THEN --Dn, An
|
set_get_extendedOPC <= '1';
|
set_get_extendedOPC <= '1';
|
END IF;
|
END IF;
|
set_get_bitnumber <= '1';
|
set_get_bitnumber <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
ELSE --andi, ...xxxi
|
ELSE --andi, ...xxxi
|
IF opcode(11 downto 8)="0000" THEN --ORI
|
IF opcode(11 downto 8)="0000" THEN --ORI
|
set_exec_OR <= '1';
|
set_exec_OR <= '1';
|
END IF;
|
END IF;
|
IF opcode(11 downto 8)="0010" THEN --ANDI
|
IF opcode(11 downto 8)="0010" THEN --ANDI
|
set_exec_AND <= '1';
|
set_exec_AND <= '1';
|
END IF;
|
END IF;
|
IF opcode(11 downto 8)="0100" OR opcode(11 downto 8)="0110" THEN --SUBI, ADDI
|
IF opcode(11 downto 8)="0100" OR opcode(11 downto 8)="0110" THEN --SUBI, ADDI
|
set_exec_ADD <= '1';
|
set_exec_ADD <= '1';
|
END IF;
|
END IF;
|
IF opcode(11 downto 8)="1010" THEN --EORI
|
IF opcode(11 downto 8)="1010" THEN --EORI
|
set_exec_EOR <= '1';
|
set_exec_EOR <= '1';
|
END IF;
|
END IF;
|
IF opcode(11 downto 8)="1100" THEN --CMPI
|
IF opcode(11 downto 8)="1100" THEN --CMPI
|
set_exec_CMP <= '1';
|
set_exec_CMP <= '1';
|
ELSIF trapmake='0' THEN
|
ELSIF trapmake='0' THEN
|
write_back <= '1';
|
write_back <= '1';
|
END IF;
|
END IF;
|
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec_AND OR set_exec_OR OR set_exec_EOR)='1' THEN --SR
|
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec_AND OR set_exec_OR OR set_exec_EOR)='1' THEN --SR
|
-- IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="1010") THEN --SR
|
-- IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="1010") THEN --SR
|
IF SVmode='0' AND opcode(6)='1' THEN --SR
|
IF SVmode='0' AND opcode(6)='1' THEN --SR
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
ELSE
|
ELSE
|
from_SR <= '1';
|
from_SR <= '1';
|
to_SR <= '1';
|
to_SR <= '1';
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
setnextpass <= '1';
|
setnextpass <= '1';
|
set_direct_data <= '1';
|
set_direct_data <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
IF opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="0100" --ANDI, ORI, SUBI
|
IF opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="0100" --ANDI, ORI, SUBI
|
OR opcode(11 downto 8)="0110" OR opcode(11 downto 8)="1010" OR opcode(11 downto 8)="1100" THEN --ADDI, EORI, CMPI
|
OR opcode(11 downto 8)="0110" OR opcode(11 downto 8)="1010" OR opcode(11 downto 8)="1100" THEN --ADDI, EORI, CMPI
|
-- IF (set_exec_AND OR set_exec_OR OR set_exec_ADD --ANDI, ORI, SUBI
|
-- IF (set_exec_AND OR set_exec_OR OR set_exec_ADD --ANDI, ORI, SUBI
|
-- OR set_exec_EOR OR set_exec_CMP)='1' THEN --ADDI, EORI, CMPI
|
-- OR set_exec_EOR OR set_exec_CMP)='1' THEN --ADDI, EORI, CMPI
|
|
|
next_micro_state <= andi;
|
next_micro_state <= andi;
|
set_direct_data <= '1';
|
set_direct_data <= '1';
|
IF datatype="10" THEN
|
IF datatype="10" THEN
|
longreaddirect <= '1';
|
longreaddirect <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
IF opcode(11 downto 8)/="1100" THEN --CMPI
|
IF opcode(11 downto 8)/="1100" THEN --CMPI
|
IF endOPC='1' THEN
|
IF endOPC='1' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF opcode(11 downto 8)="1100" OR opcode(11 downto 8)="0100" THEN --CMPI, SUBI
|
IF opcode(11 downto 8)="1100" OR opcode(11 downto 8)="0100" THEN --CMPI, SUBI
|
setaddsub <= '0';
|
setaddsub <= '0';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
-- 0001, 0010, 0011 -----------------------------------------------------------------
|
-- 0001, 0010, 0011 -----------------------------------------------------------------
|
WHEN "0001"|"0010"|"0011" => --move.b, move.l, move.w
|
WHEN "0001"|"0010"|"0011" => --move.b, move.l, move.w
|
set_exec_MOVE <= '1';
|
set_exec_MOVE <= '1';
|
IF opcode(8 downto 6)="001" THEN
|
IF opcode(8 downto 6)="001" THEN
|
no_Flags <= '1';
|
no_Flags <= '1';
|
END IF;
|
END IF;
|
IF opcode(5 downto 4)="00" THEN --Dn, An
|
IF opcode(5 downto 4)="00" THEN --Dn, An
|
regdirectsource <= '1';
|
regdirectsource <= '1';
|
END IF;
|
END IF;
|
CASE opcode(13 downto 12) IS
|
CASE opcode(13 downto 12) IS
|
WHEN "01" => datatype <= "00"; --Byte
|
WHEN "01" => datatype <= "00"; --Byte
|
WHEN "10" => datatype <= "10"; --Long
|
WHEN "10" => datatype <= "10"; --Long
|
WHEN OTHERS => datatype <= "01"; --Word
|
WHEN OTHERS => datatype <= "01"; --Word
|
END CASE;
|
END CASE;
|
source_lowbits <= '1'; -- Dn=> An=>
|
source_lowbits <= '1'; -- Dn=> An=>
|
IF opcode(3)='1' THEN
|
IF opcode(3)='1' THEN
|
source_areg <= '1';
|
source_areg <= '1';
|
END IF;
|
END IF;
|
IF getbrief='1' AND nextpass='1' THEN -- =>(d16,An) =>(d8,An,Xn)
|
IF getbrief='1' AND nextpass='1' THEN -- =>(d16,An) =>(d8,An,Xn)
|
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
END IF;
|
END IF;
|
|
|
IF execOPC='1' AND opcode(8 downto 7)="00" THEN
|
IF execOPC='1' AND opcode(8 downto 7)="00" THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
|
|
IF nextpass='1' OR execOPC='1' OR opcode(5 downto 4)="00" THEN
|
IF nextpass='1' OR execOPC='1' OR opcode(5 downto 4)="00" THEN
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
IF opcode(8 downto 6)/="000" THEN
|
IF opcode(8 downto 6)/="000" THEN
|
dest_areg <= '1';
|
dest_areg <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
|
|
IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
|
IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
|
CASE opcode(8 downto 6) IS --destination
|
CASE opcode(8 downto 6) IS --destination
|
-- WHEN "000" => --Dn
|
-- WHEN "000" => --Dn
|
-- WHEN "001" => --An
|
-- WHEN "001" => --An
|
WHEN "010"|"011"|"100" => --destination -(an)+
|
WHEN "010"|"011"|"100" => --destination -(an)+
|
IF opcode(7)='1' THEN
|
IF opcode(7)='1' THEN
|
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
ELSE
|
ELSE
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
END IF;
|
END IF;
|
IF opcode(6)='1' THEN --(An)+
|
IF opcode(6)='1' THEN --(An)+
|
postadd <= '1';
|
postadd <= '1';
|
IF opcode(11 downto 9)="111" THEN
|
IF opcode(11 downto 9)="111" THEN
|
use_SP <= '1';
|
use_SP <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF opcode(8)='1' THEN -- -(An)
|
IF opcode(8)='1' THEN -- -(An)
|
presub <= '1';
|
presub <= '1';
|
IF opcode(11 downto 9)="111" THEN
|
IF opcode(11 downto 9)="111" THEN
|
use_SP <= '1';
|
use_SP <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF opcode(7 downto 6)/="10" THEN
|
IF opcode(7 downto 6)/="10" THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
setstate <= "11";
|
setstate <= "11";
|
next_micro_state <= nop;
|
next_micro_state <= nop;
|
WHEN "101" => --(d16,An)
|
WHEN "101" => --(d16,An)
|
next_micro_state <= st_dAn1;
|
next_micro_state <= st_dAn1;
|
set_mem_regA <= '1';
|
set_mem_regA <= '1';
|
setgetbrief <= '1';
|
setgetbrief <= '1';
|
WHEN "110" => --(d8,An,Xn)
|
WHEN "110" => --(d8,An,Xn)
|
next_micro_state <= st_AnXn1;
|
next_micro_state <= st_AnXn1;
|
set_mem_regA <= '1';
|
set_mem_regA <= '1';
|
setgetbrief <= '1';
|
setgetbrief <= '1';
|
WHEN "111" =>
|
WHEN "111" =>
|
CASE opcode(11 downto 9) IS
|
CASE opcode(11 downto 9) IS
|
WHEN "000" => --(xxxx).w
|
WHEN "000" => --(xxxx).w
|
next_micro_state <= st_nn;
|
next_micro_state <= st_nn;
|
WHEN "001" => --(xxxx).l
|
WHEN "001" => --(xxxx).l
|
longreaddirect <= '1';
|
longreaddirect <= '1';
|
next_micro_state <= st_nn;
|
next_micro_state <= st_nn;
|
WHEN OTHERS =>
|
WHEN OTHERS =>
|
END CASE;
|
END CASE;
|
WHEN OTHERS =>
|
WHEN OTHERS =>
|
END CASE;
|
END CASE;
|
END IF;
|
END IF;
|
-- 0100 ----------------------------------------------------------------------------
|
-- 0100 ----------------------------------------------------------------------------
|
WHEN "0100" => --rts_group
|
WHEN "0100" => --rts_group
|
IF opcode(8)='1' THEN --lea
|
IF opcode(8)='1' THEN --lea
|
IF opcode(6)='1' THEN --lea
|
IF opcode(6)='1' THEN --lea
|
IF opcode(7)='1' THEN
|
IF opcode(7)='1' THEN
|
ea_only <= '1';
|
ea_only <= '1';
|
IF opcode(5 downto 3)="010" THEN --lea (Am),An
|
IF opcode(5 downto 3)="010" THEN --lea (Am),An
|
set_exec_move <='1';
|
set_exec_move <='1';
|
no_Flags <='1';
|
no_Flags <='1';
|
dest_areg <= '1';
|
dest_areg <= '1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
source_areg <= '1';
|
source_areg <= '1';
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF get_ea_now='1' THEN
|
IF get_ea_now='1' THEN
|
dest_areg <= '1';
|
dest_areg <= '1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
ELSE --chk
|
ELSE --chk
|
IF opcode(7)='1' THEN
|
IF opcode(7)='1' THEN
|
set_exec_ADD <= '1';
|
set_exec_ADD <= '1';
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
datatype <= "01"; --Word
|
datatype <= "01"; --Word
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
setaddsub <= '0';
|
setaddsub <= '0';
|
--first alternative
|
--first alternative
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
IF c_out(1)='1' OR OP1out(15)='1' OR OP2out(15)='1' THEN
|
IF c_out(1)='1' OR OP1out(15)='1' OR OP2out(15)='1' THEN
|
-- trap_chk <= '1'; --first I must change the Trap System
|
-- trap_chk <= '1'; --first I must change the Trap System
|
-- trapmake <= '1';
|
-- trapmake <= '1';
|
END IF;
|
END IF;
|
--second alternative
|
--second alternative
|
-- IF (c_out(1)='0' AND flag_z(1)='0') OR OP1out(15)='1' OR OP2out(15)='1' THEN
|
-- IF (c_out(1)='0' AND flag_z(1)='0') OR OP1out(15)='1' OR OP2out(15)='1' THEN
|
-- -- trap_chk <= '1'; --first I must change the Trap System
|
-- -- trap_chk <= '1'; --first I must change the Trap System
|
-- -- trapmake <= '1';
|
-- -- trapmake <= '1';
|
-- END IF;
|
-- END IF;
|
-- dest_hbits <= '1';
|
-- dest_hbits <= '1';
|
-- source_lowbits <='1';
|
-- source_lowbits <='1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
trap_illegal <= '1'; -- chk long for 68020
|
trap_illegal <= '1'; -- chk long for 68020
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
CASE opcode(11 downto 9) IS
|
CASE opcode(11 downto 9) IS
|
WHEN "000"=>
|
WHEN "000"=>
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
IF opcode(7 downto 6)="11" THEN --move from SR
|
IF opcode(7 downto 6)="11" THEN --move from SR
|
set_exec_MOVESR <= '1';
|
set_exec_MOVESR <= '1';
|
datatype <= "01";
|
datatype <= "01";
|
write_back <='1'; -- im 68000 wird auch erst gelesen
|
write_back <='1'; -- im 68000 wird auch erst gelesen
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
IF endOPC='1' THEN
|
IF endOPC='1' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
ELSE --negx
|
ELSE --negx
|
use_XFlag <= '1';
|
use_XFlag <= '1';
|
write_back <='1';
|
write_back <='1';
|
set_exec_ADD <= '1';
|
set_exec_ADD <= '1';
|
setaddsub <='0';
|
setaddsub <='0';
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
OP1out_zero <= '1';
|
OP1out_zero <= '1';
|
IF endOPC='1' THEN
|
IF endOPC='1' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
WHEN "001"=>
|
WHEN "001"=>
|
IF opcode(7 downto 6)="11" THEN --move from CCR 68010
|
IF opcode(7 downto 6)="11" THEN --move from CCR 68010
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
ELSE --clr
|
ELSE --clr
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
write_back <='1';
|
write_back <='1';
|
set_exec_AND <= '1';
|
set_exec_AND <= '1';
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
OP1out_zero <= '1';
|
OP1out_zero <= '1';
|
IF endOPC='1' THEN
|
IF endOPC='1' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
WHEN "010"=>
|
WHEN "010"=>
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
IF opcode(7 downto 6)="11" THEN --move to CCR
|
IF opcode(7 downto 6)="11" THEN --move to CCR
|
set_exec_MOVE <= '1';
|
set_exec_MOVE <= '1';
|
datatype <= "01";
|
datatype <= "01";
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
to_SR <= '1';
|
to_SR <= '1';
|
END IF;
|
END IF;
|
ELSE --neg
|
ELSE --neg
|
write_back <='1';
|
write_back <='1';
|
set_exec_ADD <= '1';
|
set_exec_ADD <= '1';
|
setaddsub <='0';
|
setaddsub <='0';
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
OP1out_zero <= '1';
|
OP1out_zero <= '1';
|
IF endOPC='1' THEN
|
IF endOPC='1' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
WHEN "011"=> --not, move toSR
|
WHEN "011"=> --not, move toSR
|
IF opcode(7 downto 6)="11" THEN --move to SR
|
IF opcode(7 downto 6)="11" THEN --move to SR
|
IF SVmode='1' THEN
|
IF SVmode='1' THEN
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
set_exec_MOVE <= '1';
|
set_exec_MOVE <= '1';
|
datatype <= "01";
|
datatype <= "01";
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
to_SR <= '1';
|
to_SR <= '1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
ELSE --not
|
ELSE --not
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
write_back <='1';
|
write_back <='1';
|
set_exec_EOR <= '1';
|
set_exec_EOR <= '1';
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
OP2out_one <= '1';
|
OP2out_one <= '1';
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
IF endOPC='1' THEN
|
IF endOPC='1' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
WHEN "100"|"110"=>
|
WHEN "100"|"110"=>
|
IF opcode(7)='1' THEN --movem, ext
|
IF opcode(7)='1' THEN --movem, ext
|
IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
|
IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
set_exec_EXT <= '1';
|
set_exec_EXT <= '1';
|
set_exec_move <= '1';
|
set_exec_move <= '1';
|
END IF;
|
END IF;
|
IF opcode(6)='0' THEN
|
IF opcode(6)='0' THEN
|
datatype <= "01"; --WORD
|
datatype <= "01"; --WORD
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
ELSE --movem
|
ELSE --movem
|
-- IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN --MOVEM
|
-- IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN --MOVEM
|
ea_only <= '1';
|
ea_only <= '1';
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
datatype <= "01"; --Word
|
datatype <= "01"; --Word
|
set_get_movem_mask <='1';
|
set_get_movem_mask <='1';
|
set_get_extendedOPC <='1';
|
set_get_extendedOPC <='1';
|
|
|
IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
|
IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
|
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
setstate <= "01";
|
setstate <= "01";
|
IF opcode(10)='0' THEN
|
IF opcode(10)='0' THEN
|
set_movem_busy <='1';
|
set_movem_busy <='1';
|
ELSE
|
ELSE
|
next_micro_state <= movem;
|
next_micro_state <= movem;
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
|
|
ELSE
|
ELSE
|
IF opcode(6)='0' THEN
|
IF opcode(6)='0' THEN
|
datatype <= "01"; --Word
|
datatype <= "01"; --Word
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
IF opcode(5 downto 3)="100" OR opcode(5 downto 3)="011" THEN
|
IF opcode(5 downto 3)="100" OR opcode(5 downto 3)="011" THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
save_memaddr <= '1';
|
save_memaddr <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF get_ea_now='1' THEN
|
IF get_ea_now='1' THEN
|
set_movem_busy <= '1';
|
set_movem_busy <= '1';
|
IF opcode(10)='0' THEN
|
IF opcode(10)='0' THEN
|
setstate <="01";
|
setstate <="01";
|
ELSE
|
ELSE
|
setstate <="10";
|
setstate <="10";
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF opcode(5 downto 3)="100" THEN
|
IF opcode(5 downto 3)="100" THEN
|
movem_presub <= '1';
|
movem_presub <= '1';
|
END IF;
|
END IF;
|
IF movem_addr='1' THEN
|
IF movem_addr='1' THEN
|
IF opcode(10)='1' THEN
|
IF opcode(10)='1' THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF movem_busy='1' THEN
|
IF movem_busy='1' THEN
|
IF opcode(10)='0' THEN
|
IF opcode(10)='0' THEN
|
setstate <="11";
|
setstate <="11";
|
ELSE
|
ELSE
|
setstate <="10";
|
setstate <="10";
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
IF opcode(10)='1' THEN --MUL, DIV 68020
|
IF opcode(10)='1' THEN --MUL, DIV 68020
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
ELSE --pea, swap
|
ELSE --pea, swap
|
IF opcode(6)='1' THEN
|
IF opcode(6)='1' THEN
|
datatype <= "10";
|
datatype <= "10";
|
IF opcode(5 downto 3)="000" THEN --swap
|
IF opcode(5 downto 3)="000" THEN --swap
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
exec_swap <= '1';
|
exec_swap <= '1';
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
ELSIF opcode(5 downto 3)="001" THEN --bkpt
|
ELSIF opcode(5 downto 3)="001" THEN --bkpt
|
|
|
ELSE --pea
|
ELSE --pea
|
ea_only <= '1';
|
ea_only <= '1';
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
IF nextpass='1' AND micro_state=idle THEN
|
IF nextpass='1' AND micro_state=idle THEN
|
presub <= '1';
|
presub <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
setstate <="11";
|
setstate <="11";
|
next_micro_state <= nop;
|
next_micro_state <= nop;
|
END IF;
|
END IF;
|
IF get_ea_now='1' THEN
|
IF get_ea_now='1' THEN
|
setstate <="01";
|
setstate <="01";
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
ELSE --nbcd
|
ELSE --nbcd
|
IF decodeOPC='1' THEN --nbcd
|
IF decodeOPC='1' THEN --nbcd
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
use_XFlag <= '1';
|
use_XFlag <= '1';
|
write_back <='1';
|
write_back <='1';
|
set_exec_ADD <= '1';
|
set_exec_ADD <= '1';
|
set_exec_SBCD <= '1';
|
set_exec_SBCD <= '1';
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
OP1out_zero <= '1';
|
OP1out_zero <= '1';
|
IF endOPC='1' THEN
|
IF endOPC='1' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
WHEN "101"=> --tst, tas
|
WHEN "101"=> --tst, tas
|
|
IF opcode(7 downto 2)="111111" THEN --4AFC illegal
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
ELSE
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
dest_hbits <= '1'; --for Flags
|
dest_hbits <= '1'; --for Flags
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
-- IF opcode(3)='1' THEN --MC68020...
|
-- IF opcode(3)='1' THEN --MC68020...
|
-- source_areg <= '1';
|
-- source_areg <= '1';
|
-- END IF;
|
-- END IF;
|
END IF;
|
END IF;
|
set_exec_MOVE <= '1';
|
set_exec_MOVE <= '1';
|
IF opcode(7 downto 6)="11" THEN --tas
|
IF opcode(7 downto 6)="11" THEN --tas
|
set_exec_tas <= '1';
|
set_exec_tas <= '1';
|
write_back <= '1';
|
write_back <= '1';
|
datatype <= "00"; --Byte
|
datatype <= "00"; --Byte
|
IF execOPC='1' AND endOPC='1' THEN
|
IF execOPC='1' AND endOPC='1' THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
END IF;
|
-- WHEN "110"=>
|
-- WHEN "110"=>
|
WHEN "111"=> --4EXX
|
WHEN "111"=> --4EXX
|
IF opcode(7)='1' THEN --jsr, jmp
|
IF opcode(7)='1' THEN --jsr, jmp
|
datatype <= "10";
|
datatype <= "10";
|
ea_only <= '1';
|
ea_only <= '1';
|
IF nextpass='1' AND micro_state=idle THEN
|
IF nextpass='1' AND micro_state=idle THEN
|
presub <= '1';
|
presub <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
setstate <="11";
|
setstate <="11";
|
next_micro_state <= nop;
|
next_micro_state <= nop;
|
END IF;
|
END IF;
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
IF get_ea_now='1' THEN --jsr
|
IF get_ea_now='1' THEN --jsr
|
IF opcode(6)='0' THEN
|
IF opcode(6)='0' THEN
|
setstate <="01";
|
setstate <="01";
|
END IF;
|
END IF;
|
ea_to_pc <= '1';
|
ea_to_pc <= '1';
|
IF opcode(5 downto 1)="11100" THEN
|
IF opcode(5 downto 1)="11100" THEN
|
writePC_add <= '1';
|
writePC_add <= '1';
|
ELSE
|
ELSE
|
writePC <= '1';
|
writePC <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
ELSE --
|
ELSE --
|
CASE opcode(6 downto 0) IS
|
CASE opcode(6 downto 0) IS
|
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
|
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
|
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
|
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
|
trap_trap <='1';
|
trap_trap <='1';
|
trapmake <= '1';
|
trapmake <= '1';
|
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link
|
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link
|
datatype <= "10";
|
datatype <= "10";
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
next_micro_state <= link;
|
next_micro_state <= link;
|
set_exec_MOVE <= '1'; --für displacement
|
set_exec_MOVE <= '1'; --für displacement
|
presub <= '1';
|
presub <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
source_areg <= '1';
|
source_areg <= '1';
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
setstackaddr <='1';
|
setstackaddr <='1';
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
|
|
WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" => --unlink
|
WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" => --unlink
|
datatype <= "10";
|
datatype <= "10";
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
setstate <= "10";
|
setstate <= "10";
|
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
ELSIF execOPC='1' THEN
|
ELSIF execOPC='1' THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
exec_exg <= '1';
|
exec_exg <= '1';
|
ELSE
|
ELSE
|
setstackaddr <='1';
|
setstackaddr <='1';
|
regwrena <= '1';
|
regwrena <= '1';
|
get_ea_now <= '1';
|
get_ea_now <= '1';
|
ea_only <= '1';
|
ea_only <= '1';
|
END IF;
|
END IF;
|
|
|
WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" => --move An,USP
|
WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" => --move An,USP
|
IF SVmode='1' THEN
|
IF SVmode='1' THEN
|
no_Flags <= '1';
|
no_Flags <= '1';
|
to_USP <= '1';
|
to_USP <= '1';
|
setstackaddr <= '1';
|
setstackaddr <= '1';
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
source_areg <= '1';
|
source_areg <= '1';
|
set_exec_MOVE <= '1';
|
set_exec_MOVE <= '1';
|
datatype <= "10";
|
datatype <= "10";
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
|
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
|
IF SVmode='1' THEN
|
IF SVmode='1' THEN
|
no_Flags <= '1';
|
no_Flags <= '1';
|
from_USP <= '1';
|
from_USP <= '1';
|
set_exec_MOVE <= '1';
|
set_exec_MOVE <= '1';
|
datatype <= "10";
|
datatype <= "10";
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
|
|
WHEN "1110000" => --reset
|
WHEN "1110000" => --reset
|
IF SVmode='0' THEN
|
IF SVmode='0' THEN
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
|
|
WHEN "1110001" => --nop
|
WHEN "1110001" => --nop
|
|
|
WHEN "1110010" => --stop
|
WHEN "1110010" => --stop
|
IF SVmode='0' THEN
|
IF SVmode='0' THEN
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
ELSE
|
ELSE
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
setnextpass <= '1';
|
setnextpass <= '1';
|
set_directSR <= '1';
|
set_directSR <= '1';
|
set_stop <= '1';
|
set_stop <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
WHEN "1110011" => --rte
|
WHEN "1110011" => --rte
|
IF SVmode='1' THEN
|
IF SVmode='1' THEN
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
datatype <= "01";
|
datatype <= "01";
|
setstate <= "10";
|
setstate <= "10";
|
postadd <= '1';
|
postadd <= '1';
|
setstackaddr <= '1';
|
setstackaddr <= '1';
|
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
set_directSR <= '1';
|
set_directSR <= '1';
|
next_micro_state <= rte;
|
next_micro_state <= rte;
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
|
|
WHEN "1110101" => --rts
|
WHEN "1110101" => --rts
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
datatype <= "10";
|
datatype <= "10";
|
setstate <= "10";
|
setstate <= "10";
|
postadd <= '1';
|
postadd <= '1';
|
setstackaddr <= '1';
|
setstackaddr <= '1';
|
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
set_directPC <= '1';
|
set_directPC <= '1';
|
next_micro_state <= nop;
|
next_micro_state <= nop;
|
END IF;
|
END IF;
|
|
|
WHEN "1110110" => --trapv
|
WHEN "1110110" => --trapv
|
IF Flags(1)='1' THEN
|
IF Flags(1)='1' THEN
|
trap_trapv <= '1';
|
trap_trapv <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
|
|
WHEN "1110111" => --rtr
|
WHEN "1110111" => --rtr
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
datatype <= "01";
|
datatype <= "01";
|
setstate <= "10";
|
setstate <= "10";
|
postadd <= '1';
|
postadd <= '1';
|
setstackaddr <= '1';
|
setstackaddr <= '1';
|
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
set_directCCR <= '1';
|
set_directCCR <= '1';
|
next_micro_state <= rte;
|
next_micro_state <= rte;
|
END IF;
|
END IF;
|
|
|
|
|
WHEN OTHERS =>
|
WHEN OTHERS =>
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END CASE;
|
END CASE;
|
END IF;
|
END IF;
|
WHEN OTHERS => null;
|
WHEN OTHERS => null;
|
END CASE;
|
END CASE;
|
END IF;
|
END IF;
|
|
|
-- 0101 ----------------------------------------------------------------------------
|
-- 0101 ----------------------------------------------------------------------------
|
WHEN "0101" => --subq, addq
|
WHEN "0101" => --subq, addq
|
|
|
IF opcode(7 downto 6)="11" THEN --dbcc
|
IF opcode(7 downto 6)="11" THEN --dbcc
|
IF opcode(5 downto 3)="001" THEN --dbcc
|
IF opcode(5 downto 3)="001" THEN --dbcc
|
datatype <= "01"; --Word
|
datatype <= "01"; --Word
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
next_micro_state <= nop;
|
next_micro_state <= nop;
|
OP2out_one <= '1';
|
OP2out_one <= '1';
|
IF condition='0' THEN
|
IF condition='0' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
IF c_in(2)='1' THEN
|
IF c_in(2)='1' THEN
|
next_micro_state <= dbcc1;
|
next_micro_state <= dbcc1;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
data_is_source <= '1';
|
data_is_source <= '1';
|
END IF;
|
END IF;
|
ELSE --Scc
|
ELSE --Scc
|
datatype <= "00"; --Byte
|
datatype <= "00"; --Byte
|
write_back <= '1';
|
write_back <= '1';
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
IF condition='0' THEN
|
IF condition='0' THEN
|
set_exec_Scc <= '1';
|
set_exec_Scc <= '1';
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
IF condition='1' THEN
|
IF condition='1' THEN
|
OP2out_one <= '1';
|
OP2out_one <= '1';
|
exec_EXG <= '1';
|
exec_EXG <= '1';
|
ELSE
|
ELSE
|
OP1out_zero <= '1';
|
OP1out_zero <= '1';
|
END IF;
|
END IF;
|
IF endOPC='1' THEN
|
IF endOPC='1' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
ELSE --addq, subq
|
ELSE --addq, subq
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
IF opcode(5 downto 3)="001" THEN
|
IF opcode(5 downto 3)="001" THEN
|
no_Flags <= '1';
|
no_Flags <= '1';
|
END IF;
|
END IF;
|
write_back <= '1';
|
write_back <= '1';
|
set_exec_ADDQ <= '1';
|
set_exec_ADDQ <= '1';
|
set_exec_ADD <= '1';
|
set_exec_ADD <= '1';
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
IF endOPC='1' THEN
|
IF endOPC='1' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
IF opcode(8)='1' THEN
|
IF opcode(8)='1' THEN
|
setaddsub <= '0';
|
setaddsub <= '0';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
-- 0110 ----------------------------------------------------------------------------
|
-- 0110 ----------------------------------------------------------------------------
|
WHEN "0110" => --bra,bsr,bcc
|
WHEN "0110" => --bra,bsr,bcc
|
datatype <= "10";
|
datatype <= "10";
|
|
|
IF micro_state=idle THEN
|
IF micro_state=idle THEN
|
IF opcode(11 downto 8)="0001" THEN --bsr
|
IF opcode(11 downto 8)="0001" THEN --bsr
|
IF opcode(7 downto 0)="00000000" THEN
|
IF opcode(7 downto 0)="00000000" THEN
|
next_micro_state <= bsr1;
|
next_micro_state <= bsr1;
|
ELSE
|
ELSE
|
next_micro_state <= bsr2;
|
next_micro_state <= bsr2;
|
setstate <= "01";
|
setstate <= "01";
|
END IF;
|
END IF;
|
presub <= '1';
|
presub <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
ELSE --bra
|
ELSE --bra
|
IF opcode(7 downto 0)="00000000" THEN
|
IF opcode(7 downto 0)="00000000" THEN
|
next_micro_state <= bra1;
|
next_micro_state <= bra1;
|
END IF;
|
END IF;
|
IF condition='1' THEN
|
IF condition='1' THEN
|
TG68_PC_br8 <= '1';
|
TG68_PC_br8 <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
-- 0111 ----------------------------------------------------------------------------
|
-- 0111 ----------------------------------------------------------------------------
|
WHEN "0111" => --moveq
|
WHEN "0111" => --moveq
|
IF opcode(8)='0' THEN
|
IF opcode(8)='0' THEN
|
IF trap_interrupt='0' THEN
|
IF trap_interrupt='0' THEN
|
datatype <= "10"; --Long
|
datatype <= "10"; --Long
|
Regwrena <= '1';
|
Regwrena <= '1';
|
set_exec_MOVEQ <= '1';
|
set_exec_MOVEQ <= '1';
|
set_exec_MOVE <= '1';
|
set_exec_MOVE <= '1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
|
|
-- 1000 ----------------------------------------------------------------------------
|
-- 1000 ----------------------------------------------------------------------------
|
WHEN "1000" => --or
|
WHEN "1000" => --or
|
IF opcode(7 downto 6)="11" THEN --divu, divs
|
IF opcode(7 downto 6)="11" THEN --divu, divs
|
IF opcode(5 downto 4)="00" THEN --Dn, An
|
IF opcode(5 downto 4)="00" THEN --Dn, An
|
regdirectsource <= '1';
|
regdirectsource <= '1';
|
END IF;
|
END IF;
|
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
|
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= div1;
|
next_micro_state <= div1;
|
END IF;
|
END IF;
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
IF execOPC='1' AND z_error='0' AND set_V_Flag='0' THEN
|
IF execOPC='1' AND z_error='0' AND set_V_Flag='0' THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
|
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
source_lowbits <='1';
|
source_lowbits <='1';
|
ELSE
|
ELSE
|
datatype <= "01";
|
datatype <= "01";
|
END IF;
|
END IF;
|
|
|
|
|
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --sbcd, pack , unpack
|
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --sbcd, pack , unpack
|
IF opcode(7 downto 6)="00" THEN --sbcd
|
IF opcode(7 downto 6)="00" THEN --sbcd
|
use_XZFlag <= '1';
|
use_XZFlag <= '1';
|
set_exec_ADD <= '1';
|
set_exec_ADD <= '1';
|
set_exec_SBCD <= '1';
|
set_exec_SBCD <= '1';
|
IF opcode(3)='1' THEN
|
IF opcode(3)='1' THEN
|
write_back <= '1';
|
write_back <= '1';
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
set_direct_data <= '1';
|
set_direct_data <= '1';
|
setstate <= "10";
|
setstate <= "10";
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
presub <= '1';
|
presub <= '1';
|
next_micro_state <= op_AxAy;
|
next_micro_state <= op_AxAy;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
source_lowbits <='1';
|
source_lowbits <='1';
|
IF endOPC='1' THEN
|
IF endOPC='1' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
ELSE --pack, unpack
|
ELSE --pack, unpack
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
ELSE --or
|
ELSE --or
|
set_exec_OR <= '1';
|
set_exec_OR <= '1';
|
IF opcode(8)='1' THEN
|
IF opcode(8)='1' THEN
|
write_back <= '1';
|
write_back <= '1';
|
END IF;
|
END IF;
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
IF endOPC='1' THEN
|
IF endOPC='1' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
IF opcode(8)='1' THEN
|
IF opcode(8)='1' THEN
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
ELSE
|
ELSE
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
source_lowbits <='1';
|
source_lowbits <='1';
|
IF opcode(3)='1' THEN
|
IF opcode(3)='1' THEN
|
source_areg <= '1';
|
source_areg <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
-- 1001, 1101 -----------------------------------------------------------------------
|
-- 1001, 1101 -----------------------------------------------------------------------
|
WHEN "1001"|"1101" => --sub, add
|
WHEN "1001"|"1101" => --sub, add
|
set_exec_ADD <= '1';
|
set_exec_ADD <= '1';
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
IF opcode(8 downto 6)="011" THEN --adda.w, suba.w
|
IF opcode(8 downto 6)="011" THEN --adda.w, suba.w
|
datatype <= "01"; --Word
|
datatype <= "01"; --Word
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
IF endOPC='1' THEN
|
IF endOPC='1' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
IF opcode(14)='0' THEN
|
IF opcode(14)='0' THEN
|
setaddsub <= '0';
|
setaddsub <= '0';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF opcode(8)='1' AND opcode(5 downto 4)="00" AND opcode(7 downto 6)/="11" THEN --addx, subx
|
IF opcode(8)='1' AND opcode(5 downto 4)="00" AND opcode(7 downto 6)/="11" THEN --addx, subx
|
use_XZFlag <= '1';
|
use_XZFlag <= '1';
|
IF opcode(3)='1' THEN
|
IF opcode(3)='1' THEN
|
write_back <= '1';
|
write_back <= '1';
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
set_direct_data <= '1';
|
set_direct_data <= '1';
|
setstate <= "10";
|
setstate <= "10";
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
presub <= '1';
|
presub <= '1';
|
next_micro_state <= op_AxAy;
|
next_micro_state <= op_AxAy;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
source_lowbits <='1';
|
source_lowbits <='1';
|
END IF;
|
END IF;
|
ELSE --sub, add
|
ELSE --sub, add
|
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN
|
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN
|
write_back <= '1';
|
write_back <= '1';
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
IF opcode(7 downto 6)="11" THEN --adda, suba
|
IF opcode(7 downto 6)="11" THEN --adda, suba
|
no_Flags <= '1';
|
no_Flags <= '1';
|
dest_areg <='1';
|
dest_areg <='1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
source_lowbits <='1';
|
source_lowbits <='1';
|
IF opcode(3)='1' THEN
|
IF opcode(3)='1' THEN
|
source_areg <= '1';
|
source_areg <= '1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
IF opcode(8)='1' THEN
|
IF opcode(8)='1' THEN
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
ELSE
|
ELSE
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
source_lowbits <='1';
|
source_lowbits <='1';
|
IF opcode(3)='1' THEN
|
IF opcode(3)='1' THEN
|
source_areg <= '1';
|
source_areg <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
-- 1010 ----------------------------------------------------------------------------
|
-- 1010 ----------------------------------------------------------------------------
|
WHEN "1010" => --Trap 1010
|
WHEN "1010" => --Trap 1010
|
trap_1010 <= '1';
|
trap_1010 <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
-- 1011 ----------------------------------------------------------------------------
|
-- 1011 ----------------------------------------------------------------------------
|
WHEN "1011" => --eor, cmp
|
WHEN "1011" => --eor, cmp
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
IF opcode(8 downto 6)="011" THEN --cmpa.w
|
IF opcode(8 downto 6)="011" THEN --cmpa.w
|
datatype <= "01"; --Word
|
datatype <= "01"; --Word
|
set_exec_CPMAW <= '1';
|
set_exec_CPMAW <= '1';
|
END IF;
|
END IF;
|
IF opcode(8)='1' AND opcode(5 downto 3)="001" AND opcode(7 downto 6)/="11" THEN --cmpm
|
IF opcode(8)='1' AND opcode(5 downto 3)="001" AND opcode(7 downto 6)/="11" THEN --cmpm
|
set_exec_CMP <= '1';
|
set_exec_CMP <= '1';
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
set_direct_data <= '1';
|
set_direct_data <= '1';
|
setstate <= "10";
|
setstate <= "10";
|
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
postadd <= '1';
|
postadd <= '1';
|
next_micro_state <= cmpm;
|
next_micro_state <= cmpm;
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
setaddsub <= '0';
|
setaddsub <= '0';
|
END IF;
|
END IF;
|
ELSE --sub, add
|
ELSE --sub, add
|
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
|
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
|
set_exec_EOR <= '1';
|
set_exec_EOR <= '1';
|
write_back <= '1';
|
write_back <= '1';
|
ELSE --cmp
|
ELSE --cmp
|
set_exec_CMP <= '1';
|
set_exec_CMP <= '1';
|
END IF;
|
END IF;
|
|
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
|
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
IF endOPC='1' THEN
|
IF endOPC='1' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
ELSE --cmp
|
ELSE --cmp
|
source_lowbits <='1';
|
source_lowbits <='1';
|
IF opcode(3)='1' THEN
|
IF opcode(3)='1' THEN
|
source_areg <= '1';
|
source_areg <= '1';
|
END IF;
|
END IF;
|
IF opcode(7 downto 6)="11" THEN --cmpa
|
IF opcode(7 downto 6)="11" THEN --cmpa
|
dest_areg <='1';
|
dest_areg <='1';
|
END IF;
|
END IF;
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
setaddsub <= '0';
|
setaddsub <= '0';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
-- 1100 ----------------------------------------------------------------------------
|
-- 1100 ----------------------------------------------------------------------------
|
WHEN "1100" => --and, exg
|
WHEN "1100" => --and, exg
|
IF opcode(7 downto 6)="11" THEN --mulu, muls
|
IF opcode(7 downto 6)="11" THEN --mulu, muls
|
IF opcode(5 downto 4)="00" THEN --Dn, An
|
IF opcode(5 downto 4)="00" THEN --Dn, An
|
regdirectsource <= '1';
|
regdirectsource <= '1';
|
END IF;
|
END IF;
|
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
|
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= mul1;
|
next_micro_state <= mul1;
|
END IF;
|
END IF;
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
|
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
source_lowbits <='1';
|
source_lowbits <='1';
|
ELSE
|
ELSE
|
datatype <= "01";
|
datatype <= "01";
|
END IF;
|
END IF;
|
|
|
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --exg, abcd
|
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --exg, abcd
|
IF opcode(7 downto 6)="00" THEN --abcd
|
IF opcode(7 downto 6)="00" THEN --abcd
|
use_XZFlag <= '1';
|
use_XZFlag <= '1';
|
-- datatype <= "00"; --ist schon default
|
-- datatype <= "00"; --ist schon default
|
set_exec_ADD <= '1';
|
set_exec_ADD <= '1';
|
set_exec_ABCD <= '1';
|
set_exec_ABCD <= '1';
|
IF opcode(3)='1' THEN
|
IF opcode(3)='1' THEN
|
write_back <= '1';
|
write_back <= '1';
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
set_direct_data <= '1';
|
set_direct_data <= '1';
|
setstate <= "10";
|
setstate <= "10";
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
presub <= '1';
|
presub <= '1';
|
next_micro_state <= op_AxAy;
|
next_micro_state <= op_AxAy;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
source_lowbits <='1';
|
source_lowbits <='1';
|
IF endOPC='1' THEN
|
IF endOPC='1' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
ELSE --exg
|
ELSE --exg
|
datatype <= "10";
|
datatype <= "10";
|
regwrena <= '1';
|
regwrena <= '1';
|
IF opcode(6)='1' AND opcode(3)='1' THEN
|
IF opcode(6)='1' AND opcode(3)='1' THEN
|
dest_areg <= '1';
|
dest_areg <= '1';
|
source_areg <= '1';
|
source_areg <= '1';
|
END IF;
|
END IF;
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
exec_exg <= '1';
|
exec_exg <= '1';
|
ELSE
|
ELSE
|
save_memaddr <= '1';
|
save_memaddr <= '1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
ELSE --and
|
ELSE --and
|
set_exec_AND <= '1';
|
set_exec_AND <= '1';
|
IF opcode(8)='1' THEN
|
IF opcode(8)='1' THEN
|
write_back <= '1';
|
write_back <= '1';
|
END IF;
|
END IF;
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
|
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
IF endOPC='1' THEN
|
IF endOPC='1' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
IF opcode(8)='1' THEN
|
IF opcode(8)='1' THEN
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
ELSE
|
ELSE
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
source_lowbits <='1';
|
source_lowbits <='1';
|
IF opcode(3)='1' THEN
|
IF opcode(3)='1' THEN
|
source_areg <= '1';
|
source_areg <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
-- 1110 ----------------------------------------------------------------------------
|
-- 1110 ----------------------------------------------------------------------------
|
WHEN "1110" => --rotation
|
WHEN "1110" => --rotation
|
set_exec_ROT <= '1';
|
set_exec_ROT <= '1';
|
IF opcode(7 downto 6)="11" THEN
|
IF opcode(7 downto 6)="11" THEN
|
datatype <= "01";
|
datatype <= "01";
|
rot_bits <= opcode(10 downto 9);
|
rot_bits <= opcode(10 downto 9);
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
write_back <= '1';
|
write_back <= '1';
|
ELSE
|
ELSE
|
rot_bits <= opcode(4 downto 3);
|
rot_bits <= opcode(4 downto 3);
|
data_is_source <= '1';
|
data_is_source <= '1';
|
END IF;
|
END IF;
|
|
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
IF opcode(7 downto 6)="11" THEN
|
IF opcode(7 downto 6)="11" THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
ELSE
|
ELSE
|
IF opcode(5)='1' THEN
|
IF opcode(5)='1' THEN
|
IF OP2out(5 downto 0)/="000000" THEN
|
IF OP2out(5 downto 0)/="000000" THEN
|
set_rot_cnt <= OP2out(5 downto 0);
|
set_rot_cnt <= OP2out(5 downto 0);
|
ELSE
|
ELSE
|
set_rot_nop <= '1';
|
set_rot_nop <= '1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
|
set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
|
IF opcode(11 downto 9)="000" THEN
|
IF opcode(11 downto 9)="000" THEN
|
set_rot_cnt(3) <='1';
|
set_rot_cnt(3) <='1';
|
ELSE
|
ELSE
|
set_rot_cnt(3) <='0';
|
set_rot_cnt(3) <='0';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF opcode(7 downto 6)/="11" THEN
|
IF opcode(7 downto 6)/="11" THEN
|
IF execOPC='1' AND rot_nop='0' THEN
|
IF execOPC='1' AND rot_nop='0' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
set_rot_cnt <= rot_cnt-1;
|
set_rot_cnt <= rot_cnt-1;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
-- ----------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------------
|
WHEN OTHERS =>
|
WHEN OTHERS =>
|
trap_1111 <= '1';
|
trap_1111 <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
|
|
END CASE;
|
END CASE;
|
|
|
-- END PROCESS;
|
-- END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- execute microcode
|
-- execute microcode
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
--PROCESS (micro_state)
|
--PROCESS (micro_state)
|
-- BEGIN
|
-- BEGIN
|
IF Z_error='1' THEN -- divu by zero
|
IF Z_error='1' THEN -- divu by zero
|
trapmake <= '1'; --wichtig für USP
|
trapmake <= '1'; --wichtig für USP
|
IF trapd='0' THEN
|
IF trapd='0' THEN
|
writePC <= '1';
|
writePC <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
IF trapmake='1' AND trapd='0' THEN
|
IF trapmake='1' AND trapd='0' THEN
|
next_micro_state <= trap1;
|
next_micro_state <= trap1;
|
presub <= '1';
|
presub <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
setstate <= "11";
|
setstate <= "11";
|
datatype <= "10";
|
datatype <= "10";
|
END IF;
|
END IF;
|
|
|
IF interrupt='1' THEN
|
IF interrupt='1' THEN
|
next_micro_state <= int1;
|
next_micro_state <= int1;
|
setstate <= "10";
|
setstate <= "10";
|
-- datatype <= "01"; --wirkt sich auf Flags aus
|
-- datatype <= "01"; --wirkt sich auf Flags aus
|
END IF;
|
END IF;
|
|
|
IF reset='0' THEN
|
IF reset='0' THEN
|
micro_state <= init1;
|
micro_state <= init1;
|
ELSIF rising_edge(clk) THEN
|
ELSIF rising_edge(clk) THEN
|
IF clkena='1' THEN
|
IF clkena='1' THEN
|
trapd <= trapmake;
|
trapd <= trapmake;
|
IF fetchOPC='1' THEN
|
IF fetchOPC='1' THEN
|
micro_state <= idle;
|
micro_state <= idle;
|
ELSE
|
ELSE
|
micro_state <= next_micro_state;
|
micro_state <= next_micro_state;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
CASE micro_state IS
|
CASE micro_state IS
|
WHEN ld_nn => -- (nnnn).w/l=>
|
WHEN ld_nn => -- (nnnn).w/l=>
|
get_ea_now <='1';
|
get_ea_now <='1';
|
setnextpass <= '1';
|
setnextpass <= '1';
|
setaddrlong <= '1';
|
setaddrlong <= '1';
|
|
|
WHEN st_nn => -- =>(nnnn).w/l
|
WHEN st_nn => -- =>(nnnn).w/l
|
setstate <= "11";
|
setstate <= "11";
|
setaddrlong <= '1';
|
setaddrlong <= '1';
|
next_micro_state <= nop;
|
next_micro_state <= nop;
|
|
|
WHEN ld_dAn1 => -- d(An)=>, --d(PC)=>
|
WHEN ld_dAn1 => -- d(An)=>, --d(PC)=>
|
setstate <= "01";
|
setstate <= "01";
|
next_micro_state <= ld_dAn2;
|
next_micro_state <= ld_dAn2;
|
WHEN ld_dAn2 => -- d(An)=>, --d(PC)=>
|
WHEN ld_dAn2 => -- d(An)=>, --d(PC)=>
|
get_ea_now <='1';
|
get_ea_now <='1';
|
setdisp <= '1'; --word
|
setdisp <= '1'; --word
|
setnextpass <= '1';
|
setnextpass <= '1';
|
|
|
WHEN ld_AnXn1 => -- d(An,Xn)=>, --d(PC,Xn)=>
|
WHEN ld_AnXn1 => -- d(An,Xn)=>, --d(PC,Xn)=>
|
setstate <= "01";
|
setstate <= "01";
|
next_micro_state <= ld_AnXn2;
|
next_micro_state <= ld_AnXn2;
|
WHEN ld_AnXn2 => -- d(An,Xn)=>, --d(PC,Xn)=>
|
WHEN ld_AnXn2 => -- d(An,Xn)=>, --d(PC,Xn)=>
|
setdisp <= '1'; --byte
|
setdisp <= '1'; --byte
|
setdispbyte <= '1';
|
setdispbyte <= '1';
|
setstate <= "01";
|
setstate <= "01";
|
setbriefext <= '1';
|
setbriefext <= '1';
|
next_micro_state <= ld_AnXn3;
|
next_micro_state <= ld_AnXn3;
|
WHEN ld_AnXn3 =>
|
WHEN ld_AnXn3 =>
|
get_ea_now <='1';
|
get_ea_now <='1';
|
setdisp <= '1'; --brief
|
setdisp <= '1'; --brief
|
setdispbrief <= '1';
|
setdispbrief <= '1';
|
setnextpass <= '1';
|
setnextpass <= '1';
|
|
|
WHEN st_dAn1 => -- =>d(An)
|
WHEN st_dAn1 => -- =>d(An)
|
setstate <= "01";
|
setstate <= "01";
|
next_micro_state <= st_dAn2;
|
next_micro_state <= st_dAn2;
|
WHEN st_dAn2 => -- =>d(An)
|
WHEN st_dAn2 => -- =>d(An)
|
setstate <= "11";
|
setstate <= "11";
|
setdisp <= '1'; --word
|
setdisp <= '1'; --word
|
next_micro_state <= nop;
|
next_micro_state <= nop;
|
|
|
WHEN st_AnXn1 => -- =>d(An,Xn)
|
WHEN st_AnXn1 => -- =>d(An,Xn)
|
setstate <= "01";
|
setstate <= "01";
|
next_micro_state <= st_AnXn2;
|
next_micro_state <= st_AnXn2;
|
WHEN st_AnXn2 => -- =>d(An,Xn)
|
WHEN st_AnXn2 => -- =>d(An,Xn)
|
setdisp <= '1'; --byte
|
setdisp <= '1'; --byte
|
setdispbyte <= '1';
|
setdispbyte <= '1';
|
setstate <= "01";
|
setstate <= "01";
|
setbriefext <= '1';
|
setbriefext <= '1';
|
next_micro_state <= st_AnXn3;
|
next_micro_state <= st_AnXn3;
|
WHEN st_AnXn3 =>
|
WHEN st_AnXn3 =>
|
setstate <= "11";
|
setstate <= "11";
|
setdisp <= '1'; --brief
|
setdisp <= '1'; --brief
|
setdispbrief <= '1';
|
setdispbrief <= '1';
|
next_micro_state <= nop;
|
next_micro_state <= nop;
|
|
|
WHEN bra1 => --bra
|
WHEN bra1 => --bra
|
IF condition='1' THEN
|
IF condition='1' THEN
|
TG68_PC_br8 <= '1'; --pc+0000
|
TG68_PC_br8 <= '1'; --pc+0000
|
setstate <= "01";
|
setstate <= "01";
|
next_micro_state <= bra2;
|
next_micro_state <= bra2;
|
END IF;
|
END IF;
|
WHEN bra2 => --bra
|
WHEN bra2 => --bra
|
TG68_PC_brw <= '1';
|
TG68_PC_brw <= '1';
|
|
|
WHEN bsr1 => --bsr
|
WHEN bsr1 => --bsr
|
set_TG68_PC_dec <= '1'; --in 2 Takten -2
|
set_TG68_PC_dec <= '1'; --in 2 Takten -2
|
setstate <= "01";
|
setstate <= "01";
|
next_micro_state <= bsr2;
|
next_micro_state <= bsr2;
|
WHEN bsr2 => --bsr
|
WHEN bsr2 => --bsr
|
IF TG68_PC_dec(0)='1' THEN
|
IF TG68_PC_dec(0)='1' THEN
|
TG68_PC_brw <= '1';
|
TG68_PC_brw <= '1';
|
ELSE
|
ELSE
|
TG68_PC_br8 <= '1';
|
TG68_PC_br8 <= '1';
|
END IF;
|
END IF;
|
writePC <= '1';
|
writePC <= '1';
|
setstate <= "11";
|
setstate <= "11";
|
next_micro_state <= nop;
|
next_micro_state <= nop;
|
|
|
WHEN dbcc1 => --dbcc
|
WHEN dbcc1 => --dbcc
|
TG68_PC_nop <= '1';
|
TG68_PC_nop <= '1';
|
setstate <= "01";
|
setstate <= "01";
|
next_micro_state <= dbcc2;
|
next_micro_state <= dbcc2;
|
WHEN dbcc2 => --dbcc
|
WHEN dbcc2 => --dbcc
|
TG68_PC_brw <= '1';
|
TG68_PC_brw <= '1';
|
|
|
WHEN movem => --movem
|
WHEN movem => --movem
|
set_movem_busy <='1';
|
set_movem_busy <='1';
|
setstate <= "10";
|
setstate <= "10";
|
|
|
WHEN andi => --andi
|
WHEN andi => --andi
|
IF opcode(5 downto 4)/="00" THEN
|
IF opcode(5 downto 4)/="00" THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
setnextpass <= '1';
|
setnextpass <= '1';
|
END IF;
|
END IF;
|
|
|
WHEN op_AxAy => -- op -(Ax),-(Ay)
|
WHEN op_AxAy => -- op -(Ax),-(Ay)
|
presub <= '1';
|
presub <= '1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
dest_areg <= '1';
|
dest_areg <= '1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
setstate <= "10";
|
setstate <= "10";
|
|
|
WHEN cmpm => -- cmpm (Ay)+,(Ax)+
|
WHEN cmpm => -- cmpm (Ay)+,(Ax)+
|
postadd <= '1';
|
postadd <= '1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
dest_areg <= '1';
|
dest_areg <= '1';
|
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
setstate <= "10";
|
setstate <= "10";
|
|
|
WHEN link => -- link
|
WHEN link => -- link
|
setstate <="11";
|
setstate <="11";
|
save_memaddr <= '1';
|
save_memaddr <= '1';
|
regwrena <= '1';
|
regwrena <= '1';
|
|
|
WHEN int1 => -- interrupt
|
WHEN int1 => -- interrupt
|
presub <= '1';
|
presub <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
setstate <= "11";
|
setstate <= "11";
|
datatype <= "10";
|
datatype <= "10";
|
next_micro_state <= int2;
|
next_micro_state <= int2;
|
WHEN int2 => -- interrupt
|
WHEN int2 => -- interrupt
|
presub <= '1';
|
presub <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
setstate <= "11";
|
setstate <= "11";
|
datatype <= "01";
|
datatype <= "01";
|
writeSR <= '1';
|
writeSR <= '1';
|
next_micro_state <= int3;
|
next_micro_state <= int3;
|
WHEN int3 => -- interrupt
|
WHEN int3 => -- interrupt
|
set_vectoraddr <= '1';
|
set_vectoraddr <= '1';
|
datatype <= "10";
|
datatype <= "10";
|
set_directPC <= '1';
|
set_directPC <= '1';
|
setstate <= "10";
|
setstate <= "10";
|
next_micro_state <= int4;
|
next_micro_state <= int4;
|
WHEN int4 => -- interrupt
|
WHEN int4 => -- interrupt
|
datatype <= "10";
|
datatype <= "10";
|
|
|
WHEN rte => -- RTE
|
WHEN rte => -- RTE
|
datatype <= "10";
|
datatype <= "10";
|
setstate <= "10";
|
setstate <= "10";
|
postadd <= '1';
|
postadd <= '1';
|
setstackaddr <= '1';
|
setstackaddr <= '1';
|
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
set_directPC <= '1';
|
set_directPC <= '1';
|
next_micro_state <= nop;
|
next_micro_state <= nop;
|
|
|
WHEN trap1 => -- TRAP
|
WHEN trap1 => -- TRAP
|
presub <= '1';
|
presub <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
setstate <= "11";
|
setstate <= "11";
|
datatype <= "01";
|
datatype <= "01";
|
writeSR <= '1';
|
writeSR <= '1';
|
next_micro_state <= trap2;
|
next_micro_state <= trap2;
|
WHEN trap2 => -- TRAP
|
WHEN trap2 => -- TRAP
|
set_vectoraddr <= '1';
|
set_vectoraddr <= '1';
|
datatype <= "10";
|
datatype <= "10";
|
set_directPC <= '1';
|
set_directPC <= '1';
|
-- longreaddirect <= '1';
|
-- longreaddirect <= '1';
|
setstate <= "10";
|
setstate <= "10";
|
next_micro_state <= trap3;
|
next_micro_state <= trap3;
|
WHEN trap3 => -- TRAP
|
WHEN trap3 => -- TRAP
|
datatype <= "10";
|
datatype <= "10";
|
|
|
WHEN movep1 => -- MOVEP d(An)
|
WHEN movep1 => -- MOVEP d(An)
|
setstate <= "01";
|
setstate <= "01";
|
IF opcode(6)='1' THEN
|
IF opcode(6)='1' THEN
|
set_movepl <= '1';
|
set_movepl <= '1';
|
END IF;
|
END IF;
|
next_micro_state <= movep2;
|
next_micro_state <= movep2;
|
WHEN movep2 =>
|
WHEN movep2 =>
|
setdisp <= '1';
|
setdisp <= '1';
|
IF opcode(7)='0' THEN
|
IF opcode(7)='0' THEN
|
setstate <= "10";
|
setstate <= "10";
|
ELSE
|
ELSE
|
setstate <= "11";
|
setstate <= "11";
|
wait_mem_byte <= '1';
|
wait_mem_byte <= '1';
|
END IF;
|
END IF;
|
next_micro_state <= movep3;
|
next_micro_state <= movep3;
|
WHEN movep3 =>
|
WHEN movep3 =>
|
IF opcode(6)='1' THEN
|
IF opcode(6)='1' THEN
|
set_movepw <= '1';
|
set_movepw <= '1';
|
next_micro_state <= movep4;
|
next_micro_state <= movep4;
|
END IF;
|
END IF;
|
IF opcode(7)='0' THEN
|
IF opcode(7)='0' THEN
|
setstate <= "10";
|
setstate <= "10";
|
ELSE
|
ELSE
|
setstate <= "11";
|
setstate <= "11";
|
END IF;
|
END IF;
|
WHEN movep4 =>
|
WHEN movep4 =>
|
IF opcode(7)='0' THEN
|
IF opcode(7)='0' THEN
|
setstate <= "10";
|
setstate <= "10";
|
ELSE
|
ELSE
|
wait_mem_byte <= '1';
|
wait_mem_byte <= '1';
|
setstate <= "11";
|
setstate <= "11";
|
END IF;
|
END IF;
|
next_micro_state <= movep5;
|
next_micro_state <= movep5;
|
WHEN movep5 =>
|
WHEN movep5 =>
|
IF opcode(7)='0' THEN
|
IF opcode(7)='0' THEN
|
setstate <= "10";
|
setstate <= "10";
|
ELSE
|
ELSE
|
setstate <= "11";
|
setstate <= "11";
|
END IF;
|
END IF;
|
|
|
WHEN init1 => -- init SP
|
WHEN init1 => -- init SP
|
longreaddirect <= '1';
|
longreaddirect <= '1';
|
next_micro_state <= init2;
|
next_micro_state <= init2;
|
WHEN init2 => -- init PC
|
WHEN init2 => -- init PC
|
get_ea_now <='1'; --\
|
get_ea_now <='1'; --\
|
ea_only <= '1'; --- OP1in <= memaddr_in
|
ea_only <= '1'; --- OP1in <= memaddr_in
|
setaddrlong <= '1'; -- memaddr_in <= data_read
|
setaddrlong <= '1'; -- memaddr_in <= data_read
|
regwrena <= '1';
|
regwrena <= '1';
|
setstackaddr <='1'; -- dest_addr <= SP
|
setstackaddr <='1'; -- dest_addr <= SP
|
set_directPC <= '1';
|
set_directPC <= '1';
|
longreaddirect <= '1';
|
longreaddirect <= '1';
|
next_micro_state <= nop;
|
next_micro_state <= nop;
|
|
|
WHEN mul1 => -- mulu
|
WHEN mul1 => -- mulu
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= mul2;
|
next_micro_state <= mul2;
|
WHEN mul2 => -- mulu
|
WHEN mul2 => -- mulu
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= mul3;
|
next_micro_state <= mul3;
|
WHEN mul3 => -- mulu
|
WHEN mul3 => -- mulu
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= mul4;
|
next_micro_state <= mul4;
|
WHEN mul4 => -- mulu
|
WHEN mul4 => -- mulu
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= mul5;
|
next_micro_state <= mul5;
|
WHEN mul5 => -- mulu
|
WHEN mul5 => -- mulu
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= mul6;
|
next_micro_state <= mul6;
|
WHEN mul6 => -- mulu
|
WHEN mul6 => -- mulu
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= mul7;
|
next_micro_state <= mul7;
|
WHEN mul7 => -- mulu
|
WHEN mul7 => -- mulu
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= mul8;
|
next_micro_state <= mul8;
|
WHEN mul8 => -- mulu
|
WHEN mul8 => -- mulu
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= mul9;
|
next_micro_state <= mul9;
|
WHEN mul9 => -- mulu
|
WHEN mul9 => -- mulu
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= mul10;
|
next_micro_state <= mul10;
|
WHEN mul10 => -- mulu
|
WHEN mul10 => -- mulu
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= mul11;
|
next_micro_state <= mul11;
|
WHEN mul11 => -- mulu
|
WHEN mul11 => -- mulu
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= mul12;
|
next_micro_state <= mul12;
|
WHEN mul12 => -- mulu
|
WHEN mul12 => -- mulu
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= mul13;
|
next_micro_state <= mul13;
|
WHEN mul13 => -- mulu
|
WHEN mul13 => -- mulu
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= mul14;
|
next_micro_state <= mul14;
|
WHEN mul14 => -- mulu
|
WHEN mul14 => -- mulu
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= mul15;
|
next_micro_state <= mul15;
|
WHEN mul15 => -- mulu
|
WHEN mul15 => -- mulu
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
|
|
WHEN div1 => -- divu
|
WHEN div1 => -- divu
|
IF OP2out(15 downto 0)=x"0000" THEN --div zero
|
IF OP2out(15 downto 0)=x"0000" THEN --div zero
|
set_Z_error <= '1';
|
set_Z_error <= '1';
|
ELSE
|
ELSE
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
next_micro_state <= div2;
|
next_micro_state <= div2;
|
END IF;
|
END IF;
|
setstate <="01";
|
setstate <="01";
|
WHEN div2 => -- divu
|
WHEN div2 => -- divu
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= div3;
|
next_micro_state <= div3;
|
WHEN div3 => -- divu
|
WHEN div3 => -- divu
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= div4;
|
next_micro_state <= div4;
|
WHEN div4 => -- divu
|
WHEN div4 => -- divu
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= div5;
|
next_micro_state <= div5;
|
WHEN div5 => -- divu
|
WHEN div5 => -- divu
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= div6;
|
next_micro_state <= div6;
|
WHEN div6 => -- divu
|
WHEN div6 => -- divu
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= div7;
|
next_micro_state <= div7;
|
WHEN div7 => -- divu
|
WHEN div7 => -- divu
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= div8;
|
next_micro_state <= div8;
|
WHEN div8 => -- divu
|
WHEN div8 => -- divu
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= div9;
|
next_micro_state <= div9;
|
WHEN div9 => -- divu
|
WHEN div9 => -- divu
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= div10;
|
next_micro_state <= div10;
|
WHEN div10 => -- divu
|
WHEN div10 => -- divu
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= div11;
|
next_micro_state <= div11;
|
WHEN div11 => -- divu
|
WHEN div11 => -- divu
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= div12;
|
next_micro_state <= div12;
|
WHEN div12 => -- divu
|
WHEN div12 => -- divu
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= div13;
|
next_micro_state <= div13;
|
WHEN div13 => -- divu
|
WHEN div13 => -- divu
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= div14;
|
next_micro_state <= div14;
|
WHEN div14 => -- divu
|
WHEN div14 => -- divu
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
setstate <="01";
|
setstate <="01";
|
next_micro_state <= div15;
|
next_micro_state <= div15;
|
WHEN div15 => -- divu
|
WHEN div15 => -- divu
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
|
|
WHEN OTHERS => null;
|
WHEN OTHERS => null;
|
END CASE;
|
END CASE;
|
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Conditions
|
-- Conditions
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (opcode, Flags)
|
PROCESS (opcode, Flags)
|
BEGIN
|
BEGIN
|
CASE opcode(11 downto 8) IS
|
CASE opcode(11 downto 8) IS
|
WHEN X"0" => condition <= '1';
|
WHEN X"0" => condition <= '1';
|
WHEN X"1" => condition <= '0';
|
WHEN X"1" => condition <= '0';
|
WHEN X"2" => condition <= NOT Flags(0) AND NOT Flags(2);
|
WHEN X"2" => condition <= NOT Flags(0) AND NOT Flags(2);
|
WHEN X"3" => condition <= Flags(0) OR Flags(2);
|
WHEN X"3" => condition <= Flags(0) OR Flags(2);
|
WHEN X"4" => condition <= NOT Flags(0);
|
WHEN X"4" => condition <= NOT Flags(0);
|
WHEN X"5" => condition <= Flags(0);
|
WHEN X"5" => condition <= Flags(0);
|
WHEN X"6" => condition <= NOT Flags(2);
|
WHEN X"6" => condition <= NOT Flags(2);
|
WHEN X"7" => condition <= Flags(2);
|
WHEN X"7" => condition <= Flags(2);
|
WHEN X"8" => condition <= NOT Flags(1);
|
WHEN X"8" => condition <= NOT Flags(1);
|
WHEN X"9" => condition <= Flags(1);
|
WHEN X"9" => condition <= Flags(1);
|
WHEN X"a" => condition <= NOT Flags(3);
|
WHEN X"a" => condition <= NOT Flags(3);
|
WHEN X"b" => condition <= Flags(3);
|
WHEN X"b" => condition <= Flags(3);
|
WHEN X"c" => condition <= (Flags(3) AND Flags(1)) OR (NOT Flags(3) AND NOT Flags(1));
|
WHEN X"c" => condition <= (Flags(3) AND Flags(1)) OR (NOT Flags(3) AND NOT Flags(1));
|
WHEN X"d" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1));
|
WHEN X"d" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1));
|
WHEN X"e" => condition <= (Flags(3) AND Flags(1) AND NOT Flags(2)) OR (NOT Flags(3) AND NOT Flags(1) AND NOT Flags(2));
|
WHEN X"e" => condition <= (Flags(3) AND Flags(1) AND NOT Flags(2)) OR (NOT Flags(3) AND NOT Flags(1) AND NOT Flags(2));
|
WHEN X"f" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR Flags(2);
|
WHEN X"f" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR Flags(2);
|
WHEN OTHERS => null;
|
WHEN OTHERS => null;
|
END CASE;
|
END CASE;
|
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Bits
|
-- Bits
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (opcode, OP1out, OP2out, one_bit_in, one_bit_out, bit_Number, bit_number_reg)
|
PROCESS (opcode, OP1out, OP2out, one_bit_in, one_bit_out, bit_Number, bit_number_reg)
|
BEGIN
|
BEGIN
|
CASE opcode(7 downto 6) IS
|
CASE opcode(7 downto 6) IS
|
WHEN "00" => --btst
|
WHEN "00" => --btst
|
one_bit_out <= one_bit_in;
|
one_bit_out <= one_bit_in;
|
WHEN "01" => --bchg
|
WHEN "01" => --bchg
|
one_bit_out <= NOT one_bit_in;
|
one_bit_out <= NOT one_bit_in;
|
WHEN "10" => --bclr
|
WHEN "10" => --bclr
|
one_bit_out <= '0';
|
one_bit_out <= '0';
|
WHEN "11" => --bset
|
WHEN "11" => --bset
|
one_bit_out <= '1';
|
one_bit_out <= '1';
|
WHEN OTHERS => null;
|
WHEN OTHERS => null;
|
END CASE;
|
END CASE;
|
|
|
IF opcode(8)='0' THEN
|
IF opcode(8)='0' THEN
|
IF opcode(5 downto 4)="00" THEN
|
IF opcode(5 downto 4)="00" THEN
|
bit_number <= bit_number_reg(4 downto 0);
|
bit_number <= bit_number_reg(4 downto 0);
|
ELSE
|
ELSE
|
bit_number <= "00"&bit_number_reg(2 downto 0);
|
bit_number <= "00"&bit_number_reg(2 downto 0);
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
IF opcode(5 downto 4)="00" THEN
|
IF opcode(5 downto 4)="00" THEN
|
bit_number <= OP2out(4 downto 0);
|
bit_number <= OP2out(4 downto 0);
|
ELSE
|
ELSE
|
bit_number <= "00"&OP2out(2 downto 0);
|
bit_number <= "00"&OP2out(2 downto 0);
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
bits_out <= OP1out;
|
bits_out <= OP1out;
|
CASE bit_Number IS
|
CASE bit_Number IS
|
WHEN "00000" => one_bit_in <= OP1out(0);
|
WHEN "00000" => one_bit_in <= OP1out(0);
|
bits_out(0) <= one_bit_out;
|
bits_out(0) <= one_bit_out;
|
WHEN "00001" => one_bit_in <= OP1out(1);
|
WHEN "00001" => one_bit_in <= OP1out(1);
|
bits_out(1) <= one_bit_out;
|
bits_out(1) <= one_bit_out;
|
WHEN "00010" => one_bit_in <= OP1out(2);
|
WHEN "00010" => one_bit_in <= OP1out(2);
|
bits_out(2) <= one_bit_out;
|
bits_out(2) <= one_bit_out;
|
WHEN "00011" => one_bit_in <= OP1out(3);
|
WHEN "00011" => one_bit_in <= OP1out(3);
|
bits_out(3) <= one_bit_out;
|
bits_out(3) <= one_bit_out;
|
WHEN "00100" => one_bit_in <= OP1out(4);
|
WHEN "00100" => one_bit_in <= OP1out(4);
|
bits_out(4) <= one_bit_out;
|
bits_out(4) <= one_bit_out;
|
WHEN "00101" => one_bit_in <= OP1out(5);
|
WHEN "00101" => one_bit_in <= OP1out(5);
|
bits_out(5) <= one_bit_out;
|
bits_out(5) <= one_bit_out;
|
WHEN "00110" => one_bit_in <= OP1out(6);
|
WHEN "00110" => one_bit_in <= OP1out(6);
|
bits_out(6) <= one_bit_out;
|
bits_out(6) <= one_bit_out;
|
WHEN "00111" => one_bit_in <= OP1out(7);
|
WHEN "00111" => one_bit_in <= OP1out(7);
|
bits_out(7) <= one_bit_out;
|
bits_out(7) <= one_bit_out;
|
WHEN "01000" => one_bit_in <= OP1out(8);
|
WHEN "01000" => one_bit_in <= OP1out(8);
|
bits_out(8) <= one_bit_out;
|
bits_out(8) <= one_bit_out;
|
WHEN "01001" => one_bit_in <= OP1out(9);
|
WHEN "01001" => one_bit_in <= OP1out(9);
|
bits_out(9) <= one_bit_out;
|
bits_out(9) <= one_bit_out;
|
WHEN "01010" => one_bit_in <= OP1out(10);
|
WHEN "01010" => one_bit_in <= OP1out(10);
|
bits_out(10) <= one_bit_out;
|
bits_out(10) <= one_bit_out;
|
WHEN "01011" => one_bit_in <= OP1out(11);
|
WHEN "01011" => one_bit_in <= OP1out(11);
|
bits_out(11) <= one_bit_out;
|
bits_out(11) <= one_bit_out;
|
WHEN "01100" => one_bit_in <= OP1out(12);
|
WHEN "01100" => one_bit_in <= OP1out(12);
|
bits_out(12) <= one_bit_out;
|
bits_out(12) <= one_bit_out;
|
WHEN "01101" => one_bit_in <= OP1out(13);
|
WHEN "01101" => one_bit_in <= OP1out(13);
|
bits_out(13) <= one_bit_out;
|
bits_out(13) <= one_bit_out;
|
WHEN "01110" => one_bit_in <= OP1out(14);
|
WHEN "01110" => one_bit_in <= OP1out(14);
|
bits_out(14) <= one_bit_out;
|
bits_out(14) <= one_bit_out;
|
WHEN "01111" => one_bit_in <= OP1out(15);
|
WHEN "01111" => one_bit_in <= OP1out(15);
|
bits_out(15) <= one_bit_out;
|
bits_out(15) <= one_bit_out;
|
WHEN "10000" => one_bit_in <= OP1out(16);
|
WHEN "10000" => one_bit_in <= OP1out(16);
|
bits_out(16) <= one_bit_out;
|
bits_out(16) <= one_bit_out;
|
WHEN "10001" => one_bit_in <= OP1out(17);
|
WHEN "10001" => one_bit_in <= OP1out(17);
|
bits_out(17) <= one_bit_out;
|
bits_out(17) <= one_bit_out;
|
WHEN "10010" => one_bit_in <= OP1out(18);
|
WHEN "10010" => one_bit_in <= OP1out(18);
|
bits_out(18) <= one_bit_out;
|
bits_out(18) <= one_bit_out;
|
WHEN "10011" => one_bit_in <= OP1out(19);
|
WHEN "10011" => one_bit_in <= OP1out(19);
|
bits_out(19) <= one_bit_out;
|
bits_out(19) <= one_bit_out;
|
WHEN "10100" => one_bit_in <= OP1out(20);
|
WHEN "10100" => one_bit_in <= OP1out(20);
|
bits_out(20) <= one_bit_out;
|
bits_out(20) <= one_bit_out;
|
WHEN "10101" => one_bit_in <= OP1out(21);
|
WHEN "10101" => one_bit_in <= OP1out(21);
|
bits_out(21) <= one_bit_out;
|
bits_out(21) <= one_bit_out;
|
WHEN "10110" => one_bit_in <= OP1out(22);
|
WHEN "10110" => one_bit_in <= OP1out(22);
|
bits_out(22) <= one_bit_out;
|
bits_out(22) <= one_bit_out;
|
WHEN "10111" => one_bit_in <= OP1out(23);
|
WHEN "10111" => one_bit_in <= OP1out(23);
|
bits_out(23) <= one_bit_out;
|
bits_out(23) <= one_bit_out;
|
WHEN "11000" => one_bit_in <= OP1out(24);
|
WHEN "11000" => one_bit_in <= OP1out(24);
|
bits_out(24) <= one_bit_out;
|
bits_out(24) <= one_bit_out;
|
WHEN "11001" => one_bit_in <= OP1out(25);
|
WHEN "11001" => one_bit_in <= OP1out(25);
|
bits_out(25) <= one_bit_out;
|
bits_out(25) <= one_bit_out;
|
WHEN "11010" => one_bit_in <= OP1out(26);
|
WHEN "11010" => one_bit_in <= OP1out(26);
|
bits_out(26) <= one_bit_out;
|
bits_out(26) <= one_bit_out;
|
WHEN "11011" => one_bit_in <= OP1out(27);
|
WHEN "11011" => one_bit_in <= OP1out(27);
|
bits_out(27) <= one_bit_out;
|
bits_out(27) <= one_bit_out;
|
WHEN "11100" => one_bit_in <= OP1out(28);
|
WHEN "11100" => one_bit_in <= OP1out(28);
|
bits_out(28) <= one_bit_out;
|
bits_out(28) <= one_bit_out;
|
WHEN "11101" => one_bit_in <= OP1out(29);
|
WHEN "11101" => one_bit_in <= OP1out(29);
|
bits_out(29) <= one_bit_out;
|
bits_out(29) <= one_bit_out;
|
WHEN "11110" => one_bit_in <= OP1out(30);
|
WHEN "11110" => one_bit_in <= OP1out(30);
|
bits_out(30) <= one_bit_out;
|
bits_out(30) <= one_bit_out;
|
WHEN "11111" => one_bit_in <= OP1out(31);
|
WHEN "11111" => one_bit_in <= OP1out(31);
|
bits_out(31) <= one_bit_out;
|
bits_out(31) <= one_bit_out;
|
WHEN OTHERS => null;
|
WHEN OTHERS => null;
|
END CASE;
|
END CASE;
|
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Rotation
|
-- Rotation
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, rot_nop)
|
PROCESS (opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, rot_nop)
|
BEGIN
|
BEGIN
|
CASE opcode(7 downto 6) IS
|
CASE opcode(7 downto 6) IS
|
WHEN "00" => --Byte
|
WHEN "00" => --Byte
|
rot_rot <= OP1out(7);
|
rot_rot <= OP1out(7);
|
WHEN "01"|"11" => --Word
|
WHEN "01"|"11" => --Word
|
rot_rot <= OP1out(15);
|
rot_rot <= OP1out(15);
|
WHEN "10" => --Long
|
WHEN "10" => --Long
|
rot_rot <= OP1out(31);
|
rot_rot <= OP1out(31);
|
WHEN OTHERS => null;
|
WHEN OTHERS => null;
|
END CASE;
|
END CASE;
|
|
|
CASE rot_bits IS
|
CASE rot_bits IS
|
WHEN "00" => --ASL, ASR
|
WHEN "00" => --ASL, ASR
|
rot_lsb <= '0';
|
rot_lsb <= '0';
|
rot_msb <= rot_rot;
|
rot_msb <= rot_rot;
|
WHEN "01" => --LSL, LSR
|
WHEN "01" => --LSL, LSR
|
rot_lsb <= '0';
|
rot_lsb <= '0';
|
rot_msb <= '0';
|
rot_msb <= '0';
|
WHEN "10" => --ROXL, ROXR
|
WHEN "10" => --ROXL, ROXR
|
rot_lsb <= Flags(4);
|
rot_lsb <= Flags(4);
|
rot_msb <= Flags(4);
|
rot_msb <= Flags(4);
|
WHEN "11" => --ROL, ROR
|
WHEN "11" => --ROL, ROR
|
rot_lsb <= rot_rot;
|
rot_lsb <= rot_rot;
|
rot_msb <= OP1out(0);
|
rot_msb <= OP1out(0);
|
WHEN OTHERS => null;
|
WHEN OTHERS => null;
|
END CASE;
|
END CASE;
|
|
|
IF rot_nop='1' THEN
|
IF rot_nop='1' THEN
|
rot_out <= OP1out;
|
rot_out <= OP1out;
|
rot_XC <= Flags(0);
|
rot_XC <= Flags(0);
|
ELSE
|
ELSE
|
IF opcode(8)='1' THEN --left
|
IF opcode(8)='1' THEN --left
|
rot_out <= OP1out(30 downto 0)&rot_lsb;
|
rot_out <= OP1out(30 downto 0)&rot_lsb;
|
rot_XC <= rot_rot;
|
rot_XC <= rot_rot;
|
ELSE --right
|
ELSE --right
|
rot_XC <= OP1out(0);
|
rot_XC <= OP1out(0);
|
rot_out <= rot_msb&OP1out(31 downto 1);
|
rot_out <= rot_msb&OP1out(31 downto 1);
|
CASE opcode(7 downto 6) IS
|
CASE opcode(7 downto 6) IS
|
WHEN "00" => --Byte
|
WHEN "00" => --Byte
|
rot_out(7) <= rot_msb;
|
rot_out(7) <= rot_msb;
|
WHEN "01"|"11" => --Word
|
WHEN "01"|"11" => --Word
|
rot_out(15) <= rot_msb;
|
rot_out(15) <= rot_msb;
|
WHEN OTHERS =>
|
WHEN OTHERS =>
|
END CASE;
|
END CASE;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- MULU/MULS
|
-- MULU/MULS
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (clk, opcode, OP2out, muls_msb, mulu_reg, OP1sign, sign2)
|
PROCESS (clk, opcode, OP2out, muls_msb, mulu_reg, OP1sign, sign2)
|
BEGIN
|
BEGIN
|
IF rising_edge(clk) THEN
|
IF rising_edge(clk) THEN
|
IF clkena='1' THEN
|
IF clkena='1' THEN
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
IF opcode(8)='1' AND reg_QB(15)='1' THEN --MULS Neg faktor
|
IF opcode(8)='1' AND reg_QB(15)='1' THEN --MULS Neg faktor
|
OP1sign <= '1';
|
OP1sign <= '1';
|
mulu_reg <= "0000000000000000"&(0-reg_QB(15 downto 0));
|
mulu_reg <= "0000000000000000"&(0-reg_QB(15 downto 0));
|
ELSE
|
ELSE
|
OP1sign <= '0';
|
OP1sign <= '0';
|
mulu_reg <= "0000000000000000"®_QB(15 downto 0);
|
mulu_reg <= "0000000000000000"®_QB(15 downto 0);
|
END IF;
|
END IF;
|
ELSIF exec_MULU='1' THEN
|
ELSIF exec_MULU='1' THEN
|
mulu_reg <= dummy_mulu;
|
mulu_reg <= dummy_mulu;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
IF (opcode(8)='1' AND OP2out(15)='1') OR OP1sign='1' THEN
|
IF (opcode(8)='1' AND OP2out(15)='1') OR OP1sign='1' THEN
|
muls_msb <= mulu_reg(31);
|
muls_msb <= mulu_reg(31);
|
ELSE
|
ELSE
|
muls_msb <= '0';
|
muls_msb <= '0';
|
END IF;
|
END IF;
|
|
|
IF opcode(8)='1' AND OP2out(15)='1' THEN
|
IF opcode(8)='1' AND OP2out(15)='1' THEN
|
sign2 <= '1';
|
sign2 <= '1';
|
ELSE
|
ELSE
|
sign2 <= '0';
|
sign2 <= '0';
|
END IF;
|
END IF;
|
|
|
IF mulu_reg(0)='1' THEN
|
IF mulu_reg(0)='1' THEN
|
IF OP1sign='1' THEN
|
IF OP1sign='1' THEN
|
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))-(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
|
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))-(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
|
ELSE
|
ELSE
|
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))+(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
|
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))+(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
dummy_mulu <= muls_msb&mulu_reg(31 downto 1);
|
dummy_mulu <= muls_msb&mulu_reg(31 downto 1);
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- DIVU
|
-- DIVU
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (clk, execOPC, opcode, OP1out, OP2out, div_reg, dummy_div_sub, div_quot, div_sign, dummy_div_over, dummy_div)
|
PROCESS (clk, execOPC, opcode, OP1out, OP2out, div_reg, dummy_div_sub, div_quot, div_sign, dummy_div_over, dummy_div)
|
BEGIN
|
BEGIN
|
set_V_Flag <= '0';
|
set_V_Flag <= '0';
|
|
|
IF rising_edge(clk) THEN
|
IF rising_edge(clk) THEN
|
IF clkena='1' THEN
|
IF clkena='1' THEN
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
IF opcode(8)='1' AND reg_QB(31)='1' THEN -- Neg divisor
|
IF opcode(8)='1' AND reg_QB(31)='1' THEN -- Neg divisor
|
div_sign <= '1';
|
div_sign <= '1';
|
div_reg <= 0-reg_QB;
|
div_reg <= 0-reg_QB;
|
ELSE
|
ELSE
|
div_sign <= '0';
|
div_sign <= '0';
|
div_reg <= reg_QB;
|
div_reg <= reg_QB;
|
END IF;
|
END IF;
|
ELSIF exec_DIVU='1' THEN
|
ELSIF exec_DIVU='1' THEN
|
div_reg <= div_quot;
|
div_reg <= div_quot;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
dummy_div_over <= ('0'&OP1out(31 downto 16))-('0'&OP2out(15 downto 0));
|
dummy_div_over <= ('0'&OP1out(31 downto 16))-('0'&OP2out(15 downto 0));
|
|
|
IF opcode(8)='1' AND OP2out(15) ='1' THEN
|
IF opcode(8)='1' AND OP2out(15) ='1' THEN
|
dummy_div_sub <= (div_reg(31 downto 15))+('1'&OP2out(15 downto 0));
|
dummy_div_sub <= (div_reg(31 downto 15))+('1'&OP2out(15 downto 0));
|
ELSE
|
ELSE
|
dummy_div_sub <= (div_reg(31 downto 15))-('0'&OP2out(15 downto 0));
|
dummy_div_sub <= (div_reg(31 downto 15))-('0'&OP2out(15 downto 0));
|
END IF;
|
END IF;
|
|
|
IF (dummy_div_sub(16))='1' THEN
|
IF (dummy_div_sub(16))='1' THEN
|
div_quot(31 downto 16) <= div_reg(30 downto 15);
|
div_quot(31 downto 16) <= div_reg(30 downto 15);
|
ELSE
|
ELSE
|
div_quot(31 downto 16) <= dummy_div_sub(15 downto 0);
|
div_quot(31 downto 16) <= dummy_div_sub(15 downto 0);
|
END IF;
|
END IF;
|
|
|
div_quot(15 downto 0) <= div_reg(14 downto 0)&NOT dummy_div_sub(16);
|
div_quot(15 downto 0) <= div_reg(14 downto 0)&NOT dummy_div_sub(16);
|
|
|
IF execOPC='1' AND opcode(8)='1' AND (OP2out(15) XOR div_sign)='1' THEN
|
IF execOPC='1' AND opcode(8)='1' AND (OP2out(15) XOR div_sign)='1' THEN
|
dummy_div(15 downto 0) <= 0-div_quot(15 downto 0);
|
dummy_div(15 downto 0) <= 0-div_quot(15 downto 0);
|
ELSE
|
ELSE
|
dummy_div(15 downto 0) <= div_quot(15 downto 0);
|
dummy_div(15 downto 0) <= div_quot(15 downto 0);
|
END IF;
|
END IF;
|
|
|
IF div_sign='1' THEN
|
IF div_sign='1' THEN
|
dummy_div(31 downto 16) <= 0-div_quot(31 downto 16);
|
dummy_div(31 downto 16) <= 0-div_quot(31 downto 16);
|
ELSE
|
ELSE
|
dummy_div(31 downto 16) <= div_quot(31 downto 16);
|
dummy_div(31 downto 16) <= div_quot(31 downto 16);
|
END IF;
|
END IF;
|
|
|
IF (opcode(8)='1' AND (OP2out(15) XOR div_sign XOR dummy_div(15))='1' AND dummy_div(15 downto 0)/=X"0000") --Overflow DIVS
|
IF (opcode(8)='1' AND (OP2out(15) XOR div_sign XOR dummy_div(15))='1' AND dummy_div(15 downto 0)/=X"0000") --Overflow DIVS
|
OR (opcode(8)='0' AND dummy_div_over(16)='0') THEN --Overflow DIVU
|
OR (opcode(8)='0' AND dummy_div_over(16)='0') THEN --Overflow DIVU
|
set_V_Flag <= '1';
|
set_V_Flag <= '1';
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Movem
|
-- Movem
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (reset, clk, movem_mask, movem_muxa ,movem_muxb, movem_muxc)
|
PROCESS (reset, clk, movem_mask, movem_muxa ,movem_muxb, movem_muxc)
|
BEGIN
|
BEGIN
|
IF movem_mask(7 downto 0)="00000000" THEN
|
IF movem_mask(7 downto 0)="00000000" THEN
|
movem_muxa <= movem_mask(15 downto 8);
|
movem_muxa <= movem_mask(15 downto 8);
|
movem_regaddr(3) <= '1';
|
movem_regaddr(3) <= '1';
|
ELSE
|
ELSE
|
movem_muxa <= movem_mask(7 downto 0);
|
movem_muxa <= movem_mask(7 downto 0);
|
movem_regaddr(3) <= '0';
|
movem_regaddr(3) <= '0';
|
END IF;
|
END IF;
|
IF movem_muxa(3 downto 0)="0000" THEN
|
IF movem_muxa(3 downto 0)="0000" THEN
|
movem_muxb <= movem_muxa(7 downto 4);
|
movem_muxb <= movem_muxa(7 downto 4);
|
movem_regaddr(2) <= '1';
|
movem_regaddr(2) <= '1';
|
ELSE
|
ELSE
|
movem_muxb <= movem_muxa(3 downto 0);
|
movem_muxb <= movem_muxa(3 downto 0);
|
movem_regaddr(2) <= '0';
|
movem_regaddr(2) <= '0';
|
END IF;
|
END IF;
|
IF movem_muxb(1 downto 0)="00" THEN
|
IF movem_muxb(1 downto 0)="00" THEN
|
movem_muxc <= movem_muxb(3 downto 2);
|
movem_muxc <= movem_muxb(3 downto 2);
|
movem_regaddr(1) <= '1';
|
movem_regaddr(1) <= '1';
|
ELSE
|
ELSE
|
movem_muxc <= movem_muxb(1 downto 0);
|
movem_muxc <= movem_muxb(1 downto 0);
|
movem_regaddr(1) <= '0';
|
movem_regaddr(1) <= '0';
|
END IF;
|
END IF;
|
IF movem_muxc(0)='0' THEN
|
IF movem_muxc(0)='0' THEN
|
movem_regaddr(0) <= '1';
|
movem_regaddr(0) <= '1';
|
ELSE
|
ELSE
|
movem_regaddr(0) <= '0';
|
movem_regaddr(0) <= '0';
|
END IF;
|
END IF;
|
|
|
movem_bits <= ("0000"&movem_mask(0))+("0000"&movem_mask(1))+("0000"&movem_mask(2))+("0000"&movem_mask(3))+
|
movem_bits <= ("0000"&movem_mask(0))+("0000"&movem_mask(1))+("0000"&movem_mask(2))+("0000"&movem_mask(3))+
|
("0000"&movem_mask(4))+("0000"&movem_mask(5))+("0000"&movem_mask(6))+("0000"&movem_mask(7))+
|
("0000"&movem_mask(4))+("0000"&movem_mask(5))+("0000"&movem_mask(6))+("0000"&movem_mask(7))+
|
("0000"&movem_mask(8))+("0000"&movem_mask(9))+("0000"&movem_mask(10))+("0000"&movem_mask(11))+
|
("0000"&movem_mask(8))+("0000"&movem_mask(9))+("0000"&movem_mask(10))+("0000"&movem_mask(11))+
|
("0000"&movem_mask(12))+("0000"&movem_mask(13))+("0000"&movem_mask(14))+("0000"&movem_mask(15));
|
("0000"&movem_mask(12))+("0000"&movem_mask(13))+("0000"&movem_mask(14))+("0000"&movem_mask(15));
|
|
|
IF reset = '0' THEN
|
IF reset = '0' THEN
|
movem_busy <= '0';
|
movem_busy <= '0';
|
movem_addr <= '0';
|
movem_addr <= '0';
|
|
maskzero <= '0';
|
ELSIF rising_edge(clk) THEN
|
ELSIF rising_edge(clk) THEN
|
IF clkena_in='1' AND get_movem_mask='1' THEN
|
IF clkena_in='1' AND get_movem_mask='1' THEN
|
movem_mask <= data_read(15 downto 0);
|
movem_mask <= data_read(15 downto 0);
|
END IF;
|
END IF;
|
|
IF clkena_in='1' AND test_maskzero='1' THEN
|
|
IF movem_mask=X"0000" THEN
|
|
maskzero <= '1';
|
|
END IF;
|
|
END IF;
|
|
IF clkena_in='1' AND endOPC='1' THEN
|
|
maskzero <= '0';
|
|
END IF;
|
IF clkena='1' THEN
|
IF clkena='1' THEN
|
IF set_movem_busy='1' THEN
|
IF set_movem_busy='1' THEN
|
IF movem_bits(3 downto 1) /= "000" OR opcode(10)='0' THEN
|
IF movem_bits(4 downto 1) /= "0000" OR opcode(10)='0' THEN
|
movem_busy <= '1';
|
movem_busy <= '1';
|
END IF;
|
END IF;
|
movem_addr <= '1';
|
movem_addr <= '1';
|
END IF;
|
END IF;
|
IF movem_addr='1' THEN
|
IF movem_addr='1' THEN
|
CASE movem_regaddr IS
|
CASE movem_regaddr IS
|
WHEN "0000" => movem_mask(0) <= '0';
|
WHEN "0000" => movem_mask(0) <= '0';
|
WHEN "0001" => movem_mask(1) <= '0';
|
WHEN "0001" => movem_mask(1) <= '0';
|
WHEN "0010" => movem_mask(2) <= '0';
|
WHEN "0010" => movem_mask(2) <= '0';
|
WHEN "0011" => movem_mask(3) <= '0';
|
WHEN "0011" => movem_mask(3) <= '0';
|
WHEN "0100" => movem_mask(4) <= '0';
|
WHEN "0100" => movem_mask(4) <= '0';
|
WHEN "0101" => movem_mask(5) <= '0';
|
WHEN "0101" => movem_mask(5) <= '0';
|
WHEN "0110" => movem_mask(6) <= '0';
|
WHEN "0110" => movem_mask(6) <= '0';
|
WHEN "0111" => movem_mask(7) <= '0';
|
WHEN "0111" => movem_mask(7) <= '0';
|
WHEN "1000" => movem_mask(8) <= '0';
|
WHEN "1000" => movem_mask(8) <= '0';
|
WHEN "1001" => movem_mask(9) <= '0';
|
WHEN "1001" => movem_mask(9) <= '0';
|
WHEN "1010" => movem_mask(10) <= '0';
|
WHEN "1010" => movem_mask(10) <= '0';
|
WHEN "1011" => movem_mask(11) <= '0';
|
WHEN "1011" => movem_mask(11) <= '0';
|
WHEN "1100" => movem_mask(12) <= '0';
|
WHEN "1100" => movem_mask(12) <= '0';
|
WHEN "1101" => movem_mask(13) <= '0';
|
WHEN "1101" => movem_mask(13) <= '0';
|
WHEN "1110" => movem_mask(14) <= '0';
|
WHEN "1110" => movem_mask(14) <= '0';
|
WHEN "1111" => movem_mask(15) <= '0';
|
WHEN "1111" => movem_mask(15) <= '0';
|
WHEN OTHERS => null;
|
WHEN OTHERS => null;
|
END CASE;
|
END CASE;
|
IF opcode(10)='1' THEN
|
IF opcode(10)='1' THEN
|
IF movem_bits="00010" OR movem_bits="00001" OR movem_bits="00000" THEN
|
IF movem_bits="00010" OR movem_bits="00001" OR movem_bits="00000" THEN
|
movem_busy <= '0';
|
movem_busy <= '0';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF movem_bits="00001" OR movem_bits="00000" THEN
|
IF movem_bits="00001" OR movem_bits="00000" THEN
|
movem_busy <= '0';
|
movem_busy <= '0';
|
movem_addr <= '0';
|
movem_addr <= '0';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
END;
|
END;
|
|
|
