| Line 35... |
Line 35... |
BarrelShifter :integer --0=>no, 1=>yes, 2=>switchable with CPU(1)
|
BarrelShifter :integer --0=>no, 1=>yes, 2=>switchable with CPU(1)
|
);
|
);
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
Reset : in std_logic;
|
Reset : in std_logic;
|
clkena_lw : in std_logic:='1';
|
clkena_lw : in std_logic:='1';
|
|
CPU : in std_logic_vector(1 downto 0):="00"; -- 00->68000 01->68010 11->68020(only some parts - yet)
|
execOPC : in bit;
|
execOPC : in bit;
|
decodeOPC : in bit;
|
decodeOPC : in bit;
|
exe_condition : in std_logic;
|
exe_condition : in std_logic;
|
exec_tas : in std_logic;
|
exec_tas : in std_logic;
|
long_start : in bit;
|
long_start : in bit;
|
| Line 90... |
Line 91... |
signal opaddsub : bit;
|
signal opaddsub : bit;
|
signal c_in : std_logic_vector(3 downto 0);
|
signal c_in : std_logic_vector(3 downto 0);
|
signal flag_z : std_logic_vector(2 downto 0);
|
signal flag_z : std_logic_vector(2 downto 0);
|
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
|
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
|
signal CCRin : std_logic_vector(7 downto 0);
|
signal CCRin : std_logic_vector(7 downto 0);
|
|
signal last_Flags1 : std_logic_vector(3 downto 0); --NZVC
|
|
|
--BCD
|
--BCD
|
signal bcd_pur : std_logic_vector(9 downto 0);
|
signal bcd_pur : std_logic_vector(9 downto 0);
|
signal bcd_kor : std_logic_vector(8 downto 0);
|
signal bcd_kor : std_logic_vector(8 downto 0);
|
signal halve_carry : std_logic;
|
signal halve_carry : std_logic;
|
| Line 134... |
Line 136... |
signal div_bit : std_logic;
|
signal div_bit : std_logic;
|
signal div_sub : std_logic_vector(32 downto 0);
|
signal div_sub : std_logic_vector(32 downto 0);
|
signal div_over : std_logic_vector(32 downto 0);
|
signal div_over : std_logic_vector(32 downto 0);
|
signal nozero : std_logic;
|
signal nozero : std_logic;
|
signal div_qsign : std_logic;
|
signal div_qsign : std_logic;
|
signal divisor : std_logic_vector(63 downto 0);
|
signal divident : std_logic_vector(63 downto 0);
|
signal divs : std_logic;
|
signal divs : std_logic;
|
signal signedOP : std_logic;
|
signal signedOP : std_logic;
|
signal OP1_sign : std_logic;
|
signal OP1_sign : std_logic;
|
signal OP2_sign : std_logic;
|
signal OP2_sign : std_logic;
|
signal OP2outext : std_logic_vector(15 downto 0);
|
signal OP2outext : std_logic_vector(15 downto 0);
|
| Line 251... |
Line 253... |
OP1in <= OP2out AND OP1out;
|
OP1in <= OP2out AND OP1out;
|
ELSIF exec(opcScc)='1' THEN
|
ELSIF exec(opcScc)='1' THEN
|
OP1in(7 downto 0) <= (others=>exe_condition);
|
OP1in(7 downto 0) <= (others=>exe_condition);
|
ELSIF exec(opcEOR)='1' THEN
|
ELSIF exec(opcEOR)='1' THEN
|
OP1in <= OP2out XOR OP1out;
|
OP1in <= OP2out XOR OP1out;
|
ELSIF exec(opcMOVE)='1' OR exec(exg)='1' THEN
|
-- ELSIF exec(alu_move)='1' OR exec(exg)='1' THEN
|
|
ELSIF exec(alu_move)='1' THEN
|
-- OP1in <= OP2out(31 downto 8)&(OP2out(7)OR exec_tas)&OP2out(6 downto 0);
|
-- OP1in <= OP2out(31 downto 8)&(OP2out(7)OR exec_tas)&OP2out(6 downto 0);
|
OP1in <= OP2out;
|
OP1in <= OP2out;
|
ELSIF exec(opcROT)='1' THEN
|
ELSIF exec(opcROT)='1' THEN
|
OP1in <= rot_out;
|
OP1in <= rot_out;
|
ELSIF exec(exec_BS)='1' THEN
|
ELSIF exec(exec_BS)='1' THEN
|
| Line 356... |
Line 359... |
END PROCESS;
|
END PROCESS;
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
--ALU
|
--ALU
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
PROCESS (OP1out, OP2out, exec, add_result, bcd_pur, bcd_a, bcd_kor, halve_carry, c_in)
|
PROCESS (OP1out, OP2out, CPU, exec, add_result, bcd_pur, bcd_a, bcd_kor, halve_carry, c_in)
|
BEGIN
|
BEGIN
|
--BCD_ARITH-------------------------------------------------------------------
|
--BCD_ARITH-------------------------------------------------------------------
|
--04.04.2017 by Tobiflex - BCD handling with all undefined behavior!
|
--04.04.2017 by Tobiflex - BCD handling with all undefined behavior!
|
bcd_pur <= c_in(1)&add_result(8 downto 0);
|
bcd_pur <= c_in(1)&add_result(8 downto 0);
|
bcd_kor <= "000000000";
|
bcd_kor <= "000000000";
|
| Line 384... |
Line 387... |
ELSE --opcSBCD
|
ELSE --opcSBCD
|
Vflag_a <= bcd_pur(8) AND NOT bcd_a(7);
|
Vflag_a <= bcd_pur(8) AND NOT bcd_a(7);
|
-- bcd_pur <= ('0'&OP1out(7 downto 0)&'0') - ('0'&OP2out(7 downto 0)&Flags(4));
|
-- bcd_pur <= ('0'&OP1out(7 downto 0)&'0') - ('0'&OP2out(7 downto 0)&Flags(4));
|
bcd_a <= bcd_pur(9 downto 1) - bcd_kor;
|
bcd_a <= bcd_pur(9 downto 1) - bcd_kor;
|
END IF;
|
END IF;
|
-- IF cpu(1)='1' THEN
|
IF cpu(1)='1' THEN
|
Vflag_a <= '0'; --TG 01.11.2019 only for cputest -- but other behaiver in real 68000 Hardware ??? I must check this later
|
Vflag_a <= '0'; --68020
|
-- END IF;
|
END IF;
|
bcd_a_carry <= bcd_pur(9) OR bcd_a(8);
|
bcd_a_carry <= bcd_pur(9) OR bcd_a(8);
|
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Bits
|
-- Bits
|
| Line 970... |
Line 973... |
Flags(3 downto 0) <= '0'&NOT reg_QA(31)&"00";
|
Flags(3 downto 0) <= '0'&NOT reg_QA(31)&"00";
|
ELSE
|
ELSE
|
Flags(3 downto 0) <= "0100";
|
Flags(3 downto 0) <= "0100";
|
END IF;
|
END IF;
|
ELSIF exec(no_Flags)='0' THEN
|
ELSIF exec(no_Flags)='0' THEN
|
|
last_Flags1 <= Flags(3 downto 0);
|
IF exec(opcADD)='1' THEN
|
IF exec(opcADD)='1' THEN
|
Flags(4) <= set_flags(0);
|
Flags(4) <= set_flags(0);
|
ELSIF exec(opcROT)='1' AND rot_bits/="11" AND exec(rot_nop)='0' THEN
|
ELSIF exec(opcROT)='1' AND rot_bits/="11" AND exec(rot_nop)='0' THEN
|
Flags(4) <= rot_X;
|
Flags(4) <= rot_X;
|
ELSIF exec(exec_BS)='1' THEN
|
ELSIF exec(exec_BS)='1' THEN
|
Flags(4) <= BS_X;
|
Flags(4) <= BS_X;
|
END IF;
|
END IF;
|
|
|
IF (exec(opcADD) OR exec(opcCMP))='1' THEN
|
-- IF (exec(opcADD) OR exec(opcCMP))='1' OR exec(alu_setFlags)='1' THEN
|
|
IF (exec(opcCMP) OR exec(alu_setFlags))='1' THEN
|
Flags(3 downto 0) <= set_flags;
|
Flags(3 downto 0) <= set_flags;
|
ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
|
ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
|
IF V_Flag='1' THEN
|
IF V_Flag='1' THEN
|
Flags(3 downto 0) <= "1010";
|
Flags(3 downto 0) <= "1010";
|
ELSIF exe_opcode(15)='1' OR DIV_Mode=0 THEN
|
ELSIF exe_opcode(15)='1' OR DIV_Mode=0 THEN
|
| Line 1018... |
Line 1023... |
Flags(3 downto 2) <= set_flags(3 downto 2);
|
Flags(3 downto 2) <= set_flags(3 downto 2);
|
Flags(0) <= BS_C;
|
Flags(0) <= BS_C;
|
Flags(1) <= BS_V;
|
Flags(1) <= BS_V;
|
ELSIF exec(opcBITS)='1' THEN
|
ELSIF exec(opcBITS)='1' THEN
|
Flags(2) <= NOT one_bit_in;
|
Flags(2) <= NOT one_bit_in;
|
|
ELSIF exec(opcCHK2)='1' THEN
|
|
Flags(0) <= '0';
|
|
Flags(2) <= Flags(2) OR set_flags(2);
|
|
----lower bound first
|
|
IF last_Flags1(0)='0' THEN --unsigned OP
|
|
Flags(0) <= Flags(0) OR (NOT set_flags(0) AND NOT set_flags(2));
|
|
ELSE --signed OP
|
|
Flags(0) <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR --LT
|
|
(set_flags(3) AND set_flags(1) AND NOT set_flags(2)) OR (NOT set_flags(3) AND NOT set_flags(1) AND NOT set_flags(2)); --GT
|
|
END IF;
|
ELSIF exec(opcCHK)='1' THEN
|
ELSIF exec(opcCHK)='1' THEN
|
IF exe_datatype="01" THEN --Word
|
IF exe_datatype="01" THEN --Word
|
Flags(3) <= OP1out(15);
|
Flags(3) <= OP1out(15);
|
ELSE
|
ELSE
|
Flags(3) <= OP1out(31);
|
Flags(3) <= OP1out(31);
|
| Line 1030... |
Line 1045... |
Flags(2) <='1';
|
Flags(2) <='1';
|
ELSE
|
ELSE
|
Flags(2) <='0';
|
Flags(2) <='0';
|
END IF;
|
END IF;
|
Flags(1) <= '0';
|
Flags(1) <= '0';
|
Flags(0) <= NOT set_flags(0);
|
Flags(0) <= '0';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
Flags(7 downto 5) <= "000";
|
Flags(7 downto 5) <= "000";
|
END IF;
|
END IF;
|
| Line 1172... |
Line 1187... |
|
|
PROCESS (execOPC, OP1out, OP2out, div_reg, div_neg, div_bit, div_sub, div_quot, OP1_sign, div_over, result_div, reg_QA, opcode, sndOPC, divs, exe_opcode, reg_QB,
|
PROCESS (execOPC, OP1out, OP2out, div_reg, div_neg, div_bit, div_sub, div_quot, OP1_sign, div_over, result_div, reg_QA, opcode, sndOPC, divs, exe_opcode, reg_QB,
|
signedOP, nozero, div_qsign, OP2outext)
|
signedOP, nozero, div_qsign, OP2outext)
|
BEGIN
|
BEGIN
|
divs <= (opcode(15) AND opcode(8)) OR (NOT opcode(15) AND sndOPC(11));
|
divs <= (opcode(15) AND opcode(8)) OR (NOT opcode(15) AND sndOPC(11));
|
divisor(15 downto 0) <= (OTHERS=> '0');
|
divident(15 downto 0) <= (OTHERS=> '0');
|
divisor(63 downto 32) <= (OTHERS=> divs AND reg_QA(31));
|
divident(63 downto 32) <= (OTHERS=> divs AND reg_QA(31));
|
IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
|
IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
|
divisor(47 downto 16) <= reg_QA;
|
divident(47 downto 16) <= reg_QA;
|
ELSE
|
ELSE
|
divisor(31 downto 0) <= reg_QA;
|
divident(31 downto 0) <= reg_QA;
|
IF exe_opcode(14)='1' AND sndOPC(10)='1' THEN
|
IF exe_opcode(14)='1' AND sndOPC(10)='1' THEN
|
divisor(63 downto 32) <= reg_QB;
|
divident(63 downto 32) <= reg_QB;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF signedOP='1' OR opcode(15)='0' THEN
|
IF signedOP='1' OR opcode(15)='0' THEN
|
OP2outext <= OP2out(31 downto 16);
|
OP2outext <= OP2out(31 downto 16);
|
ELSE
|
ELSE
|
| Line 1221... |
Line 1236... |
IF clkena_lw='1' THEN
|
IF clkena_lw='1' THEN
|
V_Flag <= set_V_Flag;
|
V_Flag <= set_V_Flag;
|
signedOP <= divs;
|
signedOP <= divs;
|
IF micro_state=div1 THEN
|
IF micro_state=div1 THEN
|
nozero <= '0';
|
nozero <= '0';
|
IF divs='1' AND divisor(63)='1' THEN -- Neg divisor
|
IF divs='1' AND divident(63)='1' THEN -- Neg divident
|
OP1_sign <= '1';
|
OP1_sign <= '1';
|
div_reg <= 0-divisor;
|
div_reg <= 0-divident;
|
ELSE
|
ELSE
|
OP1_sign <= '0';
|
OP1_sign <= '0';
|
div_reg <= divisor;
|
div_reg <= divident;
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
div_reg <= div_quot;
|
div_reg <= div_quot;
|
nozero <= NOT div_bit OR nozero;
|
nozero <= NOT div_bit OR nozero;
|
END IF;
|
END IF;
|
