| Line 178... |
Line 178... |
signal index : std_logic_vector(4 downto 0);
|
signal index : std_logic_vector(4 downto 0);
|
-- signal i : integer range 0 to 31;
|
-- signal i : integer range 0 to 31;
|
-- signal i : integer range 0 to 31;
|
-- signal i : integer range 0 to 31;
|
-- signal i : std_logic_vector(5 downto 0);
|
-- signal i : std_logic_vector(5 downto 0);
|
|
|
-- signal hot_bit : std_logic_vector(33 downto 0); simulation error =>
|
signal hot_msb : std_logic_vector(33 downto 0);
|
signal hot_bit : std_logic_vector(63 downto 0);
|
|
signal hot_msb : std_logic_vector(32 downto 0);
|
|
signal vector : std_logic_vector(32 downto 0);
|
signal vector : std_logic_vector(32 downto 0);
|
signal result_bs : std_logic_vector(65 downto 0);
|
signal result_bs : std_logic_vector(65 downto 0);
|
signal bit_nr : std_logic_vector(5 downto 0);
|
signal bit_nr : std_logic_vector(5 downto 0);
|
signal bit_nr7 : std_logic_vector(6 downto 0);
|
|
signal bit_msb : std_logic_vector(5 downto 0);
|
signal bit_msb : std_logic_vector(5 downto 0);
|
signal bs_shift : std_logic_vector(5 downto 0);
|
signal bs_shift : std_logic_vector(5 downto 0);
|
signal bs_shift_mod : std_logic_vector(5 downto 0);
|
signal bs_shift_mod : std_logic_vector(5 downto 0);
|
signal asl_over : std_logic_vector(32 downto 0);
|
signal asl_over : std_logic_vector(32 downto 0);
|
signal asl_over_xor : std_logic_vector(32 downto 0);
|
signal asl_over_xor : std_logic_vector(32 downto 0);
|
| Line 269... |
Line 266... |
OP1in <= bits_out;
|
OP1in <= bits_out;
|
ELSIF exec(opcBF)='1' THEN
|
ELSIF exec(opcBF)='1' THEN
|
OP1in <= bf_datareg; --new bitfieldvector for bfins - for others the old bitfieldvector
|
OP1in <= bf_datareg; --new bitfieldvector for bfins - for others the old bitfieldvector
|
ELSIF exec(opcMOVESR)='1' THEN
|
ELSIF exec(opcMOVESR)='1' THEN
|
OP1in(7 downto 0) <= Flags;
|
OP1in(7 downto 0) <= Flags;
|
-- IF exe_datatype="00" THEN
|
|
IF exe_opcode(9)='1' THEN
|
IF exe_opcode(9)='1' THEN
|
OP1in(15 downto 8) <= "00000000";
|
OP1in(15 downto 8) <= "00000000";
|
ELSE
|
ELSE
|
OP1in(15 downto 8) <= FlagsSR;
|
OP1in(15 downto 8) <= FlagsSR;
|
END IF;
|
END IF;
|
| Line 388... |
Line 384... |
ELSE --opcSBCD
|
ELSE --opcSBCD
|
Vflag_a <= bcd_pur(8) AND NOT bcd_a(7);
|
Vflag_a <= bcd_pur(8) AND NOT bcd_a(7);
|
-- bcd_pur <= ('0'&OP1out(7 downto 0)&'0') - ('0'&OP2out(7 downto 0)&Flags(4));
|
-- bcd_pur <= ('0'&OP1out(7 downto 0)&'0') - ('0'&OP2out(7 downto 0)&Flags(4));
|
bcd_a <= bcd_pur(9 downto 1) - bcd_kor;
|
bcd_a <= bcd_pur(9 downto 1) - bcd_kor;
|
END IF;
|
END IF;
|
Vflag_a <= '0'; --nur zum testen
|
Vflag_a <= '0'; --TG 01.11.2019 only for cputest -- but other behaiver in real 68000 Hardware ??? I must check this later
|
bcd_a_carry <= bcd_pur(9) OR bcd_a(8);
|
bcd_a_carry <= bcd_pur(9) OR bcd_a(8);
|
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Bits
|
-- Bits
|
| Line 494... |
Line 490... |
IF bf_exts='1' AND bf_NFlag='1' THEN
|
IF bf_exts='1' AND bf_NFlag='1' THEN
|
bf_datareg <= datareg OR unshifted_bitmask;
|
bf_datareg <= datareg OR unshifted_bitmask;
|
ELSE
|
ELSE
|
bf_datareg <= datareg;
|
bf_datareg <= datareg;
|
END IF;
|
END IF;
|
-- bf_datareg <= shifted_bitmask(31 downto 4)&"0000";
|
|
-- result(31 downto 0)<=datareg;
|
|
|
|
-- shift bitmask for operation
|
-- shift bitmask for operation
|
IF bf_loffset(4)='1' THEN
|
IF bf_loffset(4)='1' THEN
|
bitmaskmux3 <= unshifted_bitmask(15 downto 0)&unshifted_bitmask(31 downto 16);
|
bitmaskmux3 <= unshifted_bitmask(15 downto 0)&unshifted_bitmask(31 downto 16);
|
ELSE
|
ELSE
|
| Line 713... |
Line 707... |
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Barrel Shifter
|
-- Barrel Shifter
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
process (OP1out, OP2out, opcode, bit_nr, bit_nr7, bit_msb, hot_bit, bs_shift, bs_shift_mod, ring, result_bs, exe_opcode, vector,
|
process (OP1out, OP2out, opcode, bit_nr, bit_msb, bs_shift, bs_shift_mod, ring, result_bs, exe_opcode, vector,
|
rot_bits, Flags, msb, hot_msb, asl_over, asl_over_xor, ALU, asr_sign, exec)
|
rot_bits, Flags, bs_C, msb, hot_msb, asl_over, asl_over_xor, ALU, asr_sign, exec)
|
begin
|
begin
|
ring <= "100000";
|
ring <= "100000";
|
IF rot_bits="10" THEN --ROX L/R
|
IF rot_bits="10" THEN --ROX L/R
|
CASE exe_opcode(7 downto 6) IS
|
CASE exe_opcode(7 downto 6) IS
|
WHEN "00" => --Byte
|
WHEN "00" => --Byte
|
| Line 752... |
Line 746... |
ELSE
|
ELSE
|
bs_shift(5 downto 3) <="000";
|
bs_shift(5 downto 3) <="000";
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
bs_shift_mod <= std_logic_vector(unsigned(bs_shift) rem unsigned(ring));
|
|
|
|
bit_nr <= bs_shift_mod(5 downto 0);
|
|
bit_nr7 <= ('1'&ring)-('0'&bs_shift_mod);
|
|
IF exe_opcode(8)='0' THEN --right shift
|
|
bit_nr <= bit_nr7(5 downto 0);
|
|
END IF;
|
|
IF rot_bits(1)='0' THEN --only shift
|
|
IF unsigned(bs_shift)<33 THEN
|
|
IF exe_opcode(8)='0' THEN --right shift
|
|
bit_nr <= 32-bs_shift;
|
|
ELSE
|
|
bit_nr <= bs_shift;
|
|
END IF;
|
|
ELSE
|
|
bit_nr <= "100001";
|
|
bit_msb <= "000000";
|
|
END IF;
|
|
END IF;
|
|
|
|
|
|
-- calc V-Flag by ASL
|
-- calc V-Flag by ASL
|
|
bit_msb <= "000000";
|
hot_msb <= (OTHERS =>'0');
|
hot_msb <= (OTHERS =>'0');
|
hot_msb(conv_integer(bit_msb)) <= '1';
|
hot_msb(conv_integer(bit_msb)) <= '1';
|
IF bs_shift > ring THEN
|
IF bs_shift < ring THEN
|
bit_msb <= "000000";
|
|
ELSE
|
|
bit_msb <= ring-bs_shift;
|
bit_msb <= ring-bs_shift;
|
END IF;
|
END IF;
|
asl_over_xor <= (('0'&vector(30 downto 0)) XOR ('0'&vector(31 downto 1)))&msb;
|
asl_over_xor <= (('0'&vector(30 downto 0)) XOR ('0'&vector(31 downto 1)))&msb;
|
CASE exe_opcode(7 downto 6) IS
|
CASE exe_opcode(7 downto 6) IS
|
WHEN "00" => --Byte
|
WHEN "00" => --Byte
|
| Line 795... |
Line 767... |
bs_V <= '0';
|
bs_V <= '0';
|
IF rot_bits="00" AND exe_opcode(8)='1' THEN --ASL
|
IF rot_bits="00" AND exe_opcode(8)='1' THEN --ASL
|
bs_V <= not asl_over(32);
|
bs_V <= not asl_over(32);
|
END IF;
|
END IF;
|
|
|
|
bs_X <= bs_C;
|
IF exe_opcode(8)='0' THEN --right shift
|
IF exe_opcode(8)='0' THEN --right shift
|
bs_C <= result_bs(31);
|
bs_C <= result_bs(31);
|
bs_X <= result_bs(31);
|
|
ELSE --left shift
|
ELSE --left shift
|
CASE exe_opcode(7 downto 6) IS
|
CASE exe_opcode(7 downto 6) IS
|
WHEN "00" => --Byte
|
WHEN "00" => --Byte
|
bs_C <= result_bs(8);
|
bs_C <= result_bs(8);
|
bs_X <= result_bs(8);
|
|
WHEN "01"|"11" => --Word
|
WHEN "01"|"11" => --Word
|
bs_C <= result_bs(16);
|
bs_C <= result_bs(16);
|
bs_X <= result_bs(16);
|
|
WHEN "10" => --Long
|
WHEN "10" => --Long
|
bs_C <= result_bs(32);
|
bs_C <= result_bs(32);
|
bs_X <= result_bs(32);
|
|
WHEN OTHERS => NULL;
|
WHEN OTHERS => NULL;
|
END CASE;
|
END CASE;
|
END IF;
|
END IF;
|
|
|
ALU <= (others=>'-');
|
ALU <= (others=>'-');
|
| Line 836... |
Line 805... |
ELSIF rot_bits="10" THEN --ROX L/R
|
ELSIF rot_bits="10" THEN --ROX L/R
|
CASE exe_opcode(7 downto 6) IS
|
CASE exe_opcode(7 downto 6) IS
|
WHEN "00" => --Byte
|
WHEN "00" => --Byte
|
ALU(7 downto 0) <= result_bs(7 downto 0) OR result_bs(16 downto 9);
|
ALU(7 downto 0) <= result_bs(7 downto 0) OR result_bs(16 downto 9);
|
bs_C <= result_bs(8) OR result_bs(17);
|
bs_C <= result_bs(8) OR result_bs(17);
|
bs_X <= result_bs(8) OR result_bs(17);
|
|
WHEN "01"|"11" => --Word
|
WHEN "01"|"11" => --Word
|
ALU(15 downto 0) <= result_bs(15 downto 0) OR result_bs(32 downto 17);
|
ALU(15 downto 0) <= result_bs(15 downto 0) OR result_bs(32 downto 17);
|
bs_C <= result_bs(16) OR result_bs(33);
|
bs_C <= result_bs(16) OR result_bs(33);
|
bs_X <= result_bs(16) OR result_bs(33);
|
|
WHEN "10" => --Long
|
WHEN "10" => --Long
|
ALU <= result_bs(31 downto 0) OR result_bs(64 downto 33);
|
ALU <= result_bs(31 downto 0) OR result_bs(64 downto 33);
|
bs_C <= result_bs(32) OR result_bs(65);
|
bs_C <= result_bs(32) OR result_bs(65);
|
bs_X <= result_bs(32) OR result_bs(65);
|
|
WHEN OTHERS => NULL;
|
WHEN OTHERS => NULL;
|
END CASE;
|
END CASE;
|
ELSE
|
ELSE
|
IF exe_opcode(8)='0' THEN --right shift
|
IF exe_opcode(8)='0' THEN --right shift
|
ALU <= result_bs(63 downto 32);
|
ALU <= result_bs(63 downto 32);
|
| Line 865... |
Line 831... |
END IF;
|
END IF;
|
bs_X <= Flags(4);
|
bs_X <= Flags(4);
|
bs_V <= '0';
|
bs_V <= '0';
|
END IF;
|
END IF;
|
|
|
|
-- calc shift count
|
|
bs_shift_mod <= std_logic_vector(unsigned(bs_shift) rem unsigned(ring));
|
|
bit_nr <= bs_shift_mod(5 downto 0);
|
|
IF exe_opcode(8)='0' THEN --right shift
|
|
bit_nr <= ring-bs_shift_mod;
|
|
END IF;
|
|
IF rot_bits(1)='0' THEN --only shift
|
|
IF exe_opcode(8)='0' THEN --right shift
|
|
bit_nr <= 32-bs_shift_mod;
|
|
END IF;
|
|
IF bs_shift = ring THEN
|
|
IF exe_opcode(8)='0' THEN --right shift
|
|
bit_nr <= 32-ring;
|
|
ELSE
|
|
bit_nr <= ring;
|
|
END IF;
|
|
END IF;
|
|
IF bs_shift > ring THEN
|
|
IF exe_opcode(8)='0' THEN --right shift
|
|
bit_nr <= "000000";
|
|
bs_C <= '0';
|
|
ELSE
|
|
bit_nr <= ring+1;
|
|
END IF;
|
|
END IF;
|
|
END IF;
|
|
|
-- calc ASR sign
|
-- calc ASR sign
|
BSout <= ALU;
|
BSout <= ALU;
|
asr_sign <= (OTHERS =>'0');
|
asr_sign <= (OTHERS =>'0');
|
asr_sign(32 downto 1) <= asr_sign(31 downto 0) OR hot_msb(31 downto 0);
|
asr_sign(32 downto 1) <= asr_sign(31 downto 0) OR hot_msb(31 downto 0);
|
IF rot_bits="00" AND exe_opcode(8)='0' AND msb='1' THEN --ASR
|
IF rot_bits="00" AND exe_opcode(8)='0' AND msb='1' THEN --ASR
|
BSout <= ALU or asr_sign(32 downto 1);
|
BSout <= ALU or asr_sign(32 downto 1);
|
IF bs_shift > ring THEN
|
IF bs_shift > ring THEN
|
bs_C <= '1';
|
bs_C <= '1';
|
bs_X <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
vector(32 downto 0) <= '0'&OP1out;
|
vector(32 downto 0) <= '0'&OP1out;
|
CASE exe_opcode(7 downto 6) IS
|
CASE exe_opcode(7 downto 6) IS
|
| Line 900... |
Line 892... |
IF rot_bits="10" THEN --ROX L/R
|
IF rot_bits="10" THEN --ROX L/R
|
vector(32) <= Flags(4);
|
vector(32) <= Flags(4);
|
END IF;
|
END IF;
|
WHEN OTHERS => NULL;
|
WHEN OTHERS => NULL;
|
END CASE;
|
END CASE;
|
|
result_bs <= std_logic_vector(unsigned('0'&X"00000000"&vector) sll to_integer(unsigned(bit_nr(5 downto 0))));
|
hot_bit <= (OTHERS =>'0');
|
|
hot_bit(conv_integer(bit_nr(5 downto 0))) <= '1';
|
|
result_bs <= vector * hot_bit(32 downto 0);
|
|
-- if you don't like to use the multiplier -> uncommend next line and commend the lines before
|
|
-- result_bs <= std_logic_vector(unsigned('0'&X"00000000"&vector) sll to_integer(unsigned(bit_nr(5 downto 0))));
|
|
|
|
end process;
|
end process;
|
|
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
