| Line 19... |
Line 19... |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
|
-- --
|
-- --
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
|
|
-- 10.11.2019 TG inset TRAPcc
|
-- 25.11.2019 TG bugfix ILLEGAL.B handling
|
|
-- 24.11.2019 TG next try CMP2 and CHK2.l
|
|
-- 24.11.2019 retrofun(RF) commit ILLEGAL.B handling
|
|
-- 18.11.2019 TG insert CMP2 and CHK2.l
|
|
-- 17.11.2019 TG insert CAS and CAS2
|
|
-- 10.11.2019 TG insert TRAPcc
|
-- 08.11.2019 TG bugfix movem in 68020 mode
|
-- 08.11.2019 TG bugfix movem in 68020 mode
|
-- 06.11.2019 TG bugfix CHK
|
-- 06.11.2019 TG bugfix CHK
|
-- 06.11.2019 TG bugfix flags and stackframe DIVU
|
-- 06.11.2019 TG bugfix flags and stackframe DIVU
|
-- 04.11.2019 TG insert RTE from TH
|
-- 04.11.2019 TG insert RTE from TH
|
-- 03.11.2019 TG insert TrapV from TH
|
-- 03.11.2019 TG insert TrapV from TH
|
| Line 63... |
Line 68... |
--
|
--
|
-- to do 68020:
|
-- to do 68020:
|
-- (CALLM)
|
-- (CALLM)
|
-- (RETM)
|
-- (RETM)
|
|
|
-- CAS, CAS2
|
-- bugfix DIVS.W
|
|
-- bugfix CHK2, CMP2
|
|
-- rework barrel shifter
|
-- CHK2
|
-- CHK2
|
-- CMP2
|
-- CMP2
|
-- cpXXX Coprozessor stuff
|
-- cpXXX Coprozessor stuff
|
|
|
-- done 020:
|
-- done 020:
|
|
-- CAS, CAS2
|
-- TRAPcc
|
-- TRAPcc
|
-- PACK
|
-- PACK
|
-- UNPK
|
-- UNPK
|
-- Bitfields
|
-- Bitfields
|
-- address modes
|
-- address modes
|
| Line 198... |
Line 206... |
|
|
signal TG68_PC_brw : bit;
|
signal TG68_PC_brw : bit;
|
signal TG68_PC_word : bit;
|
signal TG68_PC_word : bit;
|
signal getbrief : bit;
|
signal getbrief : bit;
|
signal brief : std_logic_vector(15 downto 0);
|
signal brief : std_logic_vector(15 downto 0);
|
signal dest_areg : std_logic;
|
|
signal source_areg : std_logic;
|
|
signal data_is_source : bit;
|
signal data_is_source : bit;
|
signal store_in_tmp : bit;
|
signal store_in_tmp : bit;
|
signal write_back : bit;
|
signal write_back : bit;
|
signal exec_write_back : bit;
|
signal exec_write_back : bit;
|
signal setstackaddr : bit;
|
signal setstackaddr : bit;
|
| Line 211... |
Line 217... |
signal writePCbig : bit;
|
signal writePCbig : bit;
|
signal set_writePCbig : bit;
|
signal set_writePCbig : bit;
|
signal setopcode : bit;
|
signal setopcode : bit;
|
signal decodeOPC : bit;
|
signal decodeOPC : bit;
|
signal execOPC : bit;
|
signal execOPC : bit;
|
|
signal execOPC_ALU : bit;
|
signal setexecOPC : bit;
|
signal setexecOPC : bit;
|
signal endOPC : bit;
|
signal endOPC : bit;
|
signal setendOPC : bit;
|
signal setendOPC : bit;
|
signal Flags : std_logic_vector(7 downto 0); -- ...XNZVC
|
signal Flags : std_logic_vector(7 downto 0); -- ...XNZVC
|
signal FlagsSR : std_logic_vector(7 downto 0); -- T.S.0III
|
signal FlagsSR : std_logic_vector(7 downto 0); -- T.S.0III
|
| Line 223... |
Line 230... |
signal exec_tas : std_logic;
|
signal exec_tas : std_logic;
|
signal set_exec_tas : std_logic;
|
signal set_exec_tas : std_logic;
|
|
|
signal exe_condition : std_logic;
|
signal exe_condition : std_logic;
|
signal ea_only : bit;
|
signal ea_only : bit;
|
|
signal source_areg : std_logic;
|
signal source_lowbits : bit;
|
signal source_lowbits : bit;
|
|
signal source_LDRLbits : bit;
|
|
signal source_LDRMbits : bit;
|
signal source_2ndHbits : bit;
|
signal source_2ndHbits : bit;
|
|
signal source_2ndMbits : bit;
|
signal source_2ndLbits : bit;
|
signal source_2ndLbits : bit;
|
|
signal dest_areg : std_logic;
|
|
signal dest_LDRareg : std_logic;
|
|
signal dest_LDRHbits : bit;
|
|
signal dest_LDRLbits : bit;
|
signal dest_2ndHbits : bit;
|
signal dest_2ndHbits : bit;
|
|
signal dest_2ndLbits : bit;
|
signal dest_hbits : bit;
|
signal dest_hbits : bit;
|
signal rot_bits : std_logic_vector(1 downto 0);
|
signal rot_bits : std_logic_vector(1 downto 0);
|
signal set_rot_bits : std_logic_vector(1 downto 0);
|
signal set_rot_bits : std_logic_vector(1 downto 0);
|
signal rot_cnt : std_logic_vector(5 downto 0);
|
signal rot_cnt : std_logic_vector(5 downto 0);
|
signal set_rot_cnt : std_logic_vector(5 downto 0);
|
signal set_rot_cnt : std_logic_vector(5 downto 0);
|
| Line 254... |
Line 270... |
signal trap_trace : bit;
|
signal trap_trace : bit;
|
signal trap_1010 : bit;
|
signal trap_1010 : bit;
|
signal trap_1111 : bit;
|
signal trap_1111 : bit;
|
signal trap_trap : bit;
|
signal trap_trap : bit;
|
signal trap_trapv : bit;
|
signal trap_trapv : bit;
|
signal trap_trapcc : bit;
|
|
signal trap_interrupt : bit;
|
signal trap_interrupt : bit;
|
signal trapmake : bit;
|
signal trapmake : bit;
|
signal trapd : bit;
|
signal trapd : bit;
|
signal trap_SR : std_logic_vector(7 downto 0);
|
signal trap_SR : std_logic_vector(7 downto 0);
|
signal make_trace : std_logic;
|
signal make_trace : std_logic;
|
| Line 347... |
Line 362... |
BarrelShifter => BarrelShifter --0=>no, 1=>yes, 2=>switchable with CPU(1)
|
BarrelShifter => BarrelShifter --0=>no, 1=>yes, 2=>switchable with CPU(1)
|
)
|
)
|
port map(
|
port map(
|
clk => clk, --: in std_logic;
|
clk => clk, --: in std_logic;
|
Reset => Reset, --: in std_logic;
|
Reset => Reset, --: in std_logic;
|
|
CPU => CPU, --: in std_logic_vector(1 downto 0):="00"; -- 00->68000 01->68010 11->68020(only some parts - yet)
|
clkena_lw => clkena_lw, --: in std_logic:='1';
|
clkena_lw => clkena_lw, --: in std_logic:='1';
|
execOPC => execOPC, --: in bit;
|
execOPC => execOPC_ALU, --: in bit;
|
decodeOPC => decodeOPC, --: in bit;
|
decodeOPC => decodeOPC, --: in bit;
|
exe_condition => exe_condition, --: in std_logic;
|
exe_condition => exe_condition, --: in std_logic;
|
exec_tas => exec_tas, --: in std_logic;
|
exec_tas => exec_tas, --: in std_logic;
|
long_start => long_start_alu, --: in bit;
|
long_start => long_start_alu, --: in bit;
|
non_aligned => non_aligned,
|
non_aligned => non_aligned,
|
| Line 387... |
Line 403... |
addsub_q => addsub_q, --: buffer std_logic_vector(31 downto 0);
|
addsub_q => addsub_q, --: buffer std_logic_vector(31 downto 0);
|
ALUout => ALUout --: buffer std_logic_vector(31 downto 0)
|
ALUout => ALUout --: buffer std_logic_vector(31 downto 0)
|
);
|
);
|
|
|
long_start_alu <= to_bit(NOT memmaskmux(3));
|
long_start_alu <= to_bit(NOT memmaskmux(3));
|
|
execOPC_ALU <= execOPC OR exec(alu_exec);
|
process (memmaskmux)
|
process (memmaskmux)
|
begin
|
begin
|
non_aligned <= '0';
|
non_aligned <= '0';
|
if (memmaskmux(5 downto 4) = "01") or (memmaskmux(5 downto 4) = "10") then
|
if (memmaskmux(5 downto 4) = "01") or (memmaskmux(5 downto 4) = "10") then
|
non_aligned <= '1';
|
non_aligned <= '1';
|
| Line 579... |
Line 595... |
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- set dest regaddr
|
-- set dest regaddr
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (opcode, rf_source_addrd, brief, setstackaddr, dest_hbits, dest_areg, data_is_source, sndOPC, exec, set, dest_2ndHbits)
|
PROCESS (opcode, rf_source_addrd, brief, setstackaddr, dest_hbits, dest_areg, dest_LDRareg, data_is_source, sndOPC, exec, set, dest_2ndHbits, dest_2ndLbits, dest_LDRHbits, dest_LDRLbits, last_data_read)
|
BEGIN
|
BEGIN
|
IF exec(movem_action) ='1' THEN
|
IF exec(movem_action) ='1' THEN
|
rf_dest_addr <= rf_source_addrd;
|
rf_dest_addr <= rf_source_addrd;
|
ELSIF set(briefext)='1' THEN
|
ELSIF set(briefext)='1' THEN
|
rf_dest_addr <= brief(15 downto 12);
|
rf_dest_addr <= brief(15 downto 12);
|
| Line 592... |
Line 608... |
rf_dest_addr <= '0'&sndOPC(8 downto 6);
|
rf_dest_addr <= '0'&sndOPC(8 downto 6);
|
-- ELSE
|
-- ELSE
|
-- rf_dest_addr <= sndOPC(9 downto 6);
|
-- rf_dest_addr <= sndOPC(9 downto 6);
|
-- END IF;
|
-- END IF;
|
ELSIF dest_2ndHbits='1' THEN
|
ELSIF dest_2ndHbits='1' THEN
|
rf_dest_addr <= '0'&sndOPC(14 downto 12);
|
rf_dest_addr <= dest_LDRareg&sndOPC(14 downto 12);
|
ELSIF set(write_reminder)='1' THEN
|
ELSIF dest_LDRHbits='1' THEN
|
|
rf_dest_addr <= last_data_read(15 downto 12);
|
|
ELSIF dest_LDRLbits='1' THEN
|
|
rf_dest_addr <= '0'&last_data_read(2 downto 0);
|
|
ELSIF dest_2ndLbits='1' THEN
|
rf_dest_addr <= '0'&sndOPC(2 downto 0);
|
rf_dest_addr <= '0'&sndOPC(2 downto 0);
|
ELSIF setstackaddr='1' THEN
|
ELSIF setstackaddr='1' THEN
|
rf_dest_addr <= "1111";
|
rf_dest_addr <= "1111";
|
ELSIF dest_hbits='1' THEN
|
ELSIF dest_hbits='1' THEN
|
rf_dest_addr <= dest_areg&opcode(11 downto 9);
|
rf_dest_addr <= dest_areg&opcode(11 downto 9);
|
| Line 611... |
Line 631... |
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- set source regaddr
|
-- set source regaddr
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (opcode, movem_presub, movem_regaddr, source_lowbits, source_areg, sndOPC, exec, set, source_2ndLbits, source_2ndHbits)
|
PROCESS (opcode, movem_presub, movem_regaddr, source_lowbits, source_areg, sndOPC, exec, set, source_2ndLbits, source_2ndHbits, source_LDRLbits, source_LDRMbits, last_data_read, source_2ndMbits)
|
BEGIN
|
BEGIN
|
IF exec(movem_action)='1' OR set(movem_action) ='1' THEN
|
IF exec(movem_action)='1' OR set(movem_action) ='1' THEN
|
IF movem_presub='1' THEN
|
IF movem_presub='1' THEN
|
rf_source_addr <= movem_regaddr XOR "1111";
|
rf_source_addr <= movem_regaddr XOR "1111";
|
ELSE
|
ELSE
|
| Line 623... |
Line 643... |
END IF;
|
END IF;
|
ELSIF source_2ndLbits='1' THEN
|
ELSIF source_2ndLbits='1' THEN
|
rf_source_addr <= '0'&sndOPC(2 downto 0);
|
rf_source_addr <= '0'&sndOPC(2 downto 0);
|
ELSIF source_2ndHbits='1' THEN
|
ELSIF source_2ndHbits='1' THEN
|
rf_source_addr <= '0'&sndOPC(14 downto 12);
|
rf_source_addr <= '0'&sndOPC(14 downto 12);
|
|
ELSIF source_2ndMbits='1' THEN
|
|
rf_source_addr <= '0'&sndOPC(8 downto 6);
|
|
ELSIF source_LDRLbits='1' THEN
|
|
rf_source_addr <= '0'&last_data_read(2 downto 0);
|
|
ELSIF source_LDRMbits='1' THEN
|
|
rf_source_addr <= '0'&last_data_read(8 downto 6);
|
ELSIF source_lowbits='1' THEN
|
ELSIF source_lowbits='1' THEN
|
rf_source_addr <= source_areg&opcode(2 downto 0);
|
rf_source_addr <= source_areg&opcode(2 downto 0);
|
ELSIF exec(linksp)='1' THEN
|
ELSIF exec(linksp)='1' THEN
|
rf_source_addr <= "1111";
|
rf_source_addr <= "1111";
|
ELSE
|
ELSE
|
| Line 657... |
Line 683... |
BEGIN
|
BEGIN
|
OP2out(15 downto 0) <= reg_QB(15 downto 0);
|
OP2out(15 downto 0) <= reg_QB(15 downto 0);
|
OP2out(31 downto 16) <= (OTHERS => OP2out(15));
|
OP2out(31 downto 16) <= (OTHERS => OP2out(15));
|
IF exec(OP2out_one)='1' THEN
|
IF exec(OP2out_one)='1' THEN
|
OP2out(15 downto 0) <= "1111111111111111";
|
OP2out(15 downto 0) <= "1111111111111111";
|
ELSIF exec(opcEXT)='1' THEN
|
|
IF exe_opcode(6)='0' OR exe_opcode(8)='1' THEN --ext.w
|
|
OP2out(15 downto 8) <= (OTHERS => OP2out(7));
|
|
END IF;
|
|
ELSIF use_direct_data='1' OR (exec(exg)='1' AND execOPC='1') OR exec(get_bfoffset)='1' THEN
|
ELSIF use_direct_data='1' OR (exec(exg)='1' AND execOPC='1') OR exec(get_bfoffset)='1' THEN
|
OP2out <= data_write_tmp;
|
OP2out <= data_write_tmp;
|
ELSIF (exec(ea_data_OP1)='0' AND store_in_tmp='1') OR exec(ea_data_OP2)='1' THEN
|
ELSIF (exec(ea_data_OP1)='0' AND store_in_tmp='1') OR exec(ea_data_OP2)='1' THEN
|
OP2out <= ea_data;
|
OP2out <= ea_data;
|
ELSIF exec(opcMOVEQ)='1' THEN
|
ELSIF exec(opcMOVEQ)='1' THEN
|
| Line 676... |
Line 698... |
OP2out(3) <='1';
|
OP2out(3) <='1';
|
ELSE
|
ELSE
|
OP2out(3) <='0';
|
OP2out(3) <='0';
|
END IF;
|
END IF;
|
OP2out(15 downto 4) <= (OTHERS => '0');
|
OP2out(15 downto 4) <= (OTHERS => '0');
|
ELSIF exe_datatype="10" THEN
|
ELSIF exe_datatype="10" AND exec(opcEXT)='0' THEN
|
OP2out(31 downto 16) <= reg_QB(31 downto 16);
|
OP2out(31 downto 16) <= reg_QB(31 downto 16);
|
END IF;
|
END IF;
|
|
IF exec(opcEXTB)='1' THEN
|
|
OP2out(31 downto 8) <= (OTHERS => OP2out(7));
|
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- handle EA_data, data_write
|
-- handle EA_data, data_write
|
| Line 690... |
Line 715... |
PROCESS (clk)
|
PROCESS (clk)
|
BEGIN
|
BEGIN
|
IF rising_edge(clk) THEN
|
IF rising_edge(clk) THEN
|
IF Reset = '1' THEN
|
IF Reset = '1' THEN
|
store_in_tmp <='0';
|
store_in_tmp <='0';
|
exec_write_back <= '0';
|
|
direct_data <= '0';
|
direct_data <= '0';
|
use_direct_data <= '0';
|
use_direct_data <= '0';
|
Z_error <= '0';
|
Z_error <= '0';
|
ELSIF clkena_lw='1' THEN
|
ELSIF clkena_lw='1' THEN
|
useStackframe2<='0';
|
useStackframe2<='0';
|
direct_data <= '0';
|
direct_data <= '0';
|
IF state="11" THEN
|
|
exec_write_back <= '0';
|
|
ELSIF setstate="10" AND write_back='1' THEN
|
|
-- ELSIF setstate = "10" AND write_back = '1' AND next_micro_state = idle THEN --this shut be a fix for pinball
|
|
-- --but it destory pack -(ax),-(ay) and unpack
|
|
exec_write_back <= '1';
|
|
END IF;
|
|
|
|
IF exec(hold_OP2)='1' THEN
|
IF exec(hold_OP2)='1' THEN
|
use_direct_data <= '1';
|
use_direct_data <= '1';
|
END IF;
|
END IF;
|
IF set_direct_data='1' THEN
|
IF set_direct_data='1' THEN
|
direct_data <= '1';
|
direct_data <= '1';
|
use_direct_data <= '1';
|
use_direct_data <= '1';
|
ELSIF endOPC='1' THEN
|
ELSIF endOPC='1' OR set(ea_data_OP2)='1' THEN
|
use_direct_data <= '0';
|
use_direct_data <= '0';
|
END IF;
|
END IF;
|
exec_DIRECT <= set_exec(opcMOVE);
|
exec_DIRECT <= set_exec(opcMOVE);
|
|
|
IF endOPC='1' THEN
|
IF endOPC='1' THEN
|
| Line 898... |
Line 914... |
tmp_TG68_PC <= addr;
|
tmp_TG68_PC <= addr;
|
END IF;
|
END IF;
|
use_base <= '0';
|
use_base <= '0';
|
IF memmaskmux(3)='0' OR exec(mem_addsub)='1' THEN
|
IF memmaskmux(3)='0' OR exec(mem_addsub)='1' THEN
|
memaddr_delta <= addsub_q;
|
memaddr_delta <= addsub_q;
|
ELSIF state="01" AND exec_write_back='1' THEN
|
ELSIF set(restore_ADDR)='1' THEN
|
memaddr_delta <= tmp_TG68_PC;
|
memaddr_delta <= tmp_TG68_PC;
|
ELSIF exec(direct_delta)='1' THEN
|
ELSIF exec(direct_delta)='1' THEN
|
memaddr_delta <= data_read;
|
memaddr_delta <= data_read;
|
ELSIF exec(ea_to_pc)='1' AND setstate="00" THEN
|
ELSIF exec(ea_to_pc)='1' AND setstate="00" THEN
|
memaddr_delta <= addr;
|
memaddr_delta <= addr;
|
| Line 943... |
Line 959... |
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- PC Calc + fetch opcode
|
-- PC Calc + fetch opcode
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro_state, stop, make_trace, make_berr, IPL_nr, FlagsSR, set_rot_cnt, opcode, writePCbig, set_exec, exec,
|
PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro_state, stop, make_trace, make_berr, IPL_nr, FlagsSR, set_rot_cnt, opcode, writePCbig, set_exec, exec,
|
PC_dataa, PC_datab, setnextpass, last_data_read, TG68_PC_brw, TG68_PC_word, Z_error, trap_trap, trap_trapv, trap_trapcc, interrupt, tmp_TG68_PC, TG68_PC)
|
PC_dataa, PC_datab, setnextpass, last_data_read, TG68_PC_brw, TG68_PC_word, Z_error, trap_trap, trap_trapv, interrupt, tmp_TG68_PC, TG68_PC)
|
BEGIN
|
BEGIN
|
|
|
PC_dataa <= TG68_PC;
|
PC_dataa <= TG68_PC;
|
IF TG68_PC_brw = '1' THEN
|
IF TG68_PC_brw = '1' THEN
|
PC_dataa <= tmp_TG68_PC;
|
PC_dataa <= tmp_TG68_PC;
|
| Line 1011... |
Line 1027... |
TG68_PC <= X"00000004";
|
TG68_PC <= X"00000004";
|
decodeOPC <= '0';
|
decodeOPC <= '0';
|
endOPC <= '0';
|
endOPC <= '0';
|
TG68_PC_word <= '0';
|
TG68_PC_word <= '0';
|
execOPC <= '0';
|
execOPC <= '0';
|
|
-- execOPC_ALU <= '0';
|
stop <= '0';
|
stop <= '0';
|
rot_cnt <="000001";
|
rot_cnt <="000001";
|
-- byte <= '0';
|
-- byte <= '0';
|
-- IPL_nr <= "000";
|
-- IPL_nr <= "000";
|
trap_trace <= '0';
|
trap_trace <= '0';
|
| Line 1022... |
Line 1039... |
writePCbig <= '0';
|
writePCbig <= '0';
|
-- recall_last <= '0';
|
-- recall_last <= '0';
|
Suppress_Base <= '0';
|
Suppress_Base <= '0';
|
make_berr <= '0';
|
make_berr <= '0';
|
memmask <= "111111";
|
memmask <= "111111";
|
|
exec_write_back <= '0';
|
ELSE
|
ELSE
|
-- IPL_nr <= NOT IPL;
|
-- IPL_nr <= NOT IPL;
|
IF clkena_in='1' THEN
|
IF clkena_in='1' THEN
|
memmask <= memmask(3 downto 0)&"11";
|
memmask <= memmask(3 downto 0)&"11";
|
memread <= memread(1 downto 0)&memmaskmux(5 downto 4);
|
memread <= memread(1 downto 0)&memmaskmux(5 downto 4);
|
| Line 1043... |
Line 1061... |
IF clkena_lw='1' THEN
|
IF clkena_lw='1' THEN
|
interrupt <= setinterrupt;
|
interrupt <= setinterrupt;
|
decodeOPC <= setopcode;
|
decodeOPC <= setopcode;
|
endOPC <= setendOPC;
|
endOPC <= setendOPC;
|
execOPC <= setexecOPC;
|
execOPC <= setexecOPC;
|
|
-- IF setexecOPC='1' OR set(alu_exec)='1' THEN
|
|
-- execOPC_ALU <= '1';
|
|
-- ELSE
|
|
-- execOPC_ALU <= '0';
|
|
-- END IF;
|
|
|
exe_datatype <= set_datatype;
|
exe_datatype <= set_datatype;
|
exe_opcode <= opcode;
|
exe_opcode <= opcode;
|
|
|
if(trap_berr='0') then
|
if(trap_berr='0') then
|
| Line 1098... |
Line 1121... |
FC(1) <= NOT setstate(1) OR (PCbase AND NOT setstate(0));
|
FC(1) <= NOT setstate(1) OR (PCbase AND NOT setstate(0));
|
FC(0) <= setstate(1) AND (NOT PCbase OR setstate(0));
|
FC(0) <= setstate(1) AND (NOT PCbase OR setstate(0));
|
IF interrupt='1' THEN
|
IF interrupt='1' THEN
|
FC(1 downto 0) <= "11";
|
FC(1 downto 0) <= "11";
|
END IF;
|
END IF;
|
|
|
|
IF state="11" THEN
|
|
exec_write_back <= '0';
|
|
ELSIF setstate="10" AND write_back='1' THEN
|
|
exec_write_back <= '1';
|
|
END IF;
|
IF (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR (stop='1' AND interrupt='0') OR set_exec(opcCHK)='1' THEN
|
IF (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR (stop='1' AND interrupt='0') OR set_exec(opcCHK)='1' THEN
|
state <= "01";
|
state <= "01";
|
memmask <= "111111";
|
memmask <= "111111";
|
ELSIF execOPC='1' AND exec_write_back='1' THEN
|
ELSIF execOPC='1' AND exec_write_back='1' THEN
|
state <= "11";
|
state <= "11";
|
| Line 1175... |
Line 1204... |
IF setnextpass='1' OR regdirectsource='1' THEN
|
IF setnextpass='1' OR regdirectsource='1' THEN
|
nextpass <= '1';
|
nextpass <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
-- why do not I need this ??? What are the immediate data for ???
|
|
-- IF trap_trapcc='1' THEN
|
|
-- IF opcode(2 downto 0)="100" THEN
|
|
-- exe_pc <= (others => '0');
|
|
-- ELSE
|
|
-- exe_pc <= last_data_read;
|
|
-- END IF;
|
|
-- END IF;
|
|
|
|
IF decodeOPC='1' OR interrupt='1' THEN
|
IF decodeOPC='1' OR interrupt='1' THEN
|
trap_SR <= FlagsSR;
|
trap_SR <= FlagsSR;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
| Line 1202... |
Line 1222... |
PCbase <= '0';
|
PCbase <= '0';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF clkena_lw='1' THEN
|
IF clkena_lw='1' THEN
|
exec <= set;
|
exec <= set;
|
|
exec(alu_move) <= set(opcMOVE) OR set(alu_move);
|
|
exec(alu_setFlags) <= set(opcADD) OR set(alu_setFlags);
|
exec_tas <= '0';
|
exec_tas <= '0';
|
exec(subidx) <= set(presub) or set(subidx);
|
exec(subidx) <= set(presub) or set(subidx);
|
IF setexecOPC='1' THEN
|
IF setexecOPC='1' THEN
|
exec <= set_exec OR set;
|
exec <= set_exec OR set;
|
|
exec(alu_move) <= set_exec(opcMOVE) OR set(opcMOVE) OR set(alu_move);
|
|
exec(alu_setFlags) <= set_exec(opcADD) OR set(opcADD) OR set(alu_setFlags);
|
exec_tas <= set_exec_tas;
|
exec_tas <= set_exec_tas;
|
END IF;
|
END IF;
|
exec(get_2ndOPC) <= set(get_2ndOPC) OR setopcode;
|
exec(get_2ndOPC) <= set(get_2ndOPC) OR setopcode;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
| Line 1340... |
Line 1364... |
END IF;
|
END IF;
|
IF interrupt='1' THEN
|
IF interrupt='1' THEN
|
FC(2) <= '1';
|
FC(2) <= '1';
|
END IF;
|
END IF;
|
IF cpu(1)='0' THEN
|
IF cpu(1)='0' THEN
|
|
FlagsSR(4) <= '0';
|
FlagsSR(6) <= '0';
|
FlagsSR(6) <= '0';
|
END IF;
|
END IF;
|
FlagsSR(3) <= '0';
|
FlagsSR(3) <= '0';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
| Line 1353... |
Line 1378... |
-- decode opcode
|
-- decode opcode
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, decodeOPC, state, setexecOPC, Flags, FlagsSR, direct_data, build_logical,
|
PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, decodeOPC, state, setexecOPC, Flags, FlagsSR, direct_data, build_logical,
|
build_bcd, set_Z_error, trapd, movem_run, last_data_read, set, set_V_Flag, z_error, trap_trace, trap_interrupt,
|
build_bcd, set_Z_error, trapd, movem_run, last_data_read, set, set_V_Flag, z_error, trap_trace, trap_interrupt,
|
SVmode, preSVmode, stop, long_done, ea_only, setstate, execOPC, exec_write_back, exe_datatype,
|
SVmode, preSVmode, stop, long_done, ea_only, setstate, execOPC, exec_write_back, exe_datatype,
|
datatype, interrupt, c_out, trapmake, rot_cnt, brief, addr, trap_trapv, trap_trapcc, last_data_in, use_VBR_Stackframe,
|
datatype, interrupt, c_out, trapmake, rot_cnt, brief, addr, trap_trapv, last_data_in, use_VBR_Stackframe,
|
long_start, set_datatype, sndOPC, set_exec, exec, ea_build_now, reg_QA, reg_QB, make_berr, trap_berr)
|
long_start, set_datatype, sndOPC, set_exec, exec, ea_build_now, reg_QA, reg_QB, make_berr, trap_berr)
|
BEGIN
|
BEGIN
|
TG68_PC_brw <= '0';
|
TG68_PC_brw <= '0';
|
setstate <= "00";
|
setstate <= "00";
|
Regwrena_now <= '0';
|
Regwrena_now <= '0';
|
| Line 1365... |
Line 1390... |
setnextpass <= '0';
|
setnextpass <= '0';
|
regdirectsource <= '0';
|
regdirectsource <= '0';
|
setdisp <= '0';
|
setdisp <= '0';
|
setdispbyte <= '0';
|
setdispbyte <= '0';
|
getbrief <= '0';
|
getbrief <= '0';
|
|
dest_LDRareg <= '0';
|
dest_areg <= '0';
|
dest_areg <= '0';
|
source_areg <= '0';
|
source_areg <= '0';
|
data_is_source <= '0';
|
data_is_source <= '0';
|
write_back <= '0';
|
write_back <= '0';
|
setstackaddr <= '0';
|
setstackaddr <= '0';
|
| Line 1377... |
Line 1403... |
-- set_rot_bits <= "00";
|
-- set_rot_bits <= "00";
|
set_rot_bits <= opcode(4 downto 3);
|
set_rot_bits <= opcode(4 downto 3);
|
set_rot_cnt <= "000001";
|
set_rot_cnt <= "000001";
|
dest_hbits <= '0';
|
dest_hbits <= '0';
|
source_lowbits <= '0';
|
source_lowbits <= '0';
|
|
source_LDRLbits <= '0';
|
|
source_LDRMbits <= '0';
|
source_2ndHbits <= '0';
|
source_2ndHbits <= '0';
|
|
source_2ndMbits <= '0';
|
source_2ndLbits <= '0';
|
source_2ndLbits <= '0';
|
|
dest_LDRHbits <= '0';
|
|
dest_LDRLbits <= '0';
|
dest_2ndHbits <= '0';
|
dest_2ndHbits <= '0';
|
|
dest_2ndLbits <= '0';
|
ea_only <= '0';
|
ea_only <= '0';
|
set_direct_data <= '0';
|
set_direct_data <= '0';
|
set_exec_tas <= '0';
|
set_exec_tas <= '0';
|
trap_illegal <='0';
|
trap_illegal <='0';
|
trap_addr_error <= '0';
|
trap_addr_error <= '0';
|
trap_priv <='0';
|
trap_priv <='0';
|
trap_1010 <='0';
|
trap_1010 <='0';
|
trap_1111 <='0';
|
trap_1111 <='0';
|
trap_trap <='0';
|
trap_trap <='0';
|
trap_trapv <= '0';
|
trap_trapv <= '0';
|
trap_trapcc <= '0';
|
|
trapmake <='0';
|
trapmake <='0';
|
set_vectoraddr <='0';
|
set_vectoraddr <='0';
|
writeSR <= '0';
|
writeSR <= '0';
|
set_stop <= '0';
|
set_stop <= '0';
|
-- illegal_write_mode <= '0';
|
-- illegal_write_mode <= '0';
|
| Line 1427... |
Line 1458... |
WHEN "00" => datatype <= "00"; --Byte
|
WHEN "00" => datatype <= "00"; --Byte
|
WHEN "01" => datatype <= "01"; --Word
|
WHEN "01" => datatype <= "01"; --Word
|
WHEN OTHERS => datatype <= "10"; --Long
|
WHEN OTHERS => datatype <= "10"; --Long
|
END CASE;
|
END CASE;
|
|
|
|
IF execOPC='1' AND exec_write_back='1' THEN
|
|
set(restore_ADDR) <= '1';
|
|
END IF;
|
|
|
IF interrupt='1' AND trap_berr='1' THEN
|
IF interrupt='1' AND trap_berr='1' THEN
|
next_micro_state <= trap0;
|
next_micro_state <= trap0;
|
IF preSVmode='0' THEN
|
IF preSVmode='0' THEN
|
set(changeMode) <= '1';
|
set(changeMode) <= '1';
|
END IF;
|
END IF;
|
setstate <= "01";
|
setstate <= "01";
|
END IF;
|
END IF;
|
IF trapmake='1' AND trapd='0' THEN
|
IF trapmake='1' AND trapd='0' THEN
|
IF use_VBR_Stackframe='1' AND (trap_trapv='1' OR set_Z_error='1' OR exec(opcCHK)='1') THEN
|
-- IF use_VBR_Stackframe='1' AND (trap_trapv='1' OR set_Z_error='1' OR exec(opcCHK)='1') THEN
|
|
IF use_VBR_Stackframe='1' AND (trap_trapv='1' OR set_Z_error='1' OR exec(trap_chk)='1') THEN
|
next_micro_state <= trap00;
|
next_micro_state <= trap00;
|
else
|
else
|
next_micro_state <= trap0;
|
next_micro_state <= trap0;
|
end if;
|
end if;
|
IF use_VBR_Stackframe='0' THEN
|
IF use_VBR_Stackframe='0' THEN
|
| Line 1554... |
Line 1590... |
END CASE;
|
END CASE;
|
WHEN OTHERS => NULL;
|
WHEN OTHERS => NULL;
|
END CASE;
|
END CASE;
|
END IF;
|
END IF;
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
--prepere opcode
|
--prepare opcode
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
CASE opcode(15 downto 12) IS
|
CASE opcode(15 downto 12) IS
|
-- 0000 ----------------------------------------------------------------------------
|
-- 0000 ----------------------------------------------------------------------------
|
WHEN "0000" =>
|
WHEN "0000" =>
|
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
|
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
|
| Line 1582... |
Line 1618... |
IF setexecOPC='1' THEN
|
IF setexecOPC='1' THEN
|
dest_hbits <='1';
|
dest_hbits <='1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
IF opcode(8)='1' OR opcode(11 downto 9)="100" THEN --Bits
|
IF opcode(8)='1' OR opcode(11 downto 9)="100" THEN --Bits
|
|
IF opcode(5 downto 3)/="001" AND --ea An illegal mode
|
|
(opcode(8 downto 3)/="000111" OR opcode(2)='0') AND --BTST bit number static illegal modes
|
|
(opcode(8 downto 2)/="1001111" OR opcode(1 downto 0)="00") AND --BTST bit number dynamic illegal modes
|
|
(opcode(7 downto 6)="00" OR opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN --BCHG, BCLR, BSET illegal modes
|
set_exec(opcBITS) <= '1';
|
set_exec(opcBITS) <= '1';
|
set_exec(ea_data_OP1) <= '1';
|
set_exec(ea_data_OP1) <= '1';
|
IF opcode(7 downto 6)/="00" THEN
|
IF opcode(7 downto 6)/="00" THEN
|
IF opcode(5 downto 4)="00" THEN
|
IF opcode(5 downto 4)="00" THEN
|
set_exec(Regwrena) <= '1';
|
set_exec(Regwrena) <= '1';
|
| Line 1604... |
Line 1644... |
set(ea_build) <= '1';
|
set(ea_build) <= '1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
ea_build_now <= '1';
|
ea_build_now <= '1';
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
ELSIF opcode(8 downto 6)="011" THEN --CAS/CAS2/CMP2/CHK2
|
|
IF cpu(1)='1' THEN
|
|
IF opcode(11)='1' THEN --CAS/CAS2
|
|
IF (opcode(10 downto 9)/="00" AND --CAS illegal size
|
|
opcode(5 downto 4)/="00" AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00")) OR --ea illegal modes
|
|
(opcode(10)='1' AND opcode(5 downto 0)="111100") THEN --CAS2
|
|
CASE opcode(10 downto 9) IS
|
|
WHEN "01" => datatype <= "00"; --Byte
|
|
WHEN "10" => datatype <= "01"; --Word
|
|
WHEN OTHERS => datatype <= "10"; --Long
|
|
END CASE;
|
|
IF opcode(10)='1' AND opcode(5 downto 0)="111100" THEN --CAS2
|
|
IF decodeOPC='1' THEN
|
|
set(get_2ndOPC) <= '1';
|
|
next_micro_state <= cas21;
|
|
END IF;
|
|
ELSE --CAS
|
|
IF decodeOPC='1' THEN
|
|
next_micro_state <= nop;
|
|
set(get_2ndOPC) <= '1';
|
|
set(ea_build) <= '1';
|
|
END IF;
|
|
IF micro_state=idle AND nextpass='1' THEN
|
|
source_2ndLbits <= '1';
|
|
set(ea_data_OP1) <= '1';
|
|
set(addsub) <= '1';
|
|
set(alu_exec) <= '1';
|
|
set(alu_setFlags) <= '1';
|
|
setstate <= "01";
|
|
next_micro_state <= cas1;
|
|
END IF;
|
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
ELSE --CMP2/CHK2
|
|
IF opcode(10 downto 9)/="11" AND --illegal size
|
|
opcode(5 downto 4)/="00" AND opcode(5 downto 3)/="011" AND opcode(5 downto 3)/="100" AND opcode(5 downto 2)/="1111" THEN --ea illegal modes
|
|
set(trap_chk) <= '1';
|
|
datatype <= opcode(10 downto 9);
|
|
IF decodeOPC='1' THEN
|
|
next_micro_state <= nop;
|
|
set(get_2ndOPC) <= '1';
|
|
set(ea_build) <= '1';
|
|
END IF;
|
|
IF set(get_ea_now)='1' THEN
|
|
set(mem_addsub) <= '1';
|
|
set(OP1addr) <= '1';
|
|
END IF;
|
|
IF micro_state=idle AND nextpass='1' THEN
|
|
setstate <= "10";
|
|
set(hold_OP2) <='1';
|
|
next_micro_state <= chk20;
|
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
ELSIF opcode(11 downto 9)="111" THEN --MOVES not in 68000
|
ELSIF opcode(11 downto 9)="111" THEN --MOVES not in 68000
|
|
IF cpu(0)='1' AND opcode(7 downto 6)/="11" AND opcode(5 downto 4)/="00" AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN
|
|
IF SVmode='1' THEN
|
|
--TODO: implement MOVES
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
-- trap_addr_error <= '1';
|
|
trapmake <= '1';
|
trapmake <= '1';
|
|
ELSE
|
|
trap_priv <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
ELSE --andi, ...xxxi
|
ELSE --andi, ...xxxi
|
|
IF opcode(7 downto 6)/="11" AND opcode(5 downto 3)/="001" THEN --ea An illegal mode
|
IF opcode(11 downto 9)="000" THEN --ORI
|
IF opcode(11 downto 9)="000" THEN --ORI
|
|
IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" OR opcode(2 downto 0)="100" THEN
|
set_exec(opcOR) <= '1';
|
set_exec(opcOR) <= '1';
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
IF opcode(11 downto 9)="001" THEN --ANDI
|
IF opcode(11 downto 9)="001" THEN --ANDI
|
|
IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" OR opcode(2 downto 0)="100" THEN
|
set_exec(opcAND) <= '1';
|
set_exec(opcAND) <= '1';
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
IF opcode(11 downto 9)="010" OR opcode(11 downto 9)="011" THEN --SUBI, ADDI
|
IF opcode(11 downto 9)="010" OR opcode(11 downto 9)="011" THEN --SUBI, ADDI
|
|
IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" THEN
|
set_exec(opcADD) <= '1';
|
set_exec(opcADD) <= '1';
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
IF opcode(11 downto 9)="101" THEN --EORI
|
IF opcode(11 downto 9)="101" THEN --EORI
|
|
IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" OR opcode(2 downto 0)="100" THEN
|
set_exec(opcEOR) <= '1';
|
set_exec(opcEOR) <= '1';
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
IF opcode(11 downto 9)="110" THEN --CMPI
|
IF opcode(11 downto 9)="110" THEN --CMPI
|
|
IF opcode(5 downto 3)/="111" OR opcode(2)='0' THEN
|
set_exec(opcCMP) <= '1';
|
set_exec(opcCMP) <= '1';
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
|
IF (set_exec(opcor) OR set_exec(opcand) OR set_exec(opcADD) OR set_exec(opcEor) OR set_exec(opcCMP))='1' THEN
|
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec(opcAND) OR set_exec(opcOR) OR set_exec(opcEOR))='1' THEN --SR
|
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec(opcAND) OR set_exec(opcOR) OR set_exec(opcEOR))='1' THEN --SR
|
IF decodeOPC='1' AND SVmode='0' AND opcode(6)='1' THEN --SR
|
IF decodeOPC='1' AND SVmode='0' AND opcode(6)='1' THEN --SR
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
ELSE
|
ELSE
|
| Line 1642... |
Line 1787... |
set(oriSR) <= set_exec(opcOR);
|
set(oriSR) <= set_exec(opcOR);
|
setstate <= "01";
|
setstate <= "01";
|
next_micro_state <= nopnop;
|
next_micro_state <= nopnop;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
ELSE
|
ELSIF opcode(7)='0' OR opcode(5 downto 0)/="111100" OR (set_exec(opcand) OR set_exec(opcor) OR set_exec(opcEor))='0' THEN
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
next_micro_state <= andi;
|
next_micro_state <= andi;
|
set(get_2ndOPC) <='1';
|
set(get_2ndOPC) <='1';
|
set(ea_build) <= '1';
|
set(ea_build) <= '1';
|
set_direct_data <= '1';
|
set_direct_data <= '1';
|
| Line 1664... |
Line 1809... |
write_back <= '1';
|
write_back <= '1';
|
END IF;
|
END IF;
|
IF opcode(10 downto 9)="10" THEN --CMPI, SUBI
|
IF opcode(10 downto 9)="10" THEN --CMPI, SUBI
|
set(addsub) <= '1';
|
set(addsub) <= '1';
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
-- 0001, 0010, 0011 -----------------------------------------------------------------
|
-- 0001, 0010, 0011 -----------------------------------------------------------------
|
WHEN "0001"|"0010"|"0011" => --move.b, move.l, move.w
|
WHEN "0001"|"0010"|"0011" => --move.b, move.l, move.w
|
|
IF ((opcode(11 downto 10)="00" OR opcode(8 downto 6)/="111") AND --illegal dest ea
|
|
(opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") AND --illegal src ea
|
|
(opcode(13)='1' OR (opcode(8 downto 6)/="001" AND opcode(5 downto 3)/="001"))) THEN --byte src address reg direct, byte movea
|
set_exec(opcMOVE) <= '1';
|
set_exec(opcMOVE) <= '1';
|
ea_build_now <= '1';
|
ea_build_now <= '1';
|
IF opcode(8 downto 6)="001" THEN
|
IF opcode(8 downto 6)="001" THEN
|
set(no_Flags) <= '1';
|
set(no_Flags) <= '1';
|
END IF;
|
END IF;
|
| Line 1740... |
Line 1899... |
WHEN OTHERS => NULL;
|
WHEN OTHERS => NULL;
|
END CASE;
|
END CASE;
|
WHEN OTHERS => NULL;
|
WHEN OTHERS => NULL;
|
END CASE;
|
END CASE;
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
---- 0100 ----------------------------------------------------------------------------
|
---- 0100 ----------------------------------------------------------------------------
|
WHEN "0100" => --rts_group
|
WHEN "0100" => --rts_group
|
IF opcode(8)='1' THEN --lea
|
IF opcode(8)='1' THEN --lea, extb.l, chk
|
IF opcode(6)='1' THEN --lea
|
IF opcode(6)='1' THEN --lea, extb.l
|
IF opcode(7)='1' THEN
|
IF opcode(11 downto 9)="100" AND opcode(5 downto 3)="000" THEN --extb.l
|
|
IF opcode(7)='1' AND cpu(1)='1' THEN
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
-- IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
|
|
IF opcode(5 downto 4)="00" THEN --extb.l
|
|
set_exec(opcEXT) <= '1';
|
set_exec(opcEXT) <= '1';
|
|
set_exec(opcEXTB) <= '1';
|
set_exec(opcMOVE) <= '1';
|
set_exec(opcMOVE) <= '1';
|
set_exec(Regwrena) <= '1';
|
set_exec(Regwrena) <= '1';
|
-- IF opcode(6)='0' THEN
|
|
-- datatype <= "01"; --WORD
|
|
-- END IF;
|
|
ELSE
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
ELSE
|
|
IF opcode(7)='1' AND
|
|
(opcode(5)='1' OR opcode(4 downto 3)="10") AND
|
|
opcode(5 downto 3)/="100" AND opcode(5 downto 2)/="1111" THEN --ea illegal opcodes
|
|
source_lowbits <= '1';
|
source_areg <= '1';
|
source_areg <= '1';
|
ea_only <= '1';
|
ea_only <= '1';
|
set_exec(Regwrena) <= '1';
|
set_exec(Regwrena) <= '1';
|
set_exec(opcMOVE) <='1';
|
set_exec(opcMOVE) <='1';
|
set(no_Flags) <='1';
|
set(no_Flags) <='1';
|
| Line 1774... |
Line 1942... |
END IF;
|
END IF;
|
IF setexecOPC='1' THEN
|
IF setexecOPC='1' THEN
|
dest_areg <= '1';
|
dest_areg <= '1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
END IF;
|
END IF;
|
END IF;
|
|
ELSE
|
ELSE
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
|
END IF;
|
ELSE --chk
|
ELSE --chk
|
|
IF opcode(5 downto 3)/="001" AND --ea An illegal mode
|
|
(opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --ea illegal modes
|
IF opcode(7)='1' THEN
|
IF opcode(7)='1' THEN
|
datatype <= "01"; --Word
|
datatype <= "01"; --Word
|
set(trap_chk) <= '1';
|
set(trap_chk) <= '1';
|
IF (c_out(1)='0' OR OP1out(15)='1' OR OP2out(15)='1') AND exec(opcCHK)='1' THEN
|
IF (c_out(1)='0' OR OP1out(15)='1' OR OP2out(15)='1') AND exec(opcCHK)='1' THEN
|
trapmake <= '1';
|
trapmake <= '1';
|
| Line 1807... |
Line 1977... |
IF setexecOPC='1' THEN
|
IF setexecOPC='1' THEN
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
source_lowbits <='1';
|
source_lowbits <='1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
CASE opcode(11 downto 9) IS
|
CASE opcode(11 downto 9) IS
|
WHEN "000"=>
|
WHEN "000"=>
|
|
IF (opcode(5 downto 3)/="001" AND --ea An illegal mode
|
|
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00")) THEN --ea illegal modes
|
IF opcode(7 downto 6)="11" THEN --move from SR
|
IF opcode(7 downto 6)="11" THEN --move from SR
|
IF SR_Read=0 OR (cpu(0)='0' AND SR_Read=2) OR SVmode='1' THEN
|
IF SR_Read=0 OR (cpu(0)='0' AND SR_Read=2) OR SVmode='1' THEN
|
ea_build_now <= '1';
|
ea_build_now <= '1';
|
set_exec(opcMOVESR) <= '1';
|
set_exec(opcMOVESR) <= '1';
|
datatype <= "01";
|
datatype <= "01";
|
| Line 1841... |
Line 2017... |
END IF;
|
END IF;
|
IF setexecOPC='1' THEN
|
IF setexecOPC='1' THEN
|
set(OP1out_zero) <= '1';
|
set(OP1out_zero) <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
WHEN "001"=>
|
WHEN "001"=>
|
|
IF (opcode(5 downto 3)/="001" AND --ea An illegal mode
|
|
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00")) THEN --ea illegal modes
|
IF opcode(7 downto 6)="11" THEN --move from CCR 68010
|
IF opcode(7 downto 6)="11" THEN --move from CCR 68010
|
IF SR_Read=1 OR (cpu(0)='1' AND SR_Read=2) THEN
|
IF SR_Read=1 OR (cpu(0)='1' AND SR_Read=2) THEN
|
ea_build_now <= '1';
|
ea_build_now <= '1';
|
set_exec(opcMOVESR) <= '1';
|
set_exec(opcMOVESR) <= '1';
|
datatype <= "01";
|
datatype <= "01";
|
| Line 1872... |
Line 2054... |
END IF;
|
END IF;
|
IF opcode(5 downto 4)="00" THEN
|
IF opcode(5 downto 4)="00" THEN
|
set_exec(Regwrena) <= '1';
|
set_exec(Regwrena) <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
WHEN "010"=>
|
WHEN "010"=>
|
ea_build_now <= '1';
|
|
IF opcode(7 downto 6)="11" THEN --move to CCR
|
IF opcode(7 downto 6)="11" THEN --move to CCR
|
|
IF opcode(5 downto 3)/="001" AND --ea An illegal mode
|
|
(opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --ea illegal modes
|
|
ea_build_now <= '1';
|
datatype <= "01";
|
datatype <= "01";
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
IF (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
|
IF (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
|
set(to_CCR) <= '1';
|
set(to_CCR) <= '1';
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
ELSE --neg
|
ELSE --neg
|
|
IF (opcode(5 downto 3)/="001" AND --ea An illegal mode
|
|
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00")) THEN --ea illegal modes
|
|
ea_build_now <= '1';
|
write_back <='1';
|
write_back <='1';
|
set_exec(opcADD) <= '1';
|
set_exec(opcADD) <= '1';
|
set(addsub) <= '1';
|
set(addsub) <= '1';
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
IF opcode(5 downto 4)="00" THEN
|
IF opcode(5 downto 4)="00" THEN
|
set_exec(Regwrena) <= '1';
|
set_exec(Regwrena) <= '1';
|
END IF;
|
END IF;
|
IF setexecOPC='1' THEN
|
IF setexecOPC='1' THEN
|
set(OP1out_zero) <= '1';
|
set(OP1out_zero) <= '1';
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
WHEN "011"=> --not, move toSR
|
WHEN "011"=> --not, move toSR
|
IF opcode(7 downto 6)="11" THEN --move to SR
|
IF opcode(7 downto 6)="11" THEN --move to SR
|
|
IF opcode(5 downto 3)/="001" AND --ea An illegal mode
|
|
(opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --ea illegal modes
|
IF SVmode='1' THEN
|
IF SVmode='1' THEN
|
ea_build_now <= '1';
|
ea_build_now <= '1';
|
datatype <= "01";
|
datatype <= "01";
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
IF (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
|
IF (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
|
| Line 1909... |
Line 2110... |
END IF;
|
END IF;
|
ELSE
|
ELSE
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
ELSE --not
|
ELSE --not
|
|
IF opcode(5 downto 3)/="001" AND --ea An illegal mode
|
|
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN --ea illegal modes
|
ea_build_now <= '1';
|
ea_build_now <= '1';
|
write_back <='1';
|
write_back <='1';
|
set_exec(opcEOR) <= '1';
|
set_exec(opcEOR) <= '1';
|
set_exec(ea_data_OP1) <= '1';
|
set_exec(ea_data_OP1) <= '1';
|
IF opcode(5 downto 3)="000" THEN
|
IF opcode(5 downto 3)="000" THEN
|
set_exec(Regwrena) <= '1';
|
set_exec(Regwrena) <= '1';
|
END IF;
|
END IF;
|
IF setexecOPC='1' THEN
|
IF setexecOPC='1' THEN
|
set(OP2out_one) <= '1';
|
set(OP2out_one) <= '1';
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
WHEN "100"|"110"=>
|
WHEN "100"|"110"=>
|
IF opcode(7)='1' THEN --movem, ext
|
IF opcode(7)='1' THEN --movem, ext
|
IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
|
IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
set_exec(opcEXT) <= '1';
|
set_exec(opcEXT) <= '1';
|
set_exec(opcMOVE) <= '1';
|
set_exec(opcMOVE) <= '1';
|
set_exec(Regwrena) <= '1';
|
set_exec(Regwrena) <= '1';
|
IF opcode(6)='0' THEN
|
IF opcode(6)='0' THEN
|
datatype <= "01"; --WORD
|
datatype <= "01"; --WORD
|
|
set_exec(opcEXTB) <= '1';
|
END IF;
|
END IF;
|
ELSE --movem
|
ELSE --movem
|
-- IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN --MOVEM
|
-- IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN --MOVEM
|
|
IF (opcode(10)='1' OR ((opcode(5)='1' OR opcode(4 downto 3)="10") AND
|
|
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00"))) AND
|
|
(opcode(10)='0' OR (opcode(5 downto 4)/="00" AND
|
|
opcode(5 downto 3)/="100" AND
|
|
opcode(5 downto 2)/="1111")) THEN --ea illegal modes
|
ea_only <= '1';
|
ea_only <= '1';
|
set(no_Flags) <= '1';
|
set(no_Flags) <= '1';
|
IF opcode(6)='0' THEN
|
IF opcode(6)='0' THEN
|
datatype <= "01"; --Word transfer
|
datatype <= "01"; --Word transfer
|
END IF;
|
END IF;
|
| Line 1974... |
Line 2191... |
set(mem_addsub) <= '1';
|
set(mem_addsub) <= '1';
|
ELSE
|
ELSE
|
setstate <="01";
|
setstate <="01";
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
IF opcode(10)='1' THEN --MUL.L, DIV.L 68020
|
IF opcode(10)='1' THEN --MUL.L, DIV.L 68020
|
--FPGA Multiplier for long
|
--FPGA Multiplier for long
|
IF MUL_Hardware=1 AND (opcode(6)='0' AND (MUL_Mode=1 OR (cpu(1)='1' AND MUL_Mode=2))) THEN
|
IF opcode(8 downto 7)="00" AND opcode(5 downto 3)/="001" AND --ea An illegal mode
|
|
MUL_Hardware=1 AND (opcode(6)='0' AND (MUL_Mode=1 OR (cpu(1)='1' AND MUL_Mode=2))) THEN
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
next_micro_state <= nop;
|
next_micro_state <= nop;
|
set(get_2ndOPC) <= '1';
|
set(get_2ndOPC) <= '1';
|
set(ea_build) <= '1';
|
set(ea_build) <= '1';
|
END IF;
|
END IF;
|
| Line 1998... |
Line 2220... |
set(Regwrena) <= '1';
|
set(Regwrena) <= '1';
|
END IF;
|
END IF;
|
source_lowbits <='1';
|
source_lowbits <='1';
|
datatype <= "10";
|
datatype <= "10";
|
|
|
--no FPGA Multplier
|
--no FPGA Multiplier
|
ELSIF (opcode(6)='1' AND (DIV_Mode=1 OR (cpu(1)='1' AND DIV_Mode=2))) OR
|
ELSIF opcode(8 downto 7)="00" AND opcode(5 downto 3)/="001" AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") AND --ea An illegal mode
|
(opcode(6)='0' AND (MUL_Mode=1 OR (cpu(1)='1' AND MUL_Mode=2))) THEN
|
((opcode(6)='1' AND (DIV_Mode=1 OR (cpu(1)='1' AND DIV_Mode=2))) OR
|
|
(opcode(6)='0' AND (MUL_Mode=1 OR (cpu(1)='1' AND MUL_Mode=2)))) THEN
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
next_micro_state <= nop;
|
next_micro_state <= nop;
|
set(get_2ndOPC) <= '1';
|
set(get_2ndOPC) <= '1';
|
set(ea_build) <= '1';
|
set(ea_build) <= '1';
|
END IF;
|
END IF;
|
| Line 2040... |
Line 2263... |
set_exec(Regwrena) <= '1';
|
set_exec(Regwrena) <= '1';
|
ELSIF opcode(5 downto 3)="001" THEN --bkpt
|
ELSIF opcode(5 downto 3)="001" THEN --bkpt
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
ELSE --pea
|
ELSE --pea
|
|
IF (opcode(5)='1' OR opcode(4 downto 3)="10") AND
|
|
opcode(5 downto 3)/="100" AND
|
|
opcode(5 downto 2)/="1111" THEN --ea illegal modes
|
ea_only <= '1';
|
ea_only <= '1';
|
ea_build_now <= '1';
|
ea_build_now <= '1';
|
IF nextpass='1' AND micro_state=idle THEN
|
IF nextpass='1' AND micro_state=idle THEN
|
set(presub) <= '1';
|
set(presub) <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
| Line 2051... |
Line 2277... |
next_micro_state <= nop;
|
next_micro_state <= nop;
|
END IF;
|
END IF;
|
IF set(get_ea_now)='1' THEN
|
IF set(get_ea_now)='1' THEN
|
setstate <="01";
|
setstate <="01";
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
IF opcode(5 downto 3)="001" THEN --link.l
|
IF opcode(5 downto 3)="001" THEN --link.l
|
datatype <= "10";
|
datatype <= "10";
|
set_exec(opcADD) <= '1'; --for displacement
|
set_exec(opcADD) <= '1'; --for displacement
|
| Line 2070... |
Line 2300... |
source_lowbits <= '1';
|
source_lowbits <= '1';
|
source_areg <= '1';
|
source_areg <= '1';
|
set(store_ea_data) <= '1';
|
set(store_ea_data) <= '1';
|
END IF;
|
END IF;
|
ELSE --nbcd
|
ELSE --nbcd
|
|
IF opcode(5 downto 3)/="001" AND --ea An illegal mode
|
|
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN --ea illegal modes
|
ea_build_now <= '1';
|
ea_build_now <= '1';
|
set_exec(use_XZFlag) <= '1';
|
set_exec(use_XZFlag) <= '1';
|
write_back <='1';
|
write_back <='1';
|
set_exec(opcADD) <= '1';
|
set_exec(opcADD) <= '1';
|
set_exec(opcSBCD) <= '1';
|
set_exec(opcSBCD) <= '1';
|
| Line 2083... |
Line 2315... |
set_exec(Regwrena) <= '1';
|
set_exec(Regwrena) <= '1';
|
END IF;
|
END IF;
|
IF setexecOPC='1' THEN
|
IF setexecOPC='1' THEN
|
set(OP1out_zero) <= '1';
|
set(OP1out_zero) <= '1';
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
--0x4AXX
|
--0x4AXX
|
| Line 2094... |
Line 2330... |
-- IF opcode(7 downto 2)="111111" THEN --illegal
|
-- IF opcode(7 downto 2)="111111" THEN --illegal
|
IF opcode(7 downto 3)="11111" AND opcode(2 downto 1)/="00" THEN --0x4AFC illegal --0x4AFB BKP Sinclair QL
|
IF opcode(7 downto 3)="11111" AND opcode(2 downto 1)/="00" THEN --0x4AFC illegal --0x4AFB BKP Sinclair QL
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
ELSE
|
ELSE
|
|
IF (opcode(7 downto 6)/="11" OR --tas
|
|
(opcode(5 downto 3)/="001" AND --ea An illegal mode
|
|
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00"))) AND --ea illegal modes
|
|
((opcode(7 downto 6)/="00" OR (opcode(5 downto 3)/="001")) AND
|
|
(opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00")) THEN
|
ea_build_now <= '1';
|
ea_build_now <= '1';
|
IF setexecOPC='1' THEN
|
IF setexecOPC='1' THEN
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
IF opcode(3)='1' THEN --MC68020...
|
IF opcode(3)='1' THEN --MC68020...
|
source_areg <= '1';
|
source_areg <= '1';
|
| Line 2110... |
Line 2351... |
datatype <= "00"; --Byte
|
datatype <= "00"; --Byte
|
IF opcode(5 downto 4)="00" THEN
|
IF opcode(5 downto 4)="00" THEN
|
set_exec(Regwrena) <= '1';
|
set_exec(Regwrena) <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
---- WHEN "110"=>
|
---- WHEN "110"=>
|
WHEN "111"=> --4EXX
|
WHEN "111"=> --4EXX
|
--
|
--
|
-- ea_only <= '1';
|
-- ea_only <= '1';
|
| Line 2131... |
Line 2376... |
--
|
--
|
|
|
|
|
|
|
IF opcode(7)='1' THEN --jsr, jmp
|
IF opcode(7)='1' THEN --jsr, jmp
|
|
IF (opcode(5)='1' OR opcode(4 downto 3)="10") AND
|
|
opcode(5 downto 3)/="100" AND opcode(5 downto 2)/="1111" THEN --ea illegal modes
|
datatype <= "10";
|
datatype <= "10";
|
ea_only <= '1';
|
ea_only <= '1';
|
ea_build_now <= '1';
|
ea_build_now <= '1';
|
IF exec(ea_to_pc)='1' THEN
|
IF exec(ea_to_pc)='1' THEN
|
next_micro_state <= nop;
|
next_micro_state <= nop;
|
| Line 2143... |
Line 2390... |
set(presub) <= '1';
|
set(presub) <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
setstate <="11";
|
setstate <="11";
|
next_micro_state <= nopnop;
|
next_micro_state <= nopnop;
|
END IF;
|
END IF;
|
-- achtung buggefahr
|
|
IF micro_state=ld_AnXn1 AND brief(8)='0'THEN --JMP/JSR n(Ax,Dn)
|
IF micro_state=ld_AnXn1 AND brief(8)='0'THEN --JMP/JSR n(Ax,Dn)
|
skipFetch <= '1';
|
skipFetch <= '1';
|
END IF;
|
END IF;
|
IF state="00" THEN
|
IF state="00" THEN
|
writePC <= '1';
|
writePC <= '1';
|
| Line 2158... |
Line 2405... |
skipFetch <= '1';
|
skipFetch <= '1';
|
END IF;
|
END IF;
|
setstate <="01";
|
setstate <="01";
|
set(ea_to_pc) <= '1';
|
set(ea_to_pc) <= '1';
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
ELSE --
|
ELSE --
|
CASE opcode(6 downto 0) IS
|
CASE opcode(6 downto 0) IS
|
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
|
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
|
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
|
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
|
trap_trap <='1';
|
trap_trap <='1';
|
trapmake <= '1';
|
trapmake <= '1';
|
|
|
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111"=> --link word
|
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111"=> --link word
|
datatype <= "10";
|
datatype <= "10";
|
set_exec(opcADD) <= '1'; --for displacement
|
set_exec(opcADD) <= '1'; --for displacement
|
set_exec(Regwrena) <= '1';
|
set_exec(Regwrena) <= '1';
|
set(no_Flags) <= '1';
|
set(no_Flags) <= '1';
|
| Line 2205... |
Line 2457... |
datatype <= "10";
|
datatype <= "10";
|
ELSE
|
ELSE
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
|
|
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
|
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
|
IF SVmode='1' THEN
|
IF SVmode='1' THEN
|
-- set(no_Flags) <= '1';
|
-- set(no_Flags) <= '1';
|
set(from_USP) <= '1';
|
set(from_USP) <= '1';
|
datatype <= "10";
|
datatype <= "10";
|
| Line 2354... |
Line 2607... |
ELSE
|
ELSE
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
setstate <= "01";
|
setstate <= "01";
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
trap_trapcc<='1';
|
|
IF exe_condition='1' AND decodeOPC='0' THEN
|
IF exe_condition='1' AND decodeOPC='0' THEN
|
trap_trapv <= '1';
|
trap_trapv <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
| Line 2376... |
Line 2628... |
IF opcode(5 downto 4)="00" THEN
|
IF opcode(5 downto 4)="00" THEN
|
set_exec(Regwrena) <= '1';
|
set_exec(Regwrena) <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
ELSE --addq, subq
|
ELSE --addq, subq
|
|
IF opcode(7 downto 3)/="00001" AND
|
|
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN --ea illegal modes
|
ea_build_now <= '1';
|
ea_build_now <= '1';
|
IF opcode(5 downto 3)="001" THEN
|
IF opcode(5 downto 3)="001" THEN
|
set(no_Flags) <= '1';
|
set(no_Flags) <= '1';
|
END IF;
|
END IF;
|
IF opcode(8)='1' THEN
|
IF opcode(8)='1' THEN
|
| Line 2390... |
Line 2644... |
set_exec(opcADD) <= '1';
|
set_exec(opcADD) <= '1';
|
set_exec(ea_data_OP1) <= '1';
|
set_exec(ea_data_OP1) <= '1';
|
IF opcode(5 downto 4)="00" THEN
|
IF opcode(5 downto 4)="00" THEN
|
set_exec(Regwrena) <= '1';
|
set_exec(Regwrena) <= '1';
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
--
|
--
|
---- 0110 ----------------------------------------------------------------------------
|
---- 0110 ----------------------------------------------------------------------------
|
WHEN "0110" => --bra,bsr,bcc
|
WHEN "0110" => --bra,bsr,bcc
|
datatype <= "10";
|
datatype <= "10";
|
| Line 2425... |
Line 2683... |
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
-- 0111 ----------------------------------------------------------------------------
|
-- 0111 ----------------------------------------------------------------------------
|
WHEN "0111" => --moveq
|
WHEN "0111" => --moveq
|
|
IF opcode(8)='0' THEN
|
datatype <= "10"; --Long
|
datatype <= "10"; --Long
|
set_exec(Regwrena) <= '1';
|
set_exec(Regwrena) <= '1';
|
set_exec(opcMOVEQ) <= '1';
|
set_exec(opcMOVEQ) <= '1';
|
set_exec(opcMOVE) <= '1';
|
set_exec(opcMOVE) <= '1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
|
---- 1000 ----------------------------------------------------------------------------
|
---- 1000 ----------------------------------------------------------------------------
|
WHEN "1000" => --or
|
WHEN "1000" => --or
|
IF opcode(7 downto 6)="11" THEN --divu, divs
|
IF opcode(7 downto 6)="11" THEN --divu, divs
|
IF DIV_Mode/=3 THEN
|
IF DIV_Mode/=3 AND
|
|
opcode(5 downto 3)/="001" AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --ea illegal modes
|
IF opcode(5 downto 4)="00" THEN --Dn, An
|
IF opcode(5 downto 4)="00" THEN --Dn, An
|
regdirectsource <= '1';
|
regdirectsource <= '1';
|
END IF;
|
END IF;
|
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
|
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
|
setstate <="01";
|
setstate <="01";
|
| Line 2455... |
Line 2719... |
datatype <= "01";
|
datatype <= "01";
|
ELSE
|
ELSE
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
|
|
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --sbcd, pack , unpack
|
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --sbcd, pack , unpack
|
IF opcode(7 downto 6)="00" THEN --sbcd
|
IF opcode(7 downto 6)="00" THEN --sbcd
|
build_bcd <= '1';
|
build_bcd <= '1';
|
set_exec(opcADD) <= '1';
|
set_exec(opcADD) <= '1';
|
set_exec(opcSBCD) <= '1';
|
set_exec(opcSBCD) <= '1';
|
| Line 2499... |
Line 2762... |
ELSE
|
ELSE
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
ELSE --or
|
ELSE --or
|
|
IF opcode(7 downto 6)/="11" AND --illegal opmode
|
|
((opcode(8)='0' AND opcode(5 downto 3)/="001" AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00")) OR --illegal src ea
|
|
(opcode(8)='1' AND opcode(5 downto 4)/="00" AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00"))) THEN --illegal dst ea
|
set_exec(opcOR) <= '1';
|
set_exec(opcOR) <= '1';
|
build_logical <= '1';
|
build_logical <= '1';
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
|
|
---- 1001, 1101 -----------------------------------------------------------------------
|
---- 1001, 1101 -----------------------------------------------------------------------
|
WHEN "1001"|"1101" => --sub, add
|
WHEN "1001"|"1101" => --sub, add
|
|
IF opcode(8 downto 3)/="000001" AND --byte src address reg direct
|
|
(((opcode(8)='0' OR opcode(7 downto 6)="11") AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00")) OR --illegal src ea
|
|
(opcode(8)='1' AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00"))) THEN --illegal dst ea
|
set_exec(opcADD) <= '1';
|
set_exec(opcADD) <= '1';
|
ea_build_now <= '1';
|
ea_build_now <= '1';
|
IF opcode(14)='0' THEN
|
IF opcode(14)='0' THEN
|
set(addsub) <= '1';
|
set(addsub) <= '1';
|
END IF;
|
END IF;
|
| Line 2531... |
Line 2804... |
build_bcd <= '1';
|
build_bcd <= '1';
|
ELSE --sub, add
|
ELSE --sub, add
|
build_logical <= '1';
|
build_logical <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
--
|
--
|
---- 1010 ----------------------------------------------------------------------------
|
---- 1010 ----------------------------------------------------------------------------
|
WHEN "1010" => --Trap 1010
|
WHEN "1010" => --Trap 1010
|
trap_1010 <= '1';
|
trap_1010 <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
---- 1011 ----------------------------------------------------------------------------
|
---- 1011 ----------------------------------------------------------------------------
|
WHEN "1011" => --eor, cmp
|
WHEN "1011" => --eor, cmp
|
ea_build_now <= '1';
|
|
IF opcode(7 downto 6)="11" THEN --CMPA
|
IF opcode(7 downto 6)="11" THEN --CMPA
|
|
IF opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00" THEN --illegal src ea
|
|
ea_build_now <= '1';
|
IF opcode(8)='0' THEN --cmpa.w
|
IF opcode(8)='0' THEN --cmpa.w
|
datatype <= "01"; --Word
|
datatype <= "01"; --Word
|
set_exec(opcCPMAW) <= '1';
|
set_exec(opcCPMAW) <= '1';
|
END IF;
|
END IF;
|
set_exec(opcCMP) <= '1';
|
set_exec(opcCMP) <= '1';
|
| Line 2556... |
Line 2833... |
dest_areg <='1';
|
dest_areg <='1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
END IF;
|
END IF;
|
set(addsub) <= '1';
|
set(addsub) <= '1';
|
ELSE
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
ELSE --cmpm, eor, cmp
|
IF opcode(8)='1' THEN
|
IF opcode(8)='1' THEN
|
IF opcode(5 downto 3)="001" THEN --cmpm
|
IF opcode(5 downto 3)="001" THEN --cmpm
|
|
ea_build_now <= '1';
|
set_exec(opcCMP) <= '1';
|
set_exec(opcCMP) <= '1';
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
IF opcode(2 downto 0)="111" THEN
|
IF opcode(2 downto 0)="111" THEN
|
set(use_SP) <= '1';
|
set(use_SP) <= '1';
|
END IF;
|
END IF;
|
| Line 2571... |
Line 2853... |
next_micro_state <= cmpm;
|
next_micro_state <= cmpm;
|
END IF;
|
END IF;
|
set_exec(ea_data_OP1) <= '1';
|
set_exec(ea_data_OP1) <= '1';
|
set(addsub) <= '1';
|
set(addsub) <= '1';
|
ELSE --EOR
|
ELSE --EOR
|
|
IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" THEN --illegal dst ea
|
|
ea_build_now <= '1';
|
build_logical <= '1';
|
build_logical <= '1';
|
set_exec(opcEOR) <= '1';
|
set_exec(opcEOR) <= '1';
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
ELSE --CMP
|
ELSE --CMP
|
|
IF opcode(8 downto 3)/="000001" AND --byte src address reg direct
|
|
(opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --illegal src ea
|
|
ea_build_now <= '1';
|
build_logical <= '1';
|
build_logical <= '1';
|
set_exec(opcCMP) <= '1';
|
set_exec(opcCMP) <= '1';
|
set(addsub) <= '1';
|
set(addsub) <= '1';
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
--
|
--
|
---- 1100 ----------------------------------------------------------------------------
|
---- 1100 ----------------------------------------------------------------------------
|
WHEN "1100" => --and, exg
|
WHEN "1100" => --and, exg
|
IF opcode(7 downto 6)="11" THEN --mulu, muls
|
IF opcode(7 downto 6)="11" THEN --mulu, muls
|
IF MUL_Mode/=3 THEN
|
IF MUL_Mode/=3 AND
|
|
opcode(5 downto 3)/="001" AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --ea illegal modes
|
IF opcode(5 downto 4)="00" THEN --Dn, An
|
IF opcode(5 downto 4)="00" THEN --Dn, An
|
regdirectsource <= '1';
|
regdirectsource <= '1';
|
END IF;
|
END IF;
|
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
|
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
|
IF MUL_Hardware=0 THEN
|
IF MUL_Hardware=0 THEN
|
| Line 2608... |
Line 2904... |
END IF;
|
END IF;
|
datatype <= "01";
|
datatype <= "01";
|
IF setexecOPC='1' THEN
|
IF setexecOPC='1' THEN
|
datatype <= "10";
|
datatype <= "10";
|
END IF;
|
END IF;
|
|
|
ELSE
|
ELSE
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
|
|
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --exg, abcd
|
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --exg, abcd
|
IF opcode(7 downto 6)="00" THEN --abcd
|
IF opcode(7 downto 6)="00" THEN --abcd
|
build_bcd <= '1';
|
build_bcd <= '1';
|
set_exec(opcADD) <= '1';
|
set_exec(opcADD) <= '1';
|
set_exec(opcABCD) <= '1';
|
set_exec(opcABCD) <= '1';
|
ELSE --exg
|
ELSE --exg
|
|
IF opcode(7 downto 4)="0100" OR opcode(7 downto 3)="10001" THEN
|
datatype <= "10";
|
datatype <= "10";
|
set(Regwrena) <= '1';
|
set(Regwrena) <= '1';
|
set(exg) <= '1';
|
set(exg) <= '1';
|
|
set(alu_move) <= '1';
|
IF opcode(6)='1' AND opcode(3)='1' THEN
|
IF opcode(6)='1' AND opcode(3)='1' THEN
|
dest_areg <= '1';
|
dest_areg <= '1';
|
source_areg <= '1';
|
source_areg <= '1';
|
END IF;
|
END IF;
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
setstate <= "01";
|
setstate <= "01";
|
ELSE
|
ELSE
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
END IF;
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
ELSE --and
|
ELSE --and
|
|
IF opcode(7 downto 6)/="11" AND --illegal opmode
|
|
((opcode(8)='0' AND opcode(5 downto 3)/="001" AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00")) OR --illegal src ea
|
|
(opcode(8)='1' AND opcode(5 downto 4)/="00" AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00"))) THEN --illegal dst ea
|
set_exec(opcAND) <= '1';
|
set_exec(opcAND) <= '1';
|
build_logical <= '1';
|
build_logical <= '1';
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
--
|
--
|
---- 1110 ----------------------------------------------------------------------------
|
---- 1110 ----------------------------------------------------------------------------
|
WHEN "1110" => --rotation / bitfield
|
WHEN "1110" => --rotation / bitfield
|
IF opcode(7 downto 6)="11" THEN
|
IF opcode(7 downto 6)="11" THEN
|
IF opcode(11)='0' THEN
|
IF opcode(11)='0' THEN
|
|
IF (opcode(5 downto 4)/="00" AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00")) THEN --ea illegal modes
|
IF BarrelShifter=0 THEN
|
IF BarrelShifter=0 THEN
|
set_exec(opcROT) <= '1';
|
set_exec(opcROT) <= '1';
|
ELSE
|
ELSE
|
set_exec(exec_BS) <='1';
|
set_exec(exec_BS) <='1';
|
END IF;
|
END IF;
|
ea_build_now <= '1';
|
ea_build_now <= '1';
|
datatype <= "01";
|
datatype <= "01";
|
set_rot_bits <= opcode(10 downto 9);
|
set_rot_bits <= opcode(10 downto 9);
|
set_exec(ea_data_OP1) <= '1';
|
set_exec(ea_data_OP1) <= '1';
|
write_back <= '1';
|
write_back <= '1';
|
|
ELSE
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
ELSE --bitfield
|
ELSE --bitfield
|
IF BitField=0 OR (cpu(1)='0' AND BitField=2) THEN
|
IF BitField=0 OR (cpu(1)='0' AND BitField=2) OR
|
|
((opcode(10 downto 9)="11" OR opcode(10 downto 8)="010" OR opcode(10 downto 8)="100") AND
|
|
(opcode(5 downto 3)="001" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" OR (opcode(5 downto 3)="111" AND opcode(2 downto 1)/="00"))) OR
|
|
((opcode(10 downto 9)="00" OR opcode(10 downto 8)="011" OR opcode(10 downto 8)="101") AND
|
|
(opcode(5 downto 3)="001" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" OR opcode(5 downto 2)="1111")) THEN
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
ELSE
|
ELSE
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
next_micro_state <= nop;
|
next_micro_state <= nop;
|
| Line 2670... |
Line 2986... |
set_exec(opcBFwb) <= '1'; --'1' for tst,chg,clr,ffo,set,ins --'0' for extu,exts
|
set_exec(opcBFwb) <= '1'; --'1' for tst,chg,clr,ffo,set,ins --'0' for extu,exts
|
END IF;
|
END IF;
|
IF opcode(10 downto 8)="111" THEN --BFINS
|
IF opcode(10 downto 8)="111" THEN --BFINS
|
set_exec(ea_data_OP1) <= '1';
|
set_exec(ea_data_OP1) <= '1';
|
END IF;
|
END IF;
|
|
|
IF opcode(10 downto 8)="010" OR opcode(10 downto 8)="100" OR opcode(10 downto 8)="110" OR opcode(10 downto 8)="111" THEN
|
IF opcode(10 downto 8)="010" OR opcode(10 downto 8)="100" OR opcode(10 downto 8)="110" OR opcode(10 downto 8)="111" THEN
|
write_back <= '1';
|
write_back <= '1';
|
END IF;
|
END IF;
|
ea_only <= '1';
|
ea_only <= '1';
|
IF opcode(10 downto 8)="001" OR opcode(10 downto 8)="011" OR opcode(10 downto 8)="101" THEN
|
IF opcode(10 downto 8)="001" OR opcode(10 downto 8)="011" OR opcode(10 downto 8)="101" THEN
|
| Line 2700... |
Line 3015... |
set(get_bfoffset) <='1';
|
set(get_bfoffset) <='1';
|
setstate <= "01";
|
setstate <= "01";
|
set(mem_addsub) <='1';
|
set(mem_addsub) <='1';
|
next_micro_state <= bf1;
|
next_micro_state <= bf1;
|
END IF;
|
END IF;
|
|
|
IF setexecOPC='1' THEN
|
IF setexecOPC='1' THEN
|
IF opcode(10 downto 8)="111" THEN --BFINS
|
IF opcode(10 downto 8)="111" THEN --BFINS
|
source_2ndHbits <= '1';
|
source_2ndHbits <= '1';
|
ELSE
|
ELSE
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
| Line 2716... |
Line 3030... |
END IF;
|
END IF;
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
data_is_source <= '1';
|
data_is_source <= '1';
|
IF BarrelShifter=0 OR (cpu(1)='0' AND BarrelShifter=2) THEN
|
IF BarrelShifter=0 OR (cpu(1)='0' AND BarrelShifter=2) THEN
|
|
|
set_exec(opcROT) <= '1';
|
set_exec(opcROT) <= '1';
|
set_rot_bits <= opcode(4 downto 3);
|
set_rot_bits <= opcode(4 downto 3);
|
set_exec(Regwrena) <= '1';
|
set_exec(Regwrena) <= '1';
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
IF opcode(5)='1' THEN
|
IF opcode(5)='1' THEN
|
| Line 2741... |
Line 3054... |
set_rot_bits <= opcode(4 downto 3);
|
set_rot_bits <= opcode(4 downto 3);
|
set_exec(Regwrena) <= '1';
|
set_exec(Regwrena) <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
--
|
--
|
|
---- 1111 ----------------------------------------------------------------------------
|
|
WHEN "1111" =>
|
|
IF cpu(1)='1' AND opcode(8 downto 6)="100" THEN --cpSAVE
|
|
IF opcode(5 downto 4)/="00" AND opcode(5 downto 3)/="011" AND
|
|
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN --ea illegal modes
|
|
IF opcode(11 downto 9)/="000" THEN
|
|
IF SVmode='1' THEN
|
|
IF opcode(5)='0' AND opcode(5 downto 4)/="01" THEN
|
|
--never reached according to cputest?!
|
|
--cpSAVE not implemented
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
ELSE
|
|
trap_1111 <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
ELSE
|
|
trap_priv <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
ELSE
|
|
IF SVmode='1' THEN
|
|
trap_1111 <= '1';
|
|
trapmake <= '1';
|
|
ELSE
|
|
trap_priv <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
END IF;
|
|
ELSE
|
|
trap_1111 <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
ELSIF cpu(1)='1' AND opcode(8 downto 6)="101" THEN --cpRESTORE
|
|
IF opcode(5 downto 4)/="00" AND opcode(5 downto 3)/="100" AND
|
|
(opcode(5 downto 3)/="111" OR (opcode(2 downto 1)/="11" AND
|
|
opcode(2 downto 0)/="101")) THEN --ea illegal modes
|
|
IF opcode(5 downto 1)/="11110" THEN
|
|
IF opcode(11 downto 9)="001" OR opcode(11 downto 9)="010" THEN
|
|
IF SVmode='1' THEN
|
|
IF opcode(5 downto 3)="101" THEN
|
|
--cpRESTORE not implemented
|
|
trap_illegal <= '1';
|
|
trapmake <= '1';
|
|
ELSE
|
|
trap_1111 <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
ELSE
|
|
trap_priv <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
ELSE
|
|
IF SVmode='1' THEN
|
|
trap_1111 <= '1';
|
|
trapmake <= '1';
|
|
ELSE
|
|
trap_priv <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
END IF;
|
|
ELSE
|
|
trap_1111 <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
ELSE
|
|
trap_1111 <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
ELSE
|
|
trap_1111 <= '1';
|
|
trapmake <= '1';
|
|
END IF;
|
|
--
|
---- ----------------------------------------------------------------------------
|
---- ----------------------------------------------------------------------------
|
WHEN OTHERS =>
|
WHEN OTHERS =>
|
trap_1111 <= '1';
|
trap_illegal <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
|
|
END CASE;
|
END CASE;
|
|
|
-- use for AND, OR, EOR, CMP
|
-- use for AND, OR, EOR, CMP
|
| Line 3042... |
Line 3429... |
next_micro_state <= nop;
|
next_micro_state <= nop;
|
TG68_PC_brw <= '1';
|
TG68_PC_brw <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
|
WHEN chk20 => --if C is set -> signed compare
|
|
set(ea_data_OP1) <= '1';
|
|
set(addsub) <= '1';
|
|
set(alu_exec) <= '1';
|
|
set(alu_setFlags) <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= chk21;
|
|
WHEN chk21 => -- check lower bound
|
|
dest_2ndHbits <= '1';
|
|
IF sndOPC(15)='1' THEN
|
|
set_datatype <="10"; --long
|
|
dest_LDRareg <= '1';
|
|
IF opcode(10 downto 9)="00" THEN
|
|
set(opcEXTB) <= '1';
|
|
END IF;
|
|
END IF;
|
|
set(addsub) <= '1';
|
|
set(alu_exec) <= '1';
|
|
set(alu_setFlags) <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= chk22;
|
|
WHEN chk22 => --check upper bound
|
|
dest_2ndHbits <= '1';
|
|
set(ea_data_OP2) <= '1';
|
|
IF sndOPC(15)='1' THEN
|
|
set_datatype <="10"; --long
|
|
dest_LDRareg <= '1';
|
|
END IF;
|
|
set(addsub) <= '1';
|
|
set(alu_exec) <= '1';
|
|
set(opcCHK2) <= '1';
|
|
set(opcEXTB) <= exec(opcEXTB);
|
|
IF sndOPC(11)='1' THEN
|
|
setstate <="01";
|
|
next_micro_state <= chk23;
|
|
END IF;
|
|
WHEN chk23 =>
|
|
setstate <="01";
|
|
next_micro_state <= chk24;
|
|
WHEN chk24 =>
|
|
IF Flags(0)='1'THEN
|
|
trapmake <= '1';
|
|
END IF;
|
|
|
|
|
|
WHEN cas1 =>
|
|
setstate <="01";
|
|
next_micro_state <= cas2;
|
|
WHEN cas2 =>
|
|
source_2ndMbits <= '1';
|
|
IF Flags(2)='1'THEN
|
|
setstate<="11";
|
|
set(write_reg) <= '1';
|
|
set(restore_ADDR) <= '1';
|
|
next_micro_state <= nop;
|
|
ELSE
|
|
set(Regwrena) <= '1';
|
|
set(ea_data_OP2) <='1';
|
|
dest_2ndLbits <= '1';
|
|
set(alu_move) <= '1';
|
|
END IF;
|
|
|
|
WHEN cas21 =>
|
|
dest_2ndHbits <= '1';
|
|
dest_LDRareg <= sndOPC(15);
|
|
set(get_ea_now) <='1';
|
|
next_micro_state <= cas22;
|
|
WHEN cas22 =>
|
|
setstate <= "01";
|
|
source_2ndLbits <= '1';
|
|
set(ea_data_OP1) <= '1';
|
|
set(addsub) <= '1';
|
|
set(alu_exec) <= '1';
|
|
set(alu_setFlags) <= '1';
|
|
next_micro_state <= cas23;
|
|
WHEN cas23 =>
|
|
dest_LDRHbits <= '1';
|
|
set(get_ea_now) <='1';
|
|
next_micro_state <= cas24;
|
|
WHEN cas24 =>
|
|
IF Flags(2)='1'THEN
|
|
set(alu_setFlags) <= '1';
|
|
END IF;
|
|
setstate <="01";
|
|
set(hold_dwr) <= '1';
|
|
source_LDRLbits <= '1';
|
|
set(ea_data_OP1) <= '1';
|
|
set(addsub) <= '1';
|
|
set(alu_exec) <= '1';
|
|
next_micro_state <= cas25;
|
|
WHEN cas25 =>
|
|
setstate <= "01";
|
|
set(hold_dwr) <= '1';
|
|
next_micro_state <= cas26;
|
|
WHEN cas26 =>
|
|
IF Flags(2)='1'THEN -- write Update 1 to Destination 1
|
|
source_2ndMbits <= '1';
|
|
set(write_reg) <= '1';
|
|
dest_2ndHbits <= '1';
|
|
dest_LDRareg <= sndOPC(15);
|
|
setstate <= "11";
|
|
set(get_ea_now) <='1';
|
|
next_micro_state <= cas27;
|
|
ELSE -- write Destination 2 to Compare 2 first
|
|
set(hold_dwr) <= '1';
|
|
set(hold_OP2) <='1';
|
|
dest_LDRLbits <= '1';
|
|
set(alu_move) <= '1';
|
|
set(Regwrena) <= '1';
|
|
set(ea_data_OP2) <='1';
|
|
next_micro_state <= cas28;
|
|
END IF;
|
|
WHEN cas27 => -- write Update 2 to Destination 2
|
|
source_LDRMbits <= '1';
|
|
set(write_reg) <= '1';
|
|
dest_LDRHbits <= '1';
|
|
setstate <= "11";
|
|
set(get_ea_now) <='1';
|
|
next_micro_state <= nopnop;
|
|
WHEN cas28 => -- write Destination 1 to Compare 1 second
|
|
dest_2ndLbits <= '1';
|
|
set(alu_move) <= '1';
|
|
set(Regwrena) <= '1';
|
|
|
WHEN movem1 => --movem
|
WHEN movem1 => --movem
|
IF last_data_read(15 downto 0)/=X"0000" THEN
|
IF last_data_read(15 downto 0)/=X"0000" THEN
|
setstate <="01";
|
setstate <="01";
|
IF opcode(5 downto 3)="100" THEN
|
IF opcode(5 downto 3)="100" THEN
|
set(mem_addsub) <= '1';
|
set(mem_addsub) <= '1';
|
| Line 3374... |
Line 3885... |
END IF;
|
END IF;
|
set(Regwrena) <= '1';
|
set(Regwrena) <= '1';
|
END IF;
|
END IF;
|
datatype <= "10";
|
datatype <= "10";
|
WHEN mul_end2 => -- divu
|
WHEN mul_end2 => -- divu
|
|
dest_2ndLbits <= '1';
|
set(write_reminder) <= '1';
|
set(write_reminder) <= '1';
|
set(Regwrena) <= '1';
|
set(Regwrena) <= '1';
|
set(opcMULU) <= '1';
|
set(opcMULU) <= '1';
|
|
|
WHEN div1 => -- divu
|
WHEN div1 => -- divu
|
| Line 3406... |
Line 3918... |
ELSE
|
ELSE
|
next_micro_state <= div4;
|
next_micro_state <= div4;
|
END IF;
|
END IF;
|
WHEN div_end1 => -- divu
|
WHEN div_end1 => -- divu
|
IF opcode(15)='0' AND (DIV_Mode=1 OR DIV_Mode=2) THEN
|
IF opcode(15)='0' AND (DIV_Mode=1 OR DIV_Mode=2) THEN
|
|
dest_2ndLbits <= '1';
|
set(write_reminder) <= '1';
|
set(write_reminder) <= '1';
|
next_micro_state <= div_end2;
|
next_micro_state <= div_end2;
|
setstate <="01";
|
setstate <="01";
|
END IF;
|
END IF;
|
set(opcDIVU) <= '1';
|
set(opcDIVU) <= '1';
|
