| Line 54... |
Line 54... |
output [AMSB:0] pc;
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output [AMSB:0] pc;
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parameter RSTPC = 32'hFFFC0100;
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parameter RSTPC = 32'hFFFC0100;
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integer n;
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integer n;
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reg [AMSB:0] ras [0:DEPTH-1];
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reg [AMSB:0] ras [0:DEPTH-1];
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reg [4:0] rasp;
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reg [3:0] rasp;
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assign pc = ras[rasp];
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assign pc = ras[rasp];
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reg [47:0] lasti0, lasti1;
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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for (n = 0; n < 32; n = n + 1)
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lasti0 <= `NOP_INSN;
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lasti1 <= `NOP_INSN;
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for (n = 0; n < DEPTH; n = n + 1)
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ras[n] <= RSTPC;
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ras[n] <= RSTPC;
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rasp <= 5'd0;
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rasp <= 4'd0;
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end
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end
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else begin
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else begin
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if (fetchbuf0_v && fetchbuf1_v && (queued1 || queued2)) begin
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if (fetchbuf0_v && fetchbuf1_v && (queued1 || queued2)) begin
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// Make sure the instruction changed between clock cycles.
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lasti0 <= fetchbuf0_instr;
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lasti1 <= fetchbuf1_instr;
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if (fetchbuf0_instr != lasti0 || fetchbuf1_instr != lasti1) begin
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case(fetchbuf0_instr[`INSTRUCTION_OP])
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case(fetchbuf0_instr[`INSTRUCTION_OP])
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`JAL:
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`JAL:
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begin
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begin
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// JAL LR,xxxx assume call
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// JAL LR,xxxx assume call
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if (fetchbuf0_instr[`INSTRUCTION_RB]==regLR) begin
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if (fetchbuf0_instr[`INSTRUCTION_RB]==regLR) begin
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ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + 32'd4;
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ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + (fetchbuf0_instr[6] ? 32'd6 : 32'd4);
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rasp <= rasp - 4'd1;
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rasp <= rasp - 4'd1;
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end
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end
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// JAL r0,[r29] assume a ret
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// JAL r0,[r29] assume a ret
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else if (fetchbuf0_instr[`INSTRUCTION_RB]==5'd00 &&
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else if (fetchbuf0_instr[`INSTRUCTION_RB]==5'd00 &&
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fetchbuf0_instr[`INSTRUCTION_RA]==regLR) begin
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fetchbuf0_instr[`INSTRUCTION_RA]==regLR) begin
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rasp <= rasp + 4'd1;
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rasp <= rasp + 4'd1;
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end
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end
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end
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end
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`CALL:
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`CALL:
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begin
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begin
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ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + 32'd4;
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ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + (fetchbuf0_instr[6] ? 32'd6 : 32'd4);
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rasp <= rasp - 4'd1;
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rasp <= rasp - 4'd1;
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end
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end
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`RET: begin
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`RET: begin
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$display("RSP: Added 1");
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$display("RSP: Added 1");
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rasp <= rasp + 4'd1;
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rasp <= rasp + 4'd1;
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end
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end
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default: ;
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default: ;
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endcase
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endcase
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end
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end
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end
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else if (fetchbuf1_v && queued1)
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else if (fetchbuf1_v && queued1)
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lasti1 <= fetchbuf1_instr;
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if (fetchbuf1_instr != lasti1) begin
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case(fetchbuf1_instr[`INSTRUCTION_OP])
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case(fetchbuf1_instr[`INSTRUCTION_OP])
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`JAL:
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`JAL:
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if (fetchbuf1_instr[`INSTRUCTION_RB]==regLR) begin
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if (fetchbuf1_instr[`INSTRUCTION_RB]==regLR) begin
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ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf1_pc + 32'd4;
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ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf1_pc + (fetchbuf1_instr[6] ? 32'd6 : 32'd4);
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rasp <= rasp - 4'd1;
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rasp <= rasp - 4'd1;
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end
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end
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else if (fetchbuf1_instr[`INSTRUCTION_RB]==5'd00 &&
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else if (fetchbuf1_instr[`INSTRUCTION_RB]==5'd00 &&
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fetchbuf1_instr[`INSTRUCTION_RA]==regLR) begin
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fetchbuf1_instr[`INSTRUCTION_RA]==regLR) begin
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rasp <= rasp + 4'd1;
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rasp <= rasp + 4'd1;
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end
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end
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`CALL:
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`CALL:
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begin
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begin
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ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf1_pc + 32'd4;
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ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf1_pc + (fetchbuf1_instr[6] ? 32'd6 : 32'd4);
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rasp <= rasp - 4'd1;
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rasp <= rasp - 4'd1;
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end
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end
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`RET: begin
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`RET: begin
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rasp <= rasp + 4'd1;
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rasp <= rasp + 4'd1;
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$display("RSP: Added 1");
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$display("RSP: Added 1");
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end
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end
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default: ;
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default: ;
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endcase
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endcase
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end
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else if (fetchbuf0_v && queued1)
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else if (fetchbuf0_v && queued1)
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lasti0 <= fetchbuf0_instr;
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if (lasti0 != fetchbuf0_instr) begin
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case(fetchbuf0_instr[`INSTRUCTION_OP])
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case(fetchbuf0_instr[`INSTRUCTION_OP])
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`JAL:
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`JAL:
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if (fetchbuf0_instr[`INSTRUCTION_RB]==regLR) begin
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if (fetchbuf0_instr[`INSTRUCTION_RB]==regLR) begin
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ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + 32'd4;
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ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + (fetchbuf0_instr[6] ? 32'd6 : 32'd4);
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rasp <= rasp - 4'd1;
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rasp <= rasp - 4'd1;
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end
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end
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else if (fetchbuf0_instr[`INSTRUCTION_RB]==5'd00 &&
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else if (fetchbuf0_instr[`INSTRUCTION_RB]==5'd00 &&
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fetchbuf0_instr[`INSTRUCTION_RA]==regLR) begin
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fetchbuf0_instr[`INSTRUCTION_RA]==regLR) begin
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rasp <= rasp + 4'd1;
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rasp <= rasp + 4'd1;
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end
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end
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`CALL:
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`CALL:
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begin
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begin
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ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + 32'd4;
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ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + (fetchbuf0_instr[6] ? 32'd6 : 32'd4);
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rasp <= rasp - 4'd1;
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rasp <= rasp - 4'd1;
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end
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end
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`RET: begin
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`RET: begin
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$display("RSP: Added 1");
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$display("RSP: Added 1");
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rasp <= rasp + 4'd1;
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rasp <= rasp + 4'd1;
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end
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end
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default: ;
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default: ;
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endcase
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endcase
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end
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/*
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/*
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if (stompedRets > 4'd0) begin
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if (stompedRets > 4'd0) begin
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$display("Stomped Rets: %d", stompedRets);
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$display("Stomped Rets: %d", stompedRets);
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rasp <= rasp - stompedRets;
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rasp <= rasp - stompedRets;
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end
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end
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