// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2017-2018 Robert Finch, Waterloo
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// \\__/ o\ (C) 2017-2018 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// FT64_alu.v
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// FT64_alu.v
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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`include "FT64_defines.vh"
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`include "FT64_defines.vh"
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module FT64_alu(rst, clk, ld, abort, instr, a, b, c, pc, tgt, tgt2, ven, vm, sbl, sbu,
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module FT64_alu(rst, clk, ld, abort, instr, a, b, c, pc, tgt, tgt2, ven, vm, sbl, sbu,
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csr, o, ob, done, idle, excen, exc, thrd, ptrmask, state, mem, shift48);
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csr, o, ob, done, idle, excen, exc, thrd, ptrmask, state, mem, shift48);
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parameter DBW = 64;
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parameter DBW = 64;
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parameter BIG = 1'b1;
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parameter BIG = 1'b1;
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parameter SUP_VECTOR = 1;
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parameter SUP_VECTOR = 1;
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parameter TRUE = 1'b1;
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parameter TRUE = 1'b1;
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parameter FALSE = 1'b0;
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parameter FALSE = 1'b0;
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parameter PTR = 20'hFFF01;
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parameter PTR = 20'hFFF01;
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input rst;
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input rst;
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input clk;
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input clk;
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input ld;
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input ld;
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input abort;
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input abort;
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input [47:0] instr;
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input [47:0] instr;
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input [63:0] a;
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input [63:0] a;
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input [63:0] b;
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input [63:0] b;
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input [63:0] c;
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input [63:0] c;
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input [31:0] pc;
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input [31:0] pc;
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input [11:0] tgt;
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input [11:0] tgt;
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input [7:0] tgt2;
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input [7:0] tgt2;
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input [5:0] ven;
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input [5:0] ven;
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input [15:0] vm;
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input [15:0] vm;
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input [31:0] sbl;
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input [31:0] sbl;
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input [31:0] sbu;
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input [31:0] sbu;
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input [63:0] csr;
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input [63:0] csr;
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output reg [63:0] o;
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output reg [63:0] o;
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output reg [63:0] ob;
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output reg [63:0] ob;
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output reg done;
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output reg done;
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output reg idle;
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output reg idle;
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input [4:0] excen;
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input [4:0] excen;
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output reg [8:0] exc;
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output reg [8:0] exc;
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input thrd;
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input thrd;
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input [63:0] ptrmask;
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input [63:0] ptrmask;
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input [1:0] state;
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input [1:0] state;
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input mem;
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input mem;
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input shift48;
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input shift48;
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integer n;
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integer n;
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reg adrDone, adrIdle;
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reg adrDone, adrIdle;
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reg [63:0] addro;
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reg [63:0] addro;
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reg [63:0] addr8;
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reg [63:0] addr8;
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wire [7:0] a8 = a[7:0];
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wire [7:0] a8 = a[7:0];
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wire [15:0] a16 = a[15:0];
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wire [15:0] a16 = a[15:0];
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wire [31:0] a32 = a[31:0];
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wire [31:0] a32 = a[31:0];
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wire [7:0] b8 = b[7:0];
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wire [7:0] b8 = b[7:0];
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wire [15:0] b16 = b[15:0];
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wire [15:0] b16 = b[15:0];
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wire [31:0] b32 = b[31:0];
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wire [31:0] b32 = b[31:0];
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wire [63:0] orb = instr[6] ? {34'd0,b[29:0]} : {50'd0,b[13:0]};
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wire [63:0] orb = instr[6] ? {34'd0,b[29:0]} : {50'd0,b[13:0]};
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wire [63:0] andb = b;//((instr[6]==1'b1) ? {34'h3FFFFFFFF,b[29:0]} : {50'h3FFFFFFFFFFFF,b[13:0]});
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wire [63:0] andb = b;//((instr[6]==1'b1) ? {34'h3FFFFFFFF,b[29:0]} : {50'h3FFFFFFFFFFFF,b[13:0]});
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wire [21:0] qimm = instr[39:18];
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wire [21:0] qimm = instr[39:18];
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wire [63:0] imm = {{45{instr[39]}},instr[39:21]};
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wire [63:0] imm = {{45{instr[39]}},instr[39:21]};
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wire [DBW-1:0] divq, rem;
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wire [DBW-1:0] divq, rem;
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wire divByZero;
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wire divByZero;
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wire [15:0] prod8;
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wire [15:0] prod8;
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wire [31:0] prod16;
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wire [31:0] prod16;
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wire [63:0] prod32;
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wire [63:0] prod32;
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wire [DBW*2-1:0] prod;
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wire [DBW*2-1:0] prod;
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wire mult_done8, mult_idle8, div_done8, div_idle8;
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wire mult_done8, mult_idle8, div_done8, div_idle8;
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wire mult_done16, mult_idle16, div_done16, div_idle16;
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wire mult_done16, mult_idle16, div_done16, div_idle16;
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wire mult_done32, mult_idle32, div_done32, div_idle32;
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wire mult_done32, mult_idle32, div_done32, div_idle32;
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wire mult_done, mult_idle, div_done, div_idle;
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wire mult_done, mult_idle, div_done, div_idle;
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wire aslo;
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wire aslo;
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wire [6:0] clzo,cloo,cpopo;
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wire [6:0] clzo,cloo,cpopo;
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wire [63:0] shftho;
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wire [63:0] shftho;
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reg [34:0] addr9;
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reg [34:0] addr9;
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function IsMul;
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function IsMul;
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input [47:0] isn;
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input [47:0] isn;
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case(isn[`INSTRUCTION_OP])
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case(isn[`INSTRUCTION_OP])
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`IVECTOR:
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`IVECTOR:
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case(isn[`INSTRUCTION_S2])
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case(isn[`INSTRUCTION_S2])
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`VMUL,`VMULS: IsMul = TRUE;
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`VMUL,`VMULS: IsMul = TRUE;
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default: IsMul = FALSE;
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default: IsMul = FALSE;
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endcase
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endcase
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`RR:
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`R2:
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case(isn[`INSTRUCTION_S2])
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case(isn[`INSTRUCTION_S2])
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`MULU,`MULSU,`MUL: IsMul = TRUE;
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`MULU,`MULSU,`MUL: IsMul = TRUE;
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`MULUH,`MULSUH,`MULH: IsMul = TRUE;
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default: IsMul = FALSE;
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default: IsMul = FALSE;
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endcase
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endcase
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`MULUI,`MULSUI,`MULI: IsMul = TRUE;
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`MULUI,`MULI: IsMul = TRUE;
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default: IsMul = FALSE;
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default: IsMul = FALSE;
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endcase
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endcase
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endfunction
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endfunction
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function IsDivmod;
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function IsDivmod;
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input [47:0] isn;
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input [47:0] isn;
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case(isn[`INSTRUCTION_OP])
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case(isn[`INSTRUCTION_OP])
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`IVECTOR:
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`IVECTOR:
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case(isn[`INSTRUCTION_S2])
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case(isn[`INSTRUCTION_S2])
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`VDIV,`VDIVS: IsDivmod = TRUE;
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`VDIV,`VDIVS: IsDivmod = TRUE;
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default: IsDivmod = FALSE;
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default: IsDivmod = FALSE;
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endcase
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endcase
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`RR:
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`R2:
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case(isn[`INSTRUCTION_S2])
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case(isn[`INSTRUCTION_S2])
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`DIVMODU,`DIVMODSU,`DIVMOD: IsDivmod = TRUE;
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`DIVU,`DIVSU,`DIV: IsDivmod = TRUE;
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`MODU,`MODSU,`MOD: IsDivmod = TRUE;
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default: IsDivmod = FALSE;
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default: IsDivmod = FALSE;
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endcase
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endcase
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`DIVUI,`DIVI,`MODI: IsDivmod = TRUE;
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`DIVUI,`DIVI,`MODI: IsDivmod = TRUE;
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default: IsDivmod = FALSE;
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default: IsDivmod = FALSE;
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endcase
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endcase
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endfunction
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endfunction
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function IsSgn;
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function IsSgn;
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input [47:0] isn;
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input [47:0] isn;
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case(isn[`INSTRUCTION_OP])
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case(isn[`INSTRUCTION_OP])
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`IVECTOR:
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`IVECTOR:
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case(isn[`INSTRUCTION_S2])
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case(isn[`INSTRUCTION_S2])
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`VMUL,`VMULS,`VDIV,`VDIVS: IsSgn = TRUE;
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`VMUL,`VMULS,`VDIV,`VDIVS: IsSgn = TRUE;
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default: IsSgn = FALSE;
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default: IsSgn = FALSE;
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endcase
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endcase
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`RR:
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`R2:
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case(isn[`INSTRUCTION_S2])
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case(isn[`INSTRUCTION_S2])
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`MUL,`DIVMOD: IsSgn = TRUE;
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`MUL,`DIV,`MOD,`MULH: IsSgn = TRUE;
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default: IsSgn = FALSE;
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default: IsSgn = FALSE;
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endcase
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endcase
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`MULI,`DIVI,`MODI: IsSgn = TRUE;
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`MULI,`DIVI,`MODI: IsSgn = TRUE;
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default: IsSgn = FALSE;
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default: IsSgn = FALSE;
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endcase
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endcase
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endfunction
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endfunction
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function IsSgnus;
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function IsSgnus;
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input [47:0] isn;
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input [47:0] isn;
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case(isn[`INSTRUCTION_OP])
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case(isn[`INSTRUCTION_OP])
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`RR:
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`R2:
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case(isn[`INSTRUCTION_S2])
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case(isn[`INSTRUCTION_S2])
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`MULSU,`DIVMODSU: IsSgnus = TRUE;
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`MULSU,`MULSUH,`DIVSU,`MODSU: IsSgnus = TRUE;
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default: IsSgnus = FALSE;
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default: IsSgnus = FALSE;
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endcase
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endcase
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default: IsSgnus = FALSE;
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default: IsSgnus = FALSE;
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endcase
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endcase
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endfunction
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endfunction
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function IsShiftAndOp;
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function IsShiftAndOp;
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input [47:0] isn;
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input [47:0] isn;
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IsShiftAndOp = FALSE;
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IsShiftAndOp = FALSE;
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endfunction
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endfunction
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wire [2:0] sz =
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wire [2:0] sz =
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instr[`INSTRUCTION_OP]==`IVECTOR ? 2'd3 :
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instr[`INSTRUCTION_OP]==`IVECTOR ? 2'd3 :
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instr[`INSTRUCTION_S2]==`R1 ? instr[18:16] : instr[23:21];
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instr[`INSTRUCTION_S2]==`R1 ? instr[18:16] : instr[23:21];
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|
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wire [63:0] bfout,shfto;
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wire [63:0] bfout,shfto;
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wire [63:0] shftob;
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wire [63:0] shftob;
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wire [63:0] shftco;
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wire [63:0] shftco;
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FT64_bitfield #(DBW) ubf1
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FT64_bitfield #(DBW) ubf1
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(
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(
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.inst(instr),
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.inst(instr),
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.a(a),
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.a(a),
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.b(b),
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.b(b),
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.c(c),
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.c(c),
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.o(bfout),
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.o(bfout),
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.masko()
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.masko()
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);
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);
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FT64_multiplier #(DBW) umult1
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FT64_multiplier #(DBW) umult1
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(
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(
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.rst(rst),
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.rst(rst),
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.clk(clk),
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.clk(clk),
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.ld(ld && IsMul(instr)),
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.ld(ld && IsMul(instr)),
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.abort(abort),
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.abort(abort),
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.sgn(IsSgn(instr)),
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.sgn(IsSgn(instr)),
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.sgnus(IsSgnus(instr)),
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.sgnus(IsSgnus(instr)),
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.a(a),
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.a(a),
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.b(b),
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.b(b),
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.o(prod),
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.o(prod),
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.done(mult_done),
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.done(mult_done),
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.idle(mult_idle)
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.idle(mult_idle)
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);
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);
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FT64_divider #(DBW) udiv1
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FT64_divider #(DBW) udiv1
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(
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(
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.rst(rst),
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.rst(rst),
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.clk(clk),
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.clk(clk),
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.ld(ld && IsDivmod(instr)),
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.ld(ld && IsDivmod(instr)),
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.abort(abort),
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.abort(abort),
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.sgn(IsSgn(instr)),
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.sgn(IsSgn(instr)),
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.sgnus(IsSgnus(instr)),
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.sgnus(IsSgnus(instr)),
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.a(a),
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.a(a),
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.b(b),
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.b(b),
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.qo(divq),
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.qo(divq),
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.ro(rem),
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.ro(rem),
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.dvByZr(divByZero),
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.dvByZr(divByZero),
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.done(div_done),
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.done(div_done),
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.idle(div_idle)
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.idle(div_idle)
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);
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);
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|
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wire [5:0] bshift = instr[31:26]==`SHIFTR ? b : {instr[30],instr[17:13]};
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wire [5:0] bshift = instr[31:26]==`SHIFTR ? b : {instr[30],instr[17:13]};
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|
|
FT64_shift ushft1
|
FT64_shift ushft1
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(
|
(
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.instr(instr),
|
.instr(instr),
|
.a(a),
|
.a(a),
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.b(bshift),
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.b(bshift),
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.res(shfto),
|
.res(shfto),
|
.ov(aslo)
|
.ov(aslo)
|
);
|
);
|
|
|
FT64_shifth ushfthL
|
FT64_shifth ushfthL
|
(
|
(
|
.instr(instr),
|
.instr(instr),
|
.a(a[31:0]),
|
.a(a[31:0]),
|
.b(bshift),
|
.b(bshift),
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.res(shftho[31:0]),
|
.res(shftho[31:0]),
|
.ov()
|
.ov()
|
);
|
);
|
|
|
FT64_shifth ushfthH
|
FT64_shifth ushfthH
|
(
|
(
|
.instr(instr),
|
.instr(instr),
|
.a(a[63:32]),
|
.a(a[63:32]),
|
.b(b[63:32]),
|
.b(b[63:32]),
|
.res(shftho[63:32]),
|
.res(shftho[63:32]),
|
.ov()
|
.ov()
|
);
|
);
|
|
|
FT64_shiftc ushftc0
|
FT64_shiftc ushftc0
|
(
|
(
|
.instr(instr),
|
.instr(instr),
|
.a(a[15:0]),
|
.a(a[15:0]),
|
.b(bshift),
|
.b(bshift),
|
.res(shftco[15:0]),
|
.res(shftco[15:0]),
|
.ov()
|
.ov()
|
);
|
);
|
|
|
FT64_shiftc ushftc1
|
FT64_shiftc ushftc1
|
(
|
(
|
.instr(instr),
|
.instr(instr),
|
.a(a[31:16]),
|
.a(a[31:16]),
|
.b(b[31:16]),
|
.b(b[31:16]),
|
.res(shftco[31:16]),
|
.res(shftco[31:16]),
|
.ov()
|
.ov()
|
);
|
);
|
|
|
FT64_shiftc ushftc2
|
FT64_shiftc ushftc2
|
(
|
(
|
.instr(instr),
|
.instr(instr),
|
.a(a[47:32]),
|
.a(a[47:32]),
|
.b(b[47:32]),
|
.b(b[47:32]),
|
.res(shftco[47:32]),
|
.res(shftco[47:32]),
|
.ov()
|
.ov()
|
);
|
);
|
|
|
FT64_shiftc ushftc3
|
FT64_shiftc ushftc3
|
(
|
(
|
.instr(instr),
|
.instr(instr),
|
.a(a[63:48]),
|
.a(a[63:48]),
|
.b(b[63:48]),
|
.b(b[63:48]),
|
.res(shftco[63:48]),
|
.res(shftco[63:48]),
|
.ov()
|
.ov()
|
);
|
);
|
|
|
FT64_shiftb ushftb0
|
FT64_shiftb ushftb0
|
(
|
(
|
.instr(instr),
|
.instr(instr),
|
.a(a[7:0]),
|
.a(a[7:0]),
|
.b(bshift),
|
.b(bshift),
|
.res(shftob[7:0]),
|
.res(shftob[7:0]),
|
.ov()
|
.ov()
|
);
|
);
|
|
|
FT64_shiftb ushftb1
|
FT64_shiftb ushftb1
|
(
|
(
|
.instr(instr),
|
.instr(instr),
|
.a(a[15:8]),
|
.a(a[15:8]),
|
.b(b[15:8]),
|
.b(b[15:8]),
|
.res(shftob[15:8]),
|
.res(shftob[15:8]),
|
.ov()
|
.ov()
|
);
|
);
|
|
|
FT64_shiftb ushftb2
|
FT64_shiftb ushftb2
|
(
|
(
|
.instr(instr),
|
.instr(instr),
|
.a(a[23:16]),
|
.a(a[23:16]),
|
.b(b[23:16]),
|
.b(b[23:16]),
|
.res(shftob[23:16]),
|
.res(shftob[23:16]),
|
.ov()
|
.ov()
|
);
|
);
|
|
|
FT64_shiftb ushftb3
|
FT64_shiftb ushftb3
|
(
|
(
|
.instr(instr),
|
.instr(instr),
|
.a(a[31:24]),
|
.a(a[31:24]),
|
.b(b[31:24]),
|
.b(b[31:24]),
|
.res(shftob[31:24]),
|
.res(shftob[31:24]),
|
.ov()
|
.ov()
|
);
|
);
|
|
|
FT64_shiftb ushftb4
|
FT64_shiftb ushftb4
|
(
|
(
|
.instr(instr),
|
.instr(instr),
|
.a(a[39:32]),
|
.a(a[39:32]),
|
.b(b[39:32]),
|
.b(b[39:32]),
|
.res(shftob[39:32]),
|
.res(shftob[39:32]),
|
.ov()
|
.ov()
|
);
|
);
|
|
|
FT64_shiftb ushftb5
|
FT64_shiftb ushftb5
|
(
|
(
|
.instr(instr),
|
.instr(instr),
|
.a(a[47:40]),
|
.a(a[47:40]),
|
.b(b[47:40]),
|
.b(b[47:40]),
|
.res(shftob[47:40]),
|
.res(shftob[47:40]),
|
.ov()
|
.ov()
|
);
|
);
|
|
|
FT64_shiftb ushftb6
|
FT64_shiftb ushftb6
|
(
|
(
|
.instr(instr),
|
.instr(instr),
|
.a(a[55:48]),
|
.a(a[55:48]),
|
.b(b[55:48]),
|
.b(b[55:48]),
|
.res(shftob[55:48]),
|
.res(shftob[55:48]),
|
.ov()
|
.ov()
|
);
|
);
|
|
|
FT64_shiftb ushftb7
|
FT64_shiftb ushftb7
|
(
|
(
|
.instr(instr),
|
.instr(instr),
|
.a(a[63:56]),
|
.a(a[63:56]),
|
.b(b[63:56]),
|
.b(b[63:56]),
|
.res(shftob[63:56]),
|
.res(shftob[63:56]),
|
.ov()
|
.ov()
|
);
|
);
|
|
|
cntlz64 uclz1
|
cntlz64 uclz1
|
(
|
(
|
.i(sz==2'd0 ? {56'hFFFFFFFFFFFFFF,a[7:0]} :
|
.i(sz==2'd0 ? {56'hFFFFFFFFFFFFFF,a[7:0]} :
|
sz==2'd1 ? {48'hFFFFFFFFFFFF,a[15:0]} :
|
sz==2'd1 ? {48'hFFFFFFFFFFFF,a[15:0]} :
|
sz==2'd2 ? {32'hFFFFFFFF,a[31:0]} : a),
|
sz==2'd2 ? {32'hFFFFFFFF,a[31:0]} : a),
|
.o(clzo)
|
.o(clzo)
|
);
|
);
|
|
|
cntlo64 uclo1
|
cntlo64 uclo1
|
(
|
(
|
.i(sz==2'd0 ? a[7:0] : sz==2'd1 ? a[15:0] : sz==2'd2 ? a[31:0] : a),
|
.i(sz==2'd0 ? a[7:0] : sz==2'd1 ? a[15:0] : sz==2'd2 ? a[31:0] : a),
|
.o(cloo)
|
.o(cloo)
|
);
|
);
|
|
|
cntpop64 ucpop1
|
cntpop64 ucpop1
|
(
|
(
|
.i(sz==2'd0 ? a[7:0] : sz==2'd1 ? a[15:0] : sz==2'd2 ? a[31:0] : a),
|
.i(sz==2'd0 ? a[7:0] : sz==2'd1 ? a[15:0] : sz==2'd2 ? a[31:0] : a),
|
.o(cpopo)
|
.o(cpopo)
|
);
|
);
|
|
|
wire [7:0] bcdaddo,bcdsubo;
|
wire [7:0] bcdaddo,bcdsubo;
|
wire [15:0] bcdmulo;
|
wire [15:0] bcdmulo;
|
BCDAdd ubcd1 (1'b0,a,b,bcdaddo);
|
BCDAdd ubcd1 (1'b0,a,b,bcdaddo);
|
BCDSub ubcd2 (1'b0,a,b,bcdsubo);
|
BCDSub ubcd2 (1'b0,a,b,bcdsubo);
|
BCDMul2 ubcd3 (a,b,bcdmulo);
|
BCDMul2 ubcd3 (a,b,bcdmulo);
|
|
|
wire [7:0] s8 = a[7:0] + b[7:0];
|
wire [7:0] s8 = a[7:0] + b[7:0];
|
wire [15:0] s16 = a[15:0] + b[15:0];
|
wire [15:0] s16 = a[15:0] + b[15:0];
|
wire [31:0] s32 = a[31:0] + b[31:0];
|
wire [31:0] s32 = a[31:0] + b[31:0];
|
wire [7:0] d8 = a[7:0] - b[7:0];
|
wire [7:0] d8 = a[7:0] - b[7:0];
|
wire [15:0] d16 = a[15:0] - b[15:0];
|
wire [15:0] d16 = a[15:0] - b[15:0];
|
wire [31:0] d32 = a[31:0] - b[31:0];
|
wire [31:0] d32 = a[31:0] - b[31:0];
|
wire [63:0] and64 = a & b;
|
wire [63:0] and64 = a & b;
|
wire [63:0] or64 = a | b;
|
wire [63:0] or64 = a | b;
|
wire [63:0] xor64 = a ^ b;
|
wire [63:0] xor64 = a ^ b;
|
wire [63:0] redor64 = {63'd0,|a};
|
wire [63:0] redor64 = {63'd0,|a};
|
wire [63:0] redor32 = {63'd0,|a[31:0]};
|
wire [63:0] redor32 = {63'd0,|a[31:0]};
|
wire [63:0] redor16 = {63'd0,|a[15:0]};
|
wire [63:0] redor16 = {63'd0,|a[15:0]};
|
wire [63:0] redor8 = {63'd0,|a[7:0]};
|
wire [63:0] redor8 = {63'd0,|a[7:0]};
|
wire [63:0] zxb10 = {54'd0,b[9:0]};
|
wire [63:0] zxb10 = {54'd0,b[9:0]};
|
wire [63:0] sxb10 = {{54{b[9]}},b[9:0]};
|
wire [63:0] sxb10 = {{54{b[9]}},b[9:0]};
|
wire [63:0] zxb26 = {38'd0,instr[47:32],instr[27:18]};
|
wire [63:0] zxb26 = {38'd0,instr[47:32],instr[27:18]};
|
wire [63:0] sxb26 = {{38{instr[47]}},instr[47:32],instr[27:18]};
|
wire [63:0] sxb26 = {{38{instr[47]}},instr[47:32],instr[27:18]};
|
reg [15:0] mask;
|
reg [15:0] mask;
|
wire [4:0] cpopom;
|
wire [4:0] cpopom;
|
wire signed [63:0] as = a;
|
wire signed [63:0] as = a;
|
wire signed [63:0] bs = b;
|
wire signed [63:0] bs = b;
|
wire signed [63:0] cs = c;
|
wire signed [63:0] cs = c;
|
|
|
always @*
|
always @*
|
for (n = 0; n < 16; n = n + 1)
|
for (n = 0; n < 16; n = n + 1)
|
if (n <= ven)
|
if (n <= ven)
|
mask[n] = 1'b1;
|
mask[n] = 1'b1;
|
else
|
else
|
mask[n] = 1'b0;
|
mask[n] = 1'b0;
|
|
|
cntpop16 ucpop2
|
cntpop16 ucpop2
|
(
|
(
|
.i(vm & mask),
|
.i(vm & mask),
|
.o(cpopom)
|
.o(cpopom)
|
);
|
);
|
|
|
wire [5:0] lsto, fsto;
|
wire [5:0] lsto, fsto;
|
ffz24 uffo1
|
ffz24 uffo1
|
(
|
(
|
.i(~{8'h00,a[15:0]}),
|
.i(~{8'h00,a[15:0]}),
|
.o(lsto)
|
.o(lsto)
|
);
|
);
|
|
|
flz24 uflo1
|
flz24 uflo1
|
(
|
(
|
.i(~{8'h00,a[15:0]}),
|
.i(~{8'h00,a[15:0]}),
|
.o(fsto)
|
.o(fsto)
|
);
|
);
|
|
|
wire [DBW-1:0] bmmo;
|
wire [DBW-1:0] bmmo;
|
FT64_BMM ubmm1
|
FT64_BMM ubmm1
|
(
|
(
|
.op(1'b0),
|
.op(1'b0),
|
.a(a),
|
.a(a),
|
.b(b),
|
.b(b),
|
.o(bmmo)
|
.o(bmmo)
|
);
|
);
|
|
|
always @*
|
always @*
|
begin
|
begin
|
case(instr[`INSTRUCTION_OP])
|
case(instr[`INSTRUCTION_OP])
|
`IVECTOR:
|
`IVECTOR:
|
if (SUP_VECTOR)
|
if (SUP_VECTOR)
|
case(instr[`INSTRUCTION_S2])
|
case(instr[`INSTRUCTION_S2])
|
`VABS: o[63:0] = a[63] ? -a : a;
|
`VABS: o[63:0] = a[63] ? -a : a;
|
`VSIGN: o[63:0] = a[63] ? 64'hFFFFFFFFFFFFFFFF : a==64'd0 ? 64'd0 : 64'd1;
|
`VSIGN: o[63:0] = a[63] ? 64'hFFFFFFFFFFFFFFFF : a==64'd0 ? 64'd0 : 64'd1;
|
`VMxx:
|
`VMxx:
|
case(instr[25:23])
|
case(instr[25:23])
|
`VMAND: o[63:0] = and64;
|
`VMAND: o[63:0] = and64;
|
`VMOR: o[63:0] = or64;
|
`VMOR: o[63:0] = or64;
|
`VMXOR: o[63:0] = xor64;
|
`VMXOR: o[63:0] = xor64;
|
`VMXNOR: o[63:0] = ~(xor64);
|
`VMXNOR: o[63:0] = ~(xor64);
|
`VMPOP: o[63:0] = {57'd0,cpopo};
|
`VMPOP: o[63:0] = {57'd0,cpopo};
|
`VMFILL: for (n = 0; n < 64; n = n + 1)
|
`VMFILL: for (n = 0; n < 64; n = n + 1)
|
o[n] = (n < a);
|
o[n] = (n < a);
|
// Change the following when VL > 16
|
// Change the following when VL > 16
|
`VMFIRST: o[63:0] = fsto==5'd31 ? 64'd64 : fsto;
|
`VMFIRST: o[63:0] = fsto==5'd31 ? 64'd64 : fsto;
|
`VMLAST: o[63:0] = lsto==5'd31 ? 64'd64 : lsto;
|
`VMLAST: o[63:0] = lsto==5'd31 ? 64'd64 : lsto;
|
endcase
|
endcase
|
`VADD,`VADDS: o[63:0] = vm[ven] ? a + b : c;
|
`VADD,`VADDS: o[63:0] = vm[ven] ? a + b : c;
|
`VSUB,`VSUBS: o[63:0] = vm[ven] ? a - b : c;
|
`VSUB,`VSUBS: o[63:0] = vm[ven] ? a - b : c;
|
`VMUL,`VMULS: o[63:0] = vm[ven] ? prod[DBW-1:0] : c;
|
`VMUL,`VMULS: o[63:0] = vm[ven] ? prod[DBW-1:0] : c;
|
`VDIV,`VDIVS: o[63:0] = BIG ? (vm[ven] ? divq : c) : 64'hCCCCCCCCCCCCCCCC;
|
`VDIV,`VDIVS: o[63:0] = BIG ? (vm[ven] ? divq : c) : 64'hCCCCCCCCCCCCCCCC;
|
`VAND,`VANDS: o[63:0] = vm[ven] ? a & b : c;
|
`VAND,`VANDS: o[63:0] = vm[ven] ? a & b : c;
|
`VOR,`VORS: o[63:0] = vm[ven] ? a | b : c;
|
`VOR,`VORS: o[63:0] = vm[ven] ? a | b : c;
|
`VXOR,`VXORS: o[63:0] = vm[ven] ? a ^ b : c;
|
`VXOR,`VXORS: o[63:0] = vm[ven] ? a ^ b : c;
|
`VCNTPOP: o[63:0] = {57'd0,cpopo};
|
`VCNTPOP: o[63:0] = {57'd0,cpopo};
|
`VSHLV: o[63:0] = a; // no masking here
|
`VSHLV: o[63:0] = a; // no masking here
|
`VSHRV: o[63:0] = a;
|
`VSHRV: o[63:0] = a;
|
`VCMPRSS: o[63:0] = a;
|
`VCMPRSS: o[63:0] = a;
|
`VCIDX: o[63:0] = a * ven;
|
`VCIDX: o[63:0] = a * ven;
|
`VSCAN: o[63:0] = a * (cpopom==0 ? 0 : cpopom-1);
|
`VSCAN: o[63:0] = a * (cpopom==0 ? 0 : cpopom-1);
|
`VSxx,`VSxxS,
|
`VSxx,`VSxxS,
|
`VSxxb,`VSxxSb:
|
`VSxxb,`VSxxSb:
|
case({instr[26],instr[20:19]})
|
case({instr[26],instr[20:19]})
|
`VSEQ: begin
|
`VSEQ: begin
|
o[63:0] = c;
|
o[63:0] = c;
|
o[ven] = vm[ven] ? a==b : c[ven];
|
o[ven] = vm[ven] ? a==b : c[ven];
|
end
|
end
|
`VSNE: begin
|
`VSNE: begin
|
o[63:0] = c;
|
o[63:0] = c;
|
o[ven] = vm[ven] ? a!=b : c[ven];
|
o[ven] = vm[ven] ? a!=b : c[ven];
|
end
|
end
|
`VSLT: begin
|
`VSLT: begin
|
o[63:0] = c;
|
o[63:0] = c;
|
o[ven] = vm[ven] ? $signed(a) < $signed(b) : c[ven];
|
o[ven] = vm[ven] ? $signed(a) < $signed(b) : c[ven];
|
end
|
end
|
`VSGE: begin
|
`VSGE: begin
|
o[63:0] = c;
|
o[63:0] = c;
|
o[ven] = vm[ven] ? $signed(a) >= $signed(b) : c[ven];
|
o[ven] = vm[ven] ? $signed(a) >= $signed(b) : c[ven];
|
end
|
end
|
`VSLE: begin
|
`VSLE: begin
|
o[63:0] = c;
|
o[63:0] = c;
|
o[ven] = vm[ven] ? $signed(a) <= $signed(b) : c[ven];
|
o[ven] = vm[ven] ? $signed(a) <= $signed(b) : c[ven];
|
end
|
end
|
`VSGT: begin
|
`VSGT: begin
|
o[63:0] = c;
|
o[63:0] = c;
|
o[ven] = vm[ven] ? $signed(a) > $signed(b) : c[ven];
|
o[ven] = vm[ven] ? $signed(a) > $signed(b) : c[ven];
|
end
|
end
|
default: o[63:0] = 64'hCCCCCCCCCCCCCCCC;
|
default: o[63:0] = 64'hCCCCCCCCCCCCCCCC;
|
endcase
|
endcase
|
`VSxxU,`VSxxSU,
|
`VSxxU,`VSxxSU,
|
`VSxxUb,`VSxxSUb:
|
`VSxxUb,`VSxxSUb:
|
case({instr[26],instr[20:19]})
|
case({instr[26],instr[20:19]})
|
`VSEQ: begin
|
`VSEQ: begin
|
o[63:0] = c;
|
o[63:0] = c;
|
o[ven] = vm[ven] ? a==b : c[ven];
|
o[ven] = vm[ven] ? a==b : c[ven];
|
end
|
end
|
`VSNE: begin
|
`VSNE: begin
|
o[63:0] = c;
|
o[63:0] = c;
|
o[ven] = vm[ven] ? a!=b : c[ven];
|
o[ven] = vm[ven] ? a!=b : c[ven];
|
end
|
end
|
`VSLT: begin
|
`VSLT: begin
|
o[63:0] = c;
|
o[63:0] = c;
|
o[ven] = vm[ven] ? a < b : c[ven];
|
o[ven] = vm[ven] ? a < b : c[ven];
|
end
|
end
|
`VSGE: begin
|
`VSGE: begin
|
o[63:0] = c;
|
o[63:0] = c;
|
o[ven] = vm[ven] ? a >= b : c[ven];
|
o[ven] = vm[ven] ? a >= b : c[ven];
|
end
|
end
|
`VSLE: begin
|
`VSLE: begin
|
o[63:0] = c;
|
o[63:0] = c;
|
o[ven] = vm[ven] ? a <= b : c[ven];
|
o[ven] = vm[ven] ? a <= b : c[ven];
|
end
|
end
|
`VSGT: begin
|
`VSGT: begin
|
o[63:0] = c;
|
o[63:0] = c;
|
o[ven] = vm[ven] ? a > b : c[ven];
|
o[ven] = vm[ven] ? a > b : c[ven];
|
end
|
end
|
default: o[63:0] = 64'hCCCCCCCCCCCCCCCC;
|
default: o[63:0] = 64'hCCCCCCCCCCCCCCCC;
|
endcase
|
endcase
|
`VBITS2V: o[63:0] = vm[ven] ? a[ven] : c;
|
`VBITS2V: o[63:0] = vm[ven] ? a[ven] : c;
|
`V2BITS: begin
|
`V2BITS: begin
|
o[63:0] = b;
|
o[63:0] = b;
|
o[ven] = vm[ven] ? a[0] : b[ven];
|
o[ven] = vm[ven] ? a[0] : b[ven];
|
end
|
end
|
`VSHL,`VSHR,`VASR: o[63:0] = BIG ? shfto : 64'hCCCCCCCCCCCCCCCC;
|
`VSHL,`VSHR,`VASR: o[63:0] = BIG ? shfto : 64'hCCCCCCCCCCCCCCCC;
|
`VXCHG: o[63:0] = vm[ven] ? b : a;
|
`VXCHG: o[63:0] = vm[ven] ? b : a;
|
default: o[63:0] = 64'hCCCCCCCCCCCCCCCC;
|
default: o[63:0] = 64'hCCCCCCCCCCCCCCCC;
|
endcase
|
endcase
|
else
|
else
|
o[63:0] <= 64'hCCCCCCCCCCCCCCCC;
|
o[63:0] <= 64'hCCCCCCCCCCCCCCCC;
|
`R2:
|
`R2:
|
if (instr[6])
|
if (instr[6])
|
case(instr[47:42])
|
case(instr[47:42])
|
`SHIFTR:
|
`SHIFTR:
|
begin
|
begin
|
case(instr[35:33])
|
case(instr[35:33])
|
`ASL,`ASR,`ROL,`ROR:
|
`ASL,`ASR,`ROL,`ROR:
|
case(instr[32:30]) // size
|
case(instr[32:30]) // size
|
3'd0: addr8 = {{56{shftob[7]}},shftob[7:0]};
|
3'd0: addr8 = {{56{shftob[7]}},shftob[7:0]};
|
3'd1: addr8 = {{48{shftob[15]}},shftco[15:0]};
|
3'd1: addr8 = {{48{shftob[15]}},shftco[15:0]};
|
3'd2: addr8 = {{32{shftho[31]}},shftho[31:0]};
|
3'd2: addr8 = {{32{shftho[31]}},shftho[31:0]};
|
3'd3,3'd7: addr8 = shfto;
|
3'd3,3'd7: addr8 = shfto;
|
3'd4: addr8 = shftob;
|
3'd4: addr8 = shftob;
|
3'd5: addr8 = shftco;
|
3'd5: addr8 = shftco;
|
3'd6: addr8 = shftho;
|
3'd6: addr8 = shftho;
|
endcase
|
endcase
|
`SHL,`SHR:
|
`SHL,`SHR:
|
case(instr[32:30]) // size
|
case(instr[32:30]) // size
|
3'd0: addr8 = {56'd0,shftob[7:0]};
|
3'd0: addr8 = {56'd0,shftob[7:0]};
|
3'd1: addr8 = {48'd0,shftco[15:0]};
|
3'd1: addr8 = {48'd0,shftco[15:0]};
|
3'd2: addr8 = {32'd0,shftho[31:0]};
|
3'd2: addr8 = {32'd0,shftho[31:0]};
|
3'd3,3'd7: addr8 = shfto;
|
3'd3,3'd7: addr8 = shfto;
|
3'd4: addr8 = shftob;
|
3'd4: addr8 = shftob;
|
3'd5: addr8 = shftco;
|
3'd5: addr8 = shftco;
|
3'd6: addr8 = shftho;
|
3'd6: addr8 = shftho;
|
endcase
|
endcase
|
default: o[63:0] = 64'hDCDCDCDCDCDCDCDC;
|
default: o[63:0] = 64'hDCDCDCDCDCDCDCDC;
|
endcase
|
endcase
|
case(instr[35:33])
|
case(instr[35:33])
|
`ASL,`ASR,`SHL,`SHR,`ROL,`ROR:
|
`ASL,`ASR,`SHL,`SHR,`ROL,`ROR:
|
o[63:0] = addr9;
|
o[63:0] = addr9;
|
default: o[63:0] = 64'hDCDCDCDCDCDCDCDC;
|
default: o[63:0] = 64'hDCDCDCDCDCDCDCDC;
|
endcase
|
endcase
|
end
|
end
|
`MIN:
|
`MIN:
|
case(instr[30:28])
|
case(instr[30:28])
|
3'd3:
|
3'd3:
|
if (as < bs && as < cs)
|
if (as < bs && as < cs)
|
o[63:0] = as;
|
o[63:0] = as;
|
else if (bs < cs)
|
else if (bs < cs)
|
o[63:0] = bs;
|
o[63:0] = bs;
|
else
|
else
|
o[63:0] = cs;
|
o[63:0] = cs;
|
endcase
|
endcase
|
endcase
|
endcase
|
else
|
else
|
case(instr[`INSTRUCTION_S2])
|
case(instr[`INSTRUCTION_S2])
|
`BCD:
|
`BCD:
|
case(instr[`INSTRUCTION_S1])
|
case(instr[`INSTRUCTION_S1])
|
`BCDADD: o[63:0] = BIG ? bcdaddo : 64'hCCCCCCCCCCCCCCCC;
|
`BCDADD: o[63:0] = BIG ? bcdaddo : 64'hCCCCCCCCCCCCCCCC;
|
`BCDSUB: o[63:0] = BIG ? bcdsubo : 64'hCCCCCCCCCCCCCCCC;
|
`BCDSUB: o[63:0] = BIG ? bcdsubo : 64'hCCCCCCCCCCCCCCCC;
|
`BCDMUL: o[63:0] = BIG ? bcdmulo : 64'hCCCCCCCCCCCCCCCC;
|
`BCDMUL: o[63:0] = BIG ? bcdmulo : 64'hCCCCCCCCCCCCCCCC;
|
default: o[63:0] = 64'hDEADDEADDEADDEAD;
|
default: o[63:0] = 64'hDEADDEADDEADDEAD;
|
endcase
|
endcase
|
`MOV: begin
|
`MOV: begin
|
o[63:0] = a;
|
o[63:0] = a;
|
end
|
end
|
`VMOV: o[63:0] = a;
|
`VMOV: o[63:0] = a;
|
`R1:
|
`R1:
|
case(instr[`INSTRUCTION_S1])
|
case(instr[`INSTRUCTION_S1])
|
`CNTLZ: o[63:0] = BIG ? {57'd0,clzo} : 64'hCCCCCCCCCCCCCCCC;
|
`CNTLZ: o[63:0] = BIG ? {57'd0,clzo} : 64'hCCCCCCCCCCCCCCCC;
|
`CNTLO: o[63:0] = BIG ? {57'd0,cloo} : 64'hCCCCCCCCCCCCCCCC;
|
`CNTLO: o[63:0] = BIG ? {57'd0,cloo} : 64'hCCCCCCCCCCCCCCCC;
|
`CNTPOP: o[63:0] = BIG ? {57'd0,cpopo} : 64'hCCCCCCCCCCCCCCCC;
|
`CNTPOP: o[63:0] = BIG ? {57'd0,cpopo} : 64'hCCCCCCCCCCCCCCCC;
|
`ABS: case(sz)
|
`ABS: case(sz)
|
2'd0: o[63:0] = BIG ? (a[7] ? -a[7:0] : a[7:0]) : 64'hCCCCCCCCCCCCCCCC;
|
2'd0: o[63:0] = BIG ? (a[7] ? -a[7:0] : a[7:0]) : 64'hCCCCCCCCCCCCCCCC;
|
2'd1: o[63:0] = BIG ? (a[15] ? -a[15:0] : a[15:0]) : 64'hCCCCCCCCCCCCCCCC;
|
2'd1: o[63:0] = BIG ? (a[15] ? -a[15:0] : a[15:0]) : 64'hCCCCCCCCCCCCCCCC;
|
2'd2: o[63:0] = BIG ? (a[31] ? -a[31:0] : a[31:0]) : 64'hCCCCCCCCCCCCCCCC;
|
2'd2: o[63:0] = BIG ? (a[31] ? -a[31:0] : a[31:0]) : 64'hCCCCCCCCCCCCCCCC;
|
2'd3: o[63:0] = BIG ? (a[63] ? -a : a) : 64'hCCCCCCCCCCCCCCCC;
|
2'd3: o[63:0] = BIG ? (a[63] ? -a : a) : 64'hCCCCCCCCCCCCCCCC;
|
endcase
|
endcase
|
`NOT: case(sz)
|
`NOT: case(sz)
|
2'd0: o[63:0] = ~|a[7:0];
|
2'd0: o[63:0] = ~|a[7:0];
|
2'd1: o[63:0] = ~|a[15:0];
|
2'd1: o[63:0] = ~|a[15:0];
|
2'd2: o[63:0] = ~|a[31:0];
|
2'd2: o[63:0] = ~|a[31:0];
|
2'd3: o[63:0] = ~|a[63:0];
|
2'd3: o[63:0] = ~|a[63:0];
|
endcase
|
endcase
|
`REDOR: case(sz)
|
`REDOR: case(sz)
|
2'd0: o[63:0] = redor8;
|
2'd0: o[63:0] = redor8;
|
2'd1: o[63:0] = redor16;
|
2'd1: o[63:0] = redor16;
|
2'd2: o[63:0] = redor32;
|
2'd2: o[63:0] = redor32;
|
2'd3: o[63:0] = redor64;
|
2'd3: o[63:0] = redor64;
|
endcase
|
endcase
|
`ZXH: o[63:0] = {32'd0,a[31:0]};
|
`ZXH: o[63:0] = {32'd0,a[31:0]};
|
`ZXC: o[63:0] = {48'd0,a[15:0]};
|
`ZXC: o[63:0] = {48'd0,a[15:0]};
|
`ZXB: o[63:0] = {56'd0,a[7:0]};
|
`ZXB: o[63:0] = {56'd0,a[7:0]};
|
`SXH: o[63:0] = {{32{a[31]}},a[31:0]};
|
`SXH: o[63:0] = {{32{a[31]}},a[31:0]};
|
`SXC: o[63:0] = {{48{a[15]}},a[15:0]};
|
`SXC: o[63:0] = {{48{a[15]}},a[15:0]};
|
`SXB: o[63:0] = {{56{a[7]}},a[7:0]};
|
`SXB: o[63:0] = {{56{a[7]}},a[7:0]};
|
// 5'h1C: o[63:0] = tmem[a[9:0]];
|
// 5'h1C: o[63:0] = tmem[a[9:0]];
|
default: o = 64'hDEADDEADDEADDEAD;
|
default: o = 64'hDEADDEADDEADDEAD;
|
endcase
|
endcase
|
`BMM: o[63:0] = BIG ? bmmo : 64'hCCCCCCCCCCCCCCCC;
|
`BMM: o[63:0] = BIG ? bmmo : 64'hCCCCCCCCCCCCCCCC;
|
`SHIFT31,
|
`SHIFT31,
|
`SHIFT63,
|
`SHIFT63,
|
`SHIFTR:
|
`SHIFTR:
|
begin
|
begin
|
if (instr[25:23]==`SHL)
|
if (instr[25:23]==`SHL)
|
o[63:0] = shfto;
|
o[63:0] = shfto;
|
else
|
else
|
o[63:0] = BIG ? shfto : 64'hCCCCCCCCCCCCCCCC;
|
o[63:0] = BIG ? shfto : 64'hCCCCCCCCCCCCCCCC;
|
$display("BIG=%d",BIG);
|
$display("BIG=%d",BIG);
|
if(!BIG)
|
if(!BIG)
|
$stop;
|
$stop;
|
end
|
end
|
`ADD: case(sz)
|
`ADD: case(sz)
|
3'd0,3'd4:
|
3'd0,3'd4:
|
begin
|
begin
|
o[7:0] = a[7:0] + b[7:0];
|
o[7:0] = a[7:0] + b[7:0];
|
o[15:8] = a[15:8] + b[15:8];
|
o[15:8] = a[15:8] + b[15:8];
|
o[23:16] = a[23:16] + b[23:16];
|
o[23:16] = a[23:16] + b[23:16];
|
o[31:24] = a[31:24] + b[31:24];
|
o[31:24] = a[31:24] + b[31:24];
|
o[39:32] = a[39:32] + b[39:32];
|
o[39:32] = a[39:32] + b[39:32];
|
o[47:40] = a[47:40] + b[47:40];
|
o[47:40] = a[47:40] + b[47:40];
|
o[55:48] = a[55:48] + b[55:48];
|
o[55:48] = a[55:48] + b[55:48];
|
o[63:56] = a[63:56] + b[63:56];
|
o[63:56] = a[63:56] + b[63:56];
|
end
|
end
|
3'd1,3'd5:
|
3'd1,3'd5:
|
begin
|
begin
|
o[15:0] = a[15:0] + b[15:0];
|
o[15:0] = a[15:0] + b[15:0];
|
o[31:16] = a[31:16] + b[31:16];
|
o[31:16] = a[31:16] + b[31:16];
|
o[47:32] = a[47:32] + b[47:32];
|
o[47:32] = a[47:32] + b[47:32];
|
o[63:48] = a[63:48] + b[63:48];
|
o[63:48] = a[63:48] + b[63:48];
|
end
|
end
|
3'd2,3'd6:
|
3'd2,3'd6:
|
begin
|
begin
|
o[31:0] = a[31:0] + b[31:0];
|
o[31:0] = a[31:0] + b[31:0];
|
o[63:32] = a[63:32] + b[63:32];
|
o[63:32] = a[63:32] + b[63:32];
|
end
|
end
|
3'd3,3'd7:
|
3'd3,3'd7:
|
begin
|
begin
|
o[63:0] = a + b;
|
o[63:0] = a + b;
|
end
|
end
|
endcase
|
endcase
|
`SUB: case(sz)
|
`SUB: case(sz)
|
3'd0,3'd4:
|
3'd0,3'd4:
|
begin
|
begin
|
o[7:0] = a[7:0] - b[7:0];
|
o[7:0] = a[7:0] - b[7:0];
|
o[15:8] = a[15:8] - b[15:8];
|
o[15:8] = a[15:8] - b[15:8];
|
o[23:16] = a[23:16] - b[23:16];
|
o[23:16] = a[23:16] - b[23:16];
|
o[31:24] = a[31:24] - b[31:24];
|
o[31:24] = a[31:24] - b[31:24];
|
o[39:32] = a[39:32] - b[39:32];
|
o[39:32] = a[39:32] - b[39:32];
|
o[47:40] = a[47:40] - b[47:40];
|
o[47:40] = a[47:40] - b[47:40];
|
o[55:48] = a[55:48] - b[55:48];
|
o[55:48] = a[55:48] - b[55:48];
|
o[63:56] = a[63:56] - b[63:56];
|
o[63:56] = a[63:56] - b[63:56];
|
end
|
end
|
3'd1,3'd5:
|
3'd1,3'd5:
|
begin
|
begin
|
o[15:0] = a[15:0] - b[15:0];
|
o[15:0] = a[15:0] - b[15:0];
|
o[31:16] = a[31:16] - b[31:16];
|
o[31:16] = a[31:16] - b[31:16];
|
o[47:32] = a[47:32] - b[47:32];
|
o[47:32] = a[47:32] - b[47:32];
|
o[63:48] = a[63:48] - b[63:48];
|
o[63:48] = a[63:48] - b[63:48];
|
end
|
end
|
3'd2,3'd6:
|
3'd2,3'd6:
|
begin
|
begin
|
o[31:0] = a[31:0] - b[31:0];
|
o[31:0] = a[31:0] - b[31:0];
|
o[63:32] = a[63:32] - b[63:32];
|
o[63:32] = a[63:32] - b[63:32];
|
end
|
end
|
3'd3,3'd7:
|
3'd3,3'd7:
|
begin
|
begin
|
o[63:0] = a - b;
|
o[63:0] = a - b;
|
end
|
end
|
endcase
|
endcase
|
`SLT: tskSlt(instr,instr[25:23],a,b,o);
|
`SLT: tskSlt(instr,instr[25:23],a,b,o);
|
`SLTU: tskSltu(instr,instr[25:23],a,b,o);
|
`SLTU: tskSltu(instr,instr[25:23],a,b,o);
|
`SLE: tskSle(instr,instr[25:23],a,b,o);
|
`SLE: tskSle(instr,instr[25:23],a,b,o);
|
`SLEU: tskSleu(instr,instr[25:23],a,b,o);
|
`SLEU: tskSleu(instr,instr[25:23],a,b,o);
|
`AND: o[63:0] = and64;
|
`AND: o[63:0] = and64;
|
`OR: o[63:0] = or64;
|
`OR: o[63:0] = or64;
|
`XOR: o[63:0] = xor64;
|
`XOR: o[63:0] = xor64;
|
`NAND: o[63:0] = ~and64;
|
`NAND: o[63:0] = ~and64;
|
`NOR: o[63:0] = ~or64;
|
`NOR: o[63:0] = ~or64;
|
`XNOR: o[63:0] = ~xor64;
|
`XNOR: o[63:0] = ~xor64;
|
`SEI: o[63:0] = a | instr[21:16];
|
`SEI: o[63:0] = a | instr[21:16];
|
`RTI: o[63:0] = a | instr[21:16];
|
`RTI: o[63:0] = a | instr[21:16];
|
`CMOVEZ: begin
|
`CMOVEZ: begin
|
o[63:0] = (a==64'd0) ? b : c;
|
o[63:0] = (a==64'd0) ? b : c;
|
end
|
end
|
`CMOVNZ: if (instr[41])
|
`CMOVNZ: if (instr[41])
|
o[63:0] = (a!=64'd0) ? b : {{48{instr[38]}},instr[38:28],instr[22:18]};
|
o[63:0] = (a!=64'd0) ? b : {{48{instr[38]}},instr[38:28],instr[22:18]};
|
else
|
else
|
o[63:0] = (a!=64'd0) ? b : c;
|
o[63:0] = (a!=64'd0) ? b : c;
|
`MUX: for (n = 0; n < 64; n = n + 1)
|
`MUX: for (n = 0; n < 64; n = n + 1)
|
o[n] <= a[n] ? b[n] : c[n];
|
o[n] <= a[n] ? b[n] : c[n];
|
`MULU: o[63:0] = instr[25:24]==2'b00 ? prod[DBW-1:0] : prod[DBW*2-1:DBW];
|
`MULU: o[63:0] = prod[DBW-1:0];
|
`MULSU: o[63:0] = instr[25:24]==2'b00 ? prod[DBW-1:0] : prod[DBW*2-1:DBW];
|
`MULSU: o[63:0] = prod[DBW-1:0];
|
`MUL: o[63:0] = instr[25:24]==2'b00 ? prod[DBW-1:0] : prod[DBW*2-1:DBW];
|
`MUL: o[63:0] = prod[DBW-1:0];
|
`DIVMODU: o[63:0] = BIG ? (instr[25:24]==2'b00 ? divq : rem) : 64'hCCCCCCCCCCCCCCCC;
|
`DIVU: o[63:0] = BIG ? divq : 64'hCCCCCCCCCCCCCCCC;
|
`DIVMODSU: o[63:0] = BIG ? (instr[25:24]==2'b00 ? divq : rem) : 64'hCCCCCCCCCCCCCCCC;
|
`DIVSU: o[63:0] = BIG ? divq : 64'hCCCCCCCCCCCCCCCC;
|
`DIVMOD: o[63:0] = BIG ? (instr[25:24]==2'b00 ? divq : rem) : 64'hCCCCCCCCCCCCCCCC;
|
`DIV: o[63:0] = BIG ? divq : 64'hCCCCCCCCCCCCCCCC;
|
|
`MODU: o[63:0] = BIG ? rem : 64'hCCCCCCCCCCCCCCCC;
|
|
`MODSU: o[63:0] = BIG ? rem : 64'hCCCCCCCCCCCCCCCC;
|
|
`MOD: o[63:0] = BIG ? rem : 64'hCCCCCCCCCCCCCCCC;
|
`LEAX:
|
`LEAX:
|
begin
|
begin
|
o[63:0] = BIG ? a + (b << instr[22:21]) : 64'hCCCCCCCCEEEEEEEE;
|
o[63:0] = BIG ? a + (b << instr[22:21]) : 64'hCCCCCCCCEEEEEEEE;
|
o[63:44] = PTR;
|
o[63:44] = PTR;
|
end
|
end
|
`MIN: case(sz)
|
`MIN: case(sz)
|
3'd0,3'd4:
|
3'd0,3'd4:
|
begin
|
begin
|
o[7:0] = BIG ? ($signed(a[7:0]) < $signed(b[7:0]) ? a[7:0] : b[7:0]) : 8'hCC;
|
o[7:0] = BIG ? ($signed(a[7:0]) < $signed(b[7:0]) ? a[7:0] : b[7:0]) : 8'hCC;
|
o[15:8] = BIG ? ($signed(a[15:8]) < $signed(b[15:8]) ? a[15:8] : b[15:8]) : 64'hCCCCCCCCCCCCCCCC;
|
o[15:8] = BIG ? ($signed(a[15:8]) < $signed(b[15:8]) ? a[15:8] : b[15:8]) : 64'hCCCCCCCCCCCCCCCC;
|
o[23:16] = BIG ? ($signed(a[23:16]) < $signed(b[23:16]) ? a[23:16] : b[23:16]) : 64'hCCCCCCCCCCCCCCCC;
|
o[23:16] = BIG ? ($signed(a[23:16]) < $signed(b[23:16]) ? a[23:16] : b[23:16]) : 64'hCCCCCCCCCCCCCCCC;
|
o[31:24] = BIG ? ($signed(a[31:24]) < $signed(b[31:24]) ? a[31:24] : b[31:24]) : 64'hCCCCCCCCCCCCCCCC;
|
o[31:24] = BIG ? ($signed(a[31:24]) < $signed(b[31:24]) ? a[31:24] : b[31:24]) : 64'hCCCCCCCCCCCCCCCC;
|
o[39:32] = BIG ? ($signed(a[39:32]) < $signed(b[39:32]) ? a[39:32] : b[39:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[39:32] = BIG ? ($signed(a[39:32]) < $signed(b[39:32]) ? a[39:32] : b[39:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[47:40] = BIG ? ($signed(a[47:40]) < $signed(b[47:40]) ? a[47:40] : b[47:40]) : 64'hCCCCCCCCCCCCCCCC;
|
o[47:40] = BIG ? ($signed(a[47:40]) < $signed(b[47:40]) ? a[47:40] : b[47:40]) : 64'hCCCCCCCCCCCCCCCC;
|
o[55:48] = BIG ? ($signed(a[55:48]) < $signed(b[55:48]) ? a[55:48] : b[55:48]) : 64'hCCCCCCCCCCCCCCCC;
|
o[55:48] = BIG ? ($signed(a[55:48]) < $signed(b[55:48]) ? a[55:48] : b[55:48]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:56] = BIG ? ($signed(a[63:56]) < $signed(b[63:56]) ? a[63:56] : b[63:56]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:56] = BIG ? ($signed(a[63:56]) < $signed(b[63:56]) ? a[63:56] : b[63:56]) : 64'hCCCCCCCCCCCCCCCC;
|
end
|
end
|
3'd1,3'd5:
|
3'd1,3'd5:
|
begin
|
begin
|
o[15:0] = BIG ? ($signed(a[15:0]) < $signed(b[15:0]) ? a[15:0] : b[15:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[15:0] = BIG ? ($signed(a[15:0]) < $signed(b[15:0]) ? a[15:0] : b[15:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[32:16] = BIG ? ($signed(a[32:16]) < $signed(b[32:16]) ? a[32:16] : b[32:16]) : 64'hCCCCCCCCCCCCCCCC;
|
o[32:16] = BIG ? ($signed(a[32:16]) < $signed(b[32:16]) ? a[32:16] : b[32:16]) : 64'hCCCCCCCCCCCCCCCC;
|
o[47:32] = BIG ? ($signed(a[47:32]) < $signed(b[47:32]) ? a[47:32] : b[47:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[47:32] = BIG ? ($signed(a[47:32]) < $signed(b[47:32]) ? a[47:32] : b[47:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:48] = BIG ? ($signed(a[63:48]) < $signed(b[63:48]) ? a[63:48] : b[63:48]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:48] = BIG ? ($signed(a[63:48]) < $signed(b[63:48]) ? a[63:48] : b[63:48]) : 64'hCCCCCCCCCCCCCCCC;
|
end
|
end
|
3'd2,3'd6:
|
3'd2,3'd6:
|
begin
|
begin
|
o[31:0] = BIG ? ($signed(a[31:0]) < $signed(b[31:0]) ? a[31:0] : b[31:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[31:0] = BIG ? ($signed(a[31:0]) < $signed(b[31:0]) ? a[31:0] : b[31:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:32] = BIG ? ($signed(a[63:32]) < $signed(b[63:32]) ? a[63:32] : b[63:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:32] = BIG ? ($signed(a[63:32]) < $signed(b[63:32]) ? a[63:32] : b[63:32]) : 64'hCCCCCCCCCCCCCCCC;
|
end
|
end
|
3'd3,3'd7:
|
3'd3,3'd7:
|
begin
|
begin
|
o[63:0] = BIG ? ($signed(a) < $signed(b) ? a : b) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:0] = BIG ? ($signed(a) < $signed(b) ? a : b) : 64'hCCCCCCCCCCCCCCCC;
|
end
|
end
|
endcase
|
endcase
|
`MAX: case(sz)
|
`MAX: case(sz)
|
3'd0,3'd4:
|
3'd0,3'd4:
|
begin
|
begin
|
o[7:0] = BIG ? ($signed(a[7:0]) > $signed(b[7:0]) ? a[7:0] : b[7:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[7:0] = BIG ? ($signed(a[7:0]) > $signed(b[7:0]) ? a[7:0] : b[7:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[15:8] = BIG ? ($signed(a[15:8]) > $signed(b[15:8]) ? a[15:8] : b[15:8]) : 64'hCCCCCCCCCCCCCCCC;
|
o[15:8] = BIG ? ($signed(a[15:8]) > $signed(b[15:8]) ? a[15:8] : b[15:8]) : 64'hCCCCCCCCCCCCCCCC;
|
o[23:16] = BIG ? ($signed(a[23:16]) > $signed(b[23:16]) ? a[23:16] : b[23:16]) : 64'hCCCCCCCCCCCCCCCC;
|
o[23:16] = BIG ? ($signed(a[23:16]) > $signed(b[23:16]) ? a[23:16] : b[23:16]) : 64'hCCCCCCCCCCCCCCCC;
|
o[31:24] = BIG ? ($signed(a[31:24]) > $signed(b[31:24]) ? a[31:24] : b[31:24]) : 64'hCCCCCCCCCCCCCCCC;
|
o[31:24] = BIG ? ($signed(a[31:24]) > $signed(b[31:24]) ? a[31:24] : b[31:24]) : 64'hCCCCCCCCCCCCCCCC;
|
o[39:32] = BIG ? ($signed(a[39:32]) > $signed(b[39:32]) ? a[39:32] : b[39:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[39:32] = BIG ? ($signed(a[39:32]) > $signed(b[39:32]) ? a[39:32] : b[39:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[47:40] = BIG ? ($signed(a[47:40]) > $signed(b[47:40]) ? a[47:40] : b[47:40]) : 64'hCCCCCCCCCCCCCCCC;
|
o[47:40] = BIG ? ($signed(a[47:40]) > $signed(b[47:40]) ? a[47:40] : b[47:40]) : 64'hCCCCCCCCCCCCCCCC;
|
o[55:48] = BIG ? ($signed(a[55:48]) > $signed(b[55:48]) ? a[55:48] : b[55:48]) : 64'hCCCCCCCCCCCCCCCC;
|
o[55:48] = BIG ? ($signed(a[55:48]) > $signed(b[55:48]) ? a[55:48] : b[55:48]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:56] = BIG ? ($signed(a[63:56]) > $signed(b[63:56]) ? a[63:56] : b[63:56]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:56] = BIG ? ($signed(a[63:56]) > $signed(b[63:56]) ? a[63:56] : b[63:56]) : 64'hCCCCCCCCCCCCCCCC;
|
end
|
end
|
3'd1,3'd5:
|
3'd1,3'd5:
|
begin
|
begin
|
o[15:0] = BIG ? ($signed(a[15:0]) > $signed(b[15:0]) ? a[15:0] : b[15:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[15:0] = BIG ? ($signed(a[15:0]) > $signed(b[15:0]) ? a[15:0] : b[15:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[32:16] = BIG ? ($signed(a[32:16]) > $signed(b[32:16]) ? a[32:16] : b[32:16]) : 64'hCCCCCCCCCCCCCCCC;
|
o[32:16] = BIG ? ($signed(a[32:16]) > $signed(b[32:16]) ? a[32:16] : b[32:16]) : 64'hCCCCCCCCCCCCCCCC;
|
o[47:32] = BIG ? ($signed(a[47:32]) > $signed(b[47:32]) ? a[47:32] : b[47:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[47:32] = BIG ? ($signed(a[47:32]) > $signed(b[47:32]) ? a[47:32] : b[47:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:48] = BIG ? ($signed(a[63:48]) > $signed(b[63:48]) ? a[63:48] : b[63:48]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:48] = BIG ? ($signed(a[63:48]) > $signed(b[63:48]) ? a[63:48] : b[63:48]) : 64'hCCCCCCCCCCCCCCCC;
|
end
|
end
|
3'd2,3'd6:
|
3'd2,3'd6:
|
begin
|
begin
|
o[31:0] = BIG ? ($signed(a[31:0]) > $signed(b[31:0]) ? a[31:0] : b[31:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[31:0] = BIG ? ($signed(a[31:0]) > $signed(b[31:0]) ? a[31:0] : b[31:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:32] = BIG ? ($signed(a[63:32]) > $signed(b[63:32]) ? a[63:32] : b[63:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:32] = BIG ? ($signed(a[63:32]) > $signed(b[63:32]) ? a[63:32] : b[63:32]) : 64'hCCCCCCCCCCCCCCCC;
|
end
|
end
|
3'd3,3'd7:
|
3'd3,3'd7:
|
begin
|
begin
|
o[63:0] = BIG ? ($signed(a) > $signed(b) ? a : b) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:0] = BIG ? ($signed(a) > $signed(b) ? a : b) : 64'hCCCCCCCCCCCCCCCC;
|
end
|
end
|
endcase
|
endcase
|
`MAJ: o = (a & b) | (a & c) | (b & c);
|
`MAJ: o = (a & b) | (a & c) | (b & c);
|
`CHK: o[63:0] = (a >= b && a < c);
|
`CHK: o[63:0] = (a >= b && a < c);
|
/*
|
/*
|
`RTOP: case(c[5:0])
|
`RTOP: case(c[5:0])
|
`RTADD: o = a + b;
|
`RTADD: o = a + b;
|
`RTSUB: o = a - b;
|
`RTSUB: o = a - b;
|
`RTAND: o = and64;
|
`RTAND: o = and64;
|
`RTOR: o = or64;
|
`RTOR: o = or64;
|
`RTXOR: o = xor64;
|
`RTXOR: o = xor64;
|
`RTNAND: o = ~and64;
|
`RTNAND: o = ~and64;
|
`RTNOR: o = ~or64;
|
`RTNOR: o = ~or64;
|
`RTXNOR: o = ~xor64;
|
`RTXNOR: o = ~xor64;
|
`RTSLT: o = as < bs;
|
`RTSLT: o = as < bs;
|
`RTSGE: o = as >= bs;
|
`RTSGE: o = as >= bs;
|
`RTSLE: o = as <= bs;
|
`RTSLE: o = as <= bs;
|
`RTSGT: o = as > bs;
|
`RTSGT: o = as > bs;
|
`RTSEQ: o = as==bs;
|
`RTSEQ: o = as==bs;
|
`RTSNE: o = as!=bs;
|
`RTSNE: o = as!=bs;
|
endcase
|
endcase
|
*/
|
*/
|
default: o[63:0] = 64'hDEADDEADDEADDEAD;
|
default: o[63:0] = 64'hDEADDEADDEADDEAD;
|
endcase
|
endcase
|
`MEMNDX:
|
`MEMNDX:
|
if (instr[7:6]==2'b00)
|
if (instr[7:6]==2'b00)
|
case(instr[`INSTRUCTION_S2])
|
case(instr[`INSTRUCTION_S2])
|
`LVX,
|
`LVX,
|
`LBX,`LBUX,`LCX,`LCUX,
|
`LBX,`LBUX,`LCX,`LCUX,
|
`LHX,`LHUX,`LWX,`LWRX,`SBX,`SCX,`SHX,`SWX,`SWCX:
|
`LHX,`LHUX,`LWX,`LWRX,`SBX,`SCX,`SHX,`SWX,`SWCX:
|
if (BIG) begin
|
if (BIG) begin
|
o[63:0] = a + (b << instr[24:23]);
|
o[63:0] = a + (b << instr[24:23]);
|
end
|
end
|
else
|
else
|
o[63:0] = 64'hCCCCCCCCEEEEEEEE;
|
o[63:0] = 64'hCCCCCCCCEEEEEEEE;
|
`LVX,`SVX: if (BIG) begin
|
`LVX,`SVX: if (BIG) begin
|
o[63:0] = a + (b << 2'd3);
|
o[63:0] = a + (b << 2'd3);
|
end
|
end
|
else
|
else
|
o[63:0] = 64'hCCCCCCCCCCCCCCCC;
|
o[63:0] = 64'hCCCCCCCCCCCCCCCC;
|
`LVWS,`SVWS:
|
`LVWS,`SVWS:
|
if (BIG) begin
|
if (BIG) begin
|
o[63:0] = a + ({b * ven,3'b000});
|
o[63:0] = a + ({b * ven,3'b000});
|
end
|
end
|
else
|
else
|
o[63:0] = 64'hCCCCCCCCCCCCCCCC;
|
o[63:0] = 64'hCCCCCCCCCCCCCCCC;
|
endcase
|
endcase
|
else
|
else
|
o[63:0] = 64'hDEADDEADDEADDEAD;
|
o[63:0] = 64'hDEADDEADDEADDEAD;
|
`AUIPC:
|
`AUIPC:
|
begin
|
begin
|
if (instr[7:6]==2'b01)
|
if (instr[7:6]==2'b01)
|
o[63:0] = pc + {instr[47:13],30'd0};
|
o[63:0] = pc + {instr[47:13],30'd0};
|
else
|
else
|
o[63:0] = pc + {{15{instr[31]}},instr[31:13],30'd0};
|
o[63:0] = pc + {{15{instr[31]}},instr[31:13],30'd0};
|
o[29:0] = 30'd0;
|
o[29:0] = 30'd0;
|
// o[63:44] = PTR;
|
// o[63:44] = PTR;
|
end
|
end
|
`LUI:
|
`LUI:
|
begin
|
begin
|
if (instr[7:6]==2'b01)
|
if (instr[7:6]==2'b01)
|
o[63:0] = {instr[47:13],30'd0};
|
o[63:0] = {instr[47:13],30'd0};
|
else
|
else
|
o[63:0] = {{15{instr[31]}},instr[31:13],30'd0};
|
o[63:0] = {{15{instr[31]}},instr[31:13],30'd0};
|
end
|
end
|
`ADDI: o[63:0] = a + b;
|
`ADDI: o[63:0] = a + b;
|
`SLTI: o[63:0] = $signed(a) < $signed(b);
|
`SLTI: o[63:0] = $signed(a) < $signed(b);
|
`SLTUI: o[63:0] = a < b;
|
`SLTUI: o[63:0] = a < b;
|
`SGTI: o[63:0] = $signed(a) > $signed(b);
|
`SGTI: o[63:0] = $signed(a) > $signed(b);
|
`SGTUI: o[63:0] = a > b;
|
`SGTUI: o[63:0] = a > b;
|
`ANDI: o[63:0] = a & andb;
|
`ANDI: o[63:0] = a & andb;
|
`ORI: o[63:0] = a | orb;
|
`ORI: o[63:0] = a | orb;
|
`XORI: o[63:0] = a ^ orb;
|
`XORI: o[63:0] = a ^ orb;
|
`XNORI: o[63:0] = ~(a ^ orb);
|
`XNORI: o[63:0] = ~(a ^ orb);
|
`MULUI: o[63:0] = prod[DBW-1:0];
|
`MULUI: o[63:0] = prod[DBW-1:0];
|
`MULI: o[63:0] = prod[DBW-1:0];
|
`MULI: o[63:0] = prod[DBW-1:0];
|
`DIVUI: o[63:0] = BIG ? divq : 64'hCCCCCCCCCCCCCCCC;
|
`DIVUI: o[63:0] = BIG ? divq : 64'hCCCCCCCCCCCCCCCC;
|
`DIVI: o[63:0] = BIG ? divq : 64'hCCCCCCCCCCCCCCCC;
|
`DIVI: o[63:0] = BIG ? divq : 64'hCCCCCCCCCCCCCCCC;
|
`MODI: o[63:0] = BIG ? rem : 64'hCCCCCCCCCCCCCCCC;
|
`MODI: o[63:0] = BIG ? rem : 64'hCCCCCCCCCCCCCCCC;
|
`LB,`LBU,`SB: o[63:0] = a + b;
|
`LB,`LBU,`SB: o[63:0] = a + b;
|
`Lx,`LxU,`Sx:
|
`Lx,`LxU,`Sx:
|
begin
|
begin
|
o[63:0] = a + b;
|
o[63:0] = a + b;
|
casez(b[2:0])
|
casez(b[2:0])
|
3'b100: o[2:0] = 3'd0; // LW / SW
|
3'b100: o[2:0] = 3'd0; // LW / SW
|
3'b?10: o[1:0] = 2'd0; // LH / LHU / SH
|
3'b?10: o[1:0] = 2'd0; // LH / LHU / SH
|
3'b??1: o[0] = 1'd0; // LC / LCU / SC
|
3'b??1: o[0] = 1'd0; // LC / LCU / SC
|
endcase
|
endcase
|
end
|
end
|
`LWR,`SWC,`CAS:
|
`LWR,`SWC,`CAS:
|
begin
|
begin
|
o[63:0] = a + b;
|
o[63:0] = a + b;
|
end
|
end
|
`LVx: begin
|
`LVx: begin
|
o[63:0] = a + (instr[6] ? sxb26 : sxb10);
|
o[63:0] = a + (instr[6] ? sxb26 : sxb10);
|
end
|
end
|
`LV,`SV: begin
|
`LV,`SV: begin
|
o[63:0] = a + b + {ven,3'b0};
|
o[63:0] = a + b + {ven,3'b0};
|
end
|
end
|
`CSRRW: case(instr[27:18])
|
`CSRRW: case(instr[27:18])
|
10'h044: o[63:0] = BIG ? csr | {thrd,24'h0} : 64'hDDDDDDDDDDDDDDDD;
|
10'h044: o[63:0] = BIG ? csr | {thrd,24'h0} : 64'hDDDDDDDDDDDDDDDD;
|
default: o[63:0] = BIG ? csr : 64'hDDDDDDDDDDDDDDDD;
|
default: o[63:0] = BIG ? csr : 64'hDDDDDDDDDDDDDDDD;
|
endcase
|
endcase
|
`BITFIELD: o[63:0] = BIG ? bfout : 64'hCCCCCCCCCCCCCCCC;
|
`BITFIELD: o[63:0] = BIG ? bfout : 64'hCCCCCCCCCCCCCCCC;
|
default: o[63:0] = 64'hDEADDEADDEADDEAD;
|
default: o[63:0] = 64'hDEADDEADDEADDEAD;
|
endcase
|
endcase
|
end
|
end
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ld)
|
if (ld)
|
adrDone <= FALSE;
|
adrDone <= FALSE;
|
else if (mem|shift48)
|
else if (mem|shift48)
|
adrDone <= TRUE;
|
adrDone <= TRUE;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
case(instr[`INSTRUCTION_OP])
|
case(instr[`INSTRUCTION_OP])
|
`R2:
|
`R2:
|
if (instr[`INSTRUCTION_L2]==2'b01)
|
if (instr[`INSTRUCTION_L2]==2'b01)
|
case(instr[47:42])
|
case(instr[47:42])
|
`ADD,`SUB,
|
`ADD,`SUB,
|
`AND,`OR,`XOR,`NAND,`NOR,`XNOR,
|
`AND,`OR,`XOR,`NAND,`NOR,`XNOR,
|
`SHIFTR:
|
`SHIFTR:
|
case(instr[41:36])
|
case(instr[41:36])
|
`R1:
|
`R1:
|
case(instr[22:18])
|
case(instr[22:18])
|
`COM: addro[63:0] = ~addr8;
|
`COM: addro[63:0] = ~addr8;
|
`NOT: addro[63:0] = ~|addr8;
|
`NOT: addro[63:0] = ~|addr8;
|
`NEG: addro[63:0] = -addr8;
|
`NEG: addro[63:0] = -addr8;
|
default: addro[63:0] = 64'hDCDCDCDCDCDCDCDC;
|
default: addro[63:0] = 64'hDCDCDCDCDCDCDCDC;
|
endcase
|
endcase
|
`ADD: addro[63:0] = addr8 + c;
|
`ADD: addro[63:0] = addr8 + c;
|
`SUB: addro[63:0] = addr8 - c;
|
`SUB: addro[63:0] = addr8 - c;
|
`AND: addro[63:0] = addr8 & c;
|
`AND: addro[63:0] = addr8 & c;
|
`OR: addro[63:0] = addr8 | c;
|
`OR: addro[63:0] = addr8 | c;
|
`XOR: addro[63:0] = addr8 ^ c;
|
`XOR: addro[63:0] = addr8 ^ c;
|
default: addro[63:0] = 64'hDCDCDCDCDCDCDCDC;
|
default: addro[63:0] = 64'hDCDCDCDCDCDCDCDC;
|
endcase
|
endcase
|
default: addro[63:0] = 64'hDCDCDCDCDCDCDCDC;
|
default: addro[63:0] = 64'hDCDCDCDCDCDCDCDC;
|
endcase
|
endcase
|
else
|
else
|
addro = 64'hCCCCCCCCCCCCCCCE;
|
addro = 64'hCCCCCCCCCCCCCCCE;
|
default: addro = 64'hCCCCCCCCCCCCCCCE;
|
default: addro = 64'hCCCCCCCCCCCCCCCE;
|
endcase
|
endcase
|
|
|
reg sao_done, sao_idle;
|
reg sao_done, sao_idle;
|
|
|
// Generate done signal
|
// Generate done signal
|
always @*
|
always @*
|
if (rst)
|
if (rst)
|
done <= TRUE;
|
done <= TRUE;
|
else begin
|
else begin
|
if (IsMul(instr))
|
if (IsMul(instr))
|
done <= mult_done;
|
done <= mult_done;
|
else if (IsDivmod(instr) & BIG)
|
else if (IsDivmod(instr) & BIG)
|
done <= div_done;
|
done <= div_done;
|
else if (IsShiftAndOp(instr) & BIG)
|
else if (IsShiftAndOp(instr) & BIG)
|
done <= sao_done;
|
done <= sao_done;
|
else if (shift48)
|
else if (shift48)
|
done <= adrDone;
|
done <= adrDone;
|
else
|
else
|
done <= TRUE;
|
done <= TRUE;
|
end
|
end
|
|
|
// Generate idle signal
|
// Generate idle signal
|
always @*
|
always @*
|
if (rst)
|
if (rst)
|
idle <= TRUE;
|
idle <= TRUE;
|
else begin
|
else begin
|
if (IsMul(instr))
|
if (IsMul(instr))
|
idle <= mult_idle;
|
idle <= mult_idle;
|
else if (IsDivmod(instr) & BIG)
|
else if (IsDivmod(instr) & BIG)
|
idle <= div_idle;
|
idle <= div_idle;
|
else if (IsShiftAndOp(instr) & BIG)
|
else if (IsShiftAndOp(instr) & BIG)
|
idle <= sao_idle;
|
idle <= sao_idle;
|
else if (shift48)
|
else if (shift48)
|
idle <= adrIdle;
|
idle <= adrIdle;
|
else
|
else
|
idle <= TRUE;
|
idle <= TRUE;
|
end
|
end
|
|
|
function fnOverflow;
|
function fnOverflow;
|
input op; // 0 = add, 1=sub
|
input op; // 0 = add, 1=sub
|
input a;
|
input a;
|
input b;
|
input b;
|
input s;
|
input s;
|
fnOverflow = (op ^ s ^ b) & (~op ^ a ^ b);
|
fnOverflow = (op ^ s ^ b) & (~op ^ a ^ b);
|
endfunction
|
endfunction
|
|
|
always @*
|
always @*
|
begin
|
begin
|
if ((tgt[4:0]==5'd31 || tgt[4:0]==5'd30) && (o[31:0] < sbl || o[31:0] > sbu))
|
if ((tgt[4:0]==5'd31 || tgt[4:0]==5'd30) && (o[31:0] < sbl || o[31:0] > sbu))
|
exc <= `FLT_STK;
|
exc <= `FLT_STK;
|
else
|
else
|
case(instr[`INSTRUCTION_OP])
|
case(instr[`INSTRUCTION_OP])
|
`R2:
|
`R2:
|
case(instr[`INSTRUCTION_S2])
|
case(instr[`INSTRUCTION_S2])
|
`ADD: exc <= (fnOverflow(0,a[63],b[63],o[63]) & excen[0] & instr[24]) ? `FLT_OFL : `FLT_NONE;
|
`ADD: exc <= (fnOverflow(0,a[63],b[63],o[63]) & excen[0] & instr[24]) ? `FLT_OFL : `FLT_NONE;
|
`SUB: exc <= (fnOverflow(1,a[63],b[63],o[63]) & excen[1] & instr[24]) ? `FLT_OFL : `FLT_NONE;
|
`SUB: exc <= (fnOverflow(1,a[63],b[63],o[63]) & excen[1] & instr[24]) ? `FLT_OFL : `FLT_NONE;
|
`ASL,`ASLI: exc <= (BIG & aslo & excen[2]) ? `FLT_OFL : `FLT_NONE;
|
`ASL,`ASLI: exc <= (BIG & aslo & excen[2]) ? `FLT_OFL : `FLT_NONE;
|
`MUL,`MULSU: exc <= prod[63] ? (prod[127:64] != 64'hFFFFFFFFFFFFFFFF && excen[3] ? `FLT_OFL : `FLT_NONE ):
|
`MUL,`MULSU: exc <= prod[63] ? (prod[127:64] != 64'hFFFFFFFFFFFFFFFF && excen[3] ? `FLT_OFL : `FLT_NONE ):
|
(prod[127:64] != 64'd0 && excen[3] ? `FLT_OFL : `FLT_NONE);
|
(prod[127:64] != 64'd0 && excen[3] ? `FLT_OFL : `FLT_NONE);
|
`MULU: exc <= prod[127:64] != 64'd0 && excen[3] ? `FLT_OFL : `FLT_NONE;
|
`MULU: exc <= prod[127:64] != 64'd0 && excen[3] ? `FLT_OFL : `FLT_NONE;
|
`DIVMOD,`DIVMODSU,`DIVMODU: exc <= BIG && excen[4] & divByZero ? `FLT_DBZ : `FLT_NONE;
|
`DIV,`DIVSU,`DIVU: exc <= BIG && excen[4] & divByZero ? `FLT_DBZ : `FLT_NONE;
|
|
`MOD,`MODSU,`MODU: exc <= BIG && excen[4] & divByZero ? `FLT_DBZ : `FLT_NONE;
|
default: exc <= `FLT_NONE;
|
default: exc <= `FLT_NONE;
|
endcase
|
endcase
|
`MULI: exc <= prod[63] ? (prod[127:64] != 64'hFFFFFFFFFFFFFFFF & excen[3] ? `FLT_OFL : `FLT_NONE):
|
`MULI: exc <= prod[63] ? (prod[127:64] != 64'hFFFFFFFFFFFFFFFF & excen[3] ? `FLT_OFL : `FLT_NONE):
|
(prod[127:64] != 64'd0 & excen[3] ? `FLT_OFL : `FLT_NONE);
|
(prod[127:64] != 64'd0 & excen[3] ? `FLT_OFL : `FLT_NONE);
|
`DIVI: exc <= BIG & excen[4] & divByZero & instr[27] ? `FLT_DBZ : `FLT_NONE;
|
`DIVI: exc <= BIG & excen[4] & divByZero & instr[27] ? `FLT_DBZ : `FLT_NONE;
|
`MODI: exc <= BIG & excen[4] & divByZero & instr[27] ? `FLT_DBZ : `FLT_NONE;
|
`MODI: exc <= BIG & excen[4] & divByZero & instr[27] ? `FLT_DBZ : `FLT_NONE;
|
default: exc <= `FLT_NONE;
|
default: exc <= `FLT_NONE;
|
endcase
|
endcase
|
end
|
end
|
|
|
reg [63:0] aa, bb;
|
reg [63:0] aa, bb;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
aa <= shfto;
|
aa <= shfto;
|
bb <= c;
|
bb <= c;
|
end
|
end
|
|
|
task tskSlt;
|
task tskSlt;
|
input [47:0] instr;
|
input [47:0] instr;
|
input [2:0] sz;
|
input [2:0] sz;
|
input [63:0] a;
|
input [63:0] a;
|
input [63:0] b;
|
input [63:0] b;
|
output [63:0] o;
|
output [63:0] o;
|
begin
|
begin
|
case(sz[2:0])
|
case(sz[2:0])
|
3'd0: o[63:0] = $signed(a[7:0]) < $signed(b[7:0]);
|
3'd0: o[63:0] = $signed(a[7:0]) < $signed(b[7:0]);
|
3'd1: o[63:0] = $signed(a[15:0]) < $signed(b[15:0]);
|
3'd1: o[63:0] = $signed(a[15:0]) < $signed(b[15:0]);
|
3'd2: o[63:0] = $signed(a[31:0]) < $signed(b[31:0]);
|
3'd2: o[63:0] = $signed(a[31:0]) < $signed(b[31:0]);
|
3'd3: o[63:0] = $signed(a) < $signed(b);
|
3'd3: o[63:0] = $signed(a) < $signed(b);
|
3'd4: o[63:0] = {
|
3'd4: o[63:0] = {
|
7'h0,$signed(a[7:0]) < $signed(b[7:0]),
|
7'h0,$signed(a[7:0]) < $signed(b[7:0]),
|
7'h0,$signed(a[15:8]) < $signed(b[15:8]),
|
7'h0,$signed(a[15:8]) < $signed(b[15:8]),
|
7'h0,$signed(a[23:16]) < $signed(b[23:16]),
|
7'h0,$signed(a[23:16]) < $signed(b[23:16]),
|
7'h0,$signed(a[31:24]) < $signed(b[31:24]),
|
7'h0,$signed(a[31:24]) < $signed(b[31:24]),
|
7'h0,$signed(a[39:32]) < $signed(b[39:32]),
|
7'h0,$signed(a[39:32]) < $signed(b[39:32]),
|
7'h0,$signed(a[47:40]) < $signed(b[47:40]),
|
7'h0,$signed(a[47:40]) < $signed(b[47:40]),
|
7'h0,$signed(a[55:48]) < $signed(b[55:48]),
|
7'h0,$signed(a[55:48]) < $signed(b[55:48]),
|
7'h0,$signed(a[63:56]) < $signed(b[63:56])
|
7'h0,$signed(a[63:56]) < $signed(b[63:56])
|
};
|
};
|
3'd5: o[63:0] = {
|
3'd5: o[63:0] = {
|
15'h0,$signed(a[15:0]) < $signed(b[15:0]),
|
15'h0,$signed(a[15:0]) < $signed(b[15:0]),
|
15'h0,$signed(a[31:16]) < $signed(b[31:16]),
|
15'h0,$signed(a[31:16]) < $signed(b[31:16]),
|
15'h0,$signed(a[47:32]) < $signed(b[47:32]),
|
15'h0,$signed(a[47:32]) < $signed(b[47:32]),
|
15'h0,$signed(a[63:48]) < $signed(b[63:48])
|
15'h0,$signed(a[63:48]) < $signed(b[63:48])
|
};
|
};
|
3'd6: o[63:0] = {
|
3'd6: o[63:0] = {
|
31'h0,$signed(a[31:0]) < $signed(b[31:0]),
|
31'h0,$signed(a[31:0]) < $signed(b[31:0]),
|
31'h0,$signed(a[63:32]) < $signed(b[63:32])
|
31'h0,$signed(a[63:32]) < $signed(b[63:32])
|
};
|
};
|
3'd7: o[63:0] = $signed(a[63:0]) < $signed(b[63:0]);
|
3'd7: o[63:0] = $signed(a[63:0]) < $signed(b[63:0]);
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
task tskSle;
|
task tskSle;
|
input [47:0] instr;
|
input [47:0] instr;
|
input [2:0] sz;
|
input [2:0] sz;
|
input [63:0] a;
|
input [63:0] a;
|
input [63:0] b;
|
input [63:0] b;
|
output [63:0] o;
|
output [63:0] o;
|
begin
|
begin
|
case(sz[2:0])
|
case(sz[2:0])
|
3'd0: o[63:0] = $signed(a[7:0]) <= $signed(b[7:0]);
|
3'd0: o[63:0] = $signed(a[7:0]) <= $signed(b[7:0]);
|
3'd1: o[63:0] = $signed(a[15:0]) <= $signed(b[15:0]);
|
3'd1: o[63:0] = $signed(a[15:0]) <= $signed(b[15:0]);
|
3'd2: o[63:0] = $signed(a[31:0]) <= $signed(b[31:0]);
|
3'd2: o[63:0] = $signed(a[31:0]) <= $signed(b[31:0]);
|
3'd3: o[63:0] = $signed(a) <= $signed(b);
|
3'd3: o[63:0] = $signed(a) <= $signed(b);
|
3'd4: o[63:0] = {
|
3'd4: o[63:0] = {
|
7'h0,$signed(a[7:0]) <= $signed(b[7:0]),
|
7'h0,$signed(a[7:0]) <= $signed(b[7:0]),
|
7'h0,$signed(a[15:8]) <= $signed(b[15:8]),
|
7'h0,$signed(a[15:8]) <= $signed(b[15:8]),
|
7'h0,$signed(a[23:16]) <= $signed(b[23:16]),
|
7'h0,$signed(a[23:16]) <= $signed(b[23:16]),
|
7'h0,$signed(a[31:24]) <= $signed(b[31:24]),
|
7'h0,$signed(a[31:24]) <= $signed(b[31:24]),
|
7'h0,$signed(a[39:32]) <= $signed(b[39:32]),
|
7'h0,$signed(a[39:32]) <= $signed(b[39:32]),
|
7'h0,$signed(a[47:40]) <= $signed(b[47:40]),
|
7'h0,$signed(a[47:40]) <= $signed(b[47:40]),
|
7'h0,$signed(a[55:48]) <= $signed(b[55:48]),
|
7'h0,$signed(a[55:48]) <= $signed(b[55:48]),
|
7'h0,$signed(a[63:56]) <= $signed(b[63:56])
|
7'h0,$signed(a[63:56]) <= $signed(b[63:56])
|
};
|
};
|
3'd5: o[63:0] = {
|
3'd5: o[63:0] = {
|
15'h0,$signed(a[15:0]) <= $signed(b[15:0]),
|
15'h0,$signed(a[15:0]) <= $signed(b[15:0]),
|
15'h0,$signed(a[31:16]) <= $signed(b[31:16]),
|
15'h0,$signed(a[31:16]) <= $signed(b[31:16]),
|
15'h0,$signed(a[47:32]) <= $signed(b[47:32]),
|
15'h0,$signed(a[47:32]) <= $signed(b[47:32]),
|
15'h0,$signed(a[63:48]) <= $signed(b[63:48])
|
15'h0,$signed(a[63:48]) <= $signed(b[63:48])
|
};
|
};
|
3'd6: o[63:0] = {
|
3'd6: o[63:0] = {
|
31'h0,$signed(a[31:0]) <= $signed(b[31:0]),
|
31'h0,$signed(a[31:0]) <= $signed(b[31:0]),
|
31'h0,$signed(a[63:32]) <= $signed(b[63:32])
|
31'h0,$signed(a[63:32]) <= $signed(b[63:32])
|
};
|
};
|
3'd7: o[63:0] = $signed(a[63:0]) <= $signed(b[63:0]);
|
3'd7: o[63:0] = $signed(a[63:0]) <= $signed(b[63:0]);
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
task tskSltu;
|
task tskSltu;
|
input [47:0] instr;
|
input [47:0] instr;
|
input [2:0] sz;
|
input [2:0] sz;
|
input [63:0] a;
|
input [63:0] a;
|
input [63:0] b;
|
input [63:0] b;
|
output [63:0] o;
|
output [63:0] o;
|
begin
|
begin
|
case(sz[2:0])
|
case(sz[2:0])
|
3'd0: o[63:0] = (a[7:0]) < (b[7:0]);
|
3'd0: o[63:0] = (a[7:0]) < (b[7:0]);
|
3'd1: o[63:0] = (a[15:0]) < (b[15:0]);
|
3'd1: o[63:0] = (a[15:0]) < (b[15:0]);
|
3'd2: o[63:0] = (a[31:0]) < (b[31:0]);
|
3'd2: o[63:0] = (a[31:0]) < (b[31:0]);
|
3'd3: o[63:0] = (a) < (b);
|
3'd3: o[63:0] = (a) < (b);
|
3'd4: o[63:0] = {
|
3'd4: o[63:0] = {
|
7'h0,(a[7:0]) < (b[7:0]),
|
7'h0,(a[7:0]) < (b[7:0]),
|
7'h0,(a[15:8]) < (b[15:8]),
|
7'h0,(a[15:8]) < (b[15:8]),
|
7'h0,(a[23:16]) < (b[23:16]),
|
7'h0,(a[23:16]) < (b[23:16]),
|
7'h0,(a[31:24]) < (b[31:24]),
|
7'h0,(a[31:24]) < (b[31:24]),
|
7'h0,(a[39:32]) < (b[39:32]),
|
7'h0,(a[39:32]) < (b[39:32]),
|
7'h0,(a[47:40]) < (b[47:40]),
|
7'h0,(a[47:40]) < (b[47:40]),
|
7'h0,(a[55:48]) < (b[55:48]),
|
7'h0,(a[55:48]) < (b[55:48]),
|
7'h0,(a[63:56]) < (b[63:56])
|
7'h0,(a[63:56]) < (b[63:56])
|
};
|
};
|
3'd5: o[63:0] = {
|
3'd5: o[63:0] = {
|
15'h0,(a[15:0]) < (b[15:0]),
|
15'h0,(a[15:0]) < (b[15:0]),
|
15'h0,(a[31:16]) < (b[31:16]),
|
15'h0,(a[31:16]) < (b[31:16]),
|
15'h0,(a[47:32]) < (b[47:32]),
|
15'h0,(a[47:32]) < (b[47:32]),
|
15'h0,(a[63:48]) < (b[63:48])
|
15'h0,(a[63:48]) < (b[63:48])
|
};
|
};
|
3'd6: o[63:0] = {
|
3'd6: o[63:0] = {
|
31'h0,(a[31:0]) < (b[31:0]),
|
31'h0,(a[31:0]) < (b[31:0]),
|
31'h0,(a[63:32]) < (b[63:32])
|
31'h0,(a[63:32]) < (b[63:32])
|
};
|
};
|
3'd7: o[63:0] = (a[63:0]) < (b[63:0]);
|
3'd7: o[63:0] = (a[63:0]) < (b[63:0]);
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
task tskSleu;
|
task tskSleu;
|
input [47:0] instr;
|
input [47:0] instr;
|
input [2:0] sz;
|
input [2:0] sz;
|
input [63:0] a;
|
input [63:0] a;
|
input [63:0] b;
|
input [63:0] b;
|
output [63:0] o;
|
output [63:0] o;
|
begin
|
begin
|
case(sz[2:0])
|
case(sz[2:0])
|
3'd0: o[63:0] = (a[7:0]) <= (b[7:0]);
|
3'd0: o[63:0] = (a[7:0]) <= (b[7:0]);
|
3'd1: o[63:0] = (a[15:0]) <= (b[15:0]);
|
3'd1: o[63:0] = (a[15:0]) <= (b[15:0]);
|
3'd2: o[63:0] = (a[31:0]) <= (b[31:0]);
|
3'd2: o[63:0] = (a[31:0]) <= (b[31:0]);
|
3'd3: o[63:0] = (a) <= (b);
|
3'd3: o[63:0] = (a) <= (b);
|
3'd4: o[63:0] = {
|
3'd4: o[63:0] = {
|
7'h0,(a[7:0]) <= (b[7:0]),
|
7'h0,(a[7:0]) <= (b[7:0]),
|
7'h0,(a[15:8]) <= (b[15:8]),
|
7'h0,(a[15:8]) <= (b[15:8]),
|
7'h0,(a[23:16]) <= (b[23:16]),
|
7'h0,(a[23:16]) <= (b[23:16]),
|
7'h0,(a[31:24]) <= (b[31:24]),
|
7'h0,(a[31:24]) <= (b[31:24]),
|
7'h0,(a[39:32]) <= (b[39:32]),
|
7'h0,(a[39:32]) <= (b[39:32]),
|
7'h0,(a[47:40]) <= (b[47:40]),
|
7'h0,(a[47:40]) <= (b[47:40]),
|
7'h0,(a[55:48]) <= (b[55:48]),
|
7'h0,(a[55:48]) <= (b[55:48]),
|
7'h0,(a[63:56]) <= (b[63:56])
|
7'h0,(a[63:56]) <= (b[63:56])
|
};
|
};
|
3'd5: o[63:0] = {
|
3'd5: o[63:0] = {
|
15'h0,(a[15:0]) <= (b[15:0]),
|
15'h0,(a[15:0]) <= (b[15:0]),
|
15'h0,(a[31:16]) <= (b[31:16]),
|
15'h0,(a[31:16]) <= (b[31:16]),
|
15'h0,(a[47:32]) <= (b[47:32]),
|
15'h0,(a[47:32]) <= (b[47:32]),
|
15'h0,(a[63:48]) <= (b[63:48])
|
15'h0,(a[63:48]) <= (b[63:48])
|
};
|
};
|
3'd6: o[63:0] = {
|
3'd6: o[63:0] = {
|
31'h0,(a[31:0]) <= (b[31:0]),
|
31'h0,(a[31:0]) <= (b[31:0]),
|
31'h0,(a[63:32]) <= (b[63:32])
|
31'h0,(a[63:32]) <= (b[63:32])
|
};
|
};
|
3'd7: o[63:0] = (a[63:0]) <= (b[63:0]);
|
3'd7: o[63:0] = (a[63:0]) <= (b[63:0]);
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
endmodule
|
endmodule
|
|
|
