| Line 35... |
Line 35... |
// within a single clock cycle.
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// within a single clock cycle.
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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module FT64_L1_icache_mem(rst, clk, wr, en, lineno, i, o, ov, invall, invline);
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module FT64_L1_icache_mem(rst, clk, wr, en, lineno, i, o, ov, invall, invline);
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parameter pLines = 64;
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parameter pLines = 64;
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parameter pLineWidth = 320;
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parameter pLineWidth = 288;
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input rst;
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input rst;
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input clk;
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input clk;
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input wr;
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input wr;
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input [9:0] en;
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input [8:0] en;
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input [5:0] lineno;
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input [5:0] lineno;
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input [pLineWidth-1:0] i;
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input [pLineWidth-1:0] i;
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output [pLineWidth-1:0] o;
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output [pLineWidth-1:0] o;
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output [9:0] ov;
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output [8:0] ov;
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input invall;
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input invall;
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input invline;
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input invline;
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(* ram_style="distributed" *)
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reg [pLineWidth-1:0] mem [0:pLines-1];
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reg [pLineWidth-1:0] mem [0:pLines-1];
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reg [pLines-1:0] valid0;
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reg [pLines-1:0] valid0;
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reg [pLines-1:0] valid1;
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reg [pLines-1:0] valid1;
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reg [pLines-1:0] valid2;
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reg [pLines-1:0] valid2;
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reg [pLines-1:0] valid3;
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reg [pLines-1:0] valid3;
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reg [pLines-1:0] valid4;
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reg [pLines-1:0] valid4;
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reg [pLines-1:0] valid5;
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reg [pLines-1:0] valid5;
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reg [pLines-1:0] valid6;
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reg [pLines-1:0] valid6;
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reg [pLines-1:0] valid7;
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reg [pLines-1:0] valid7;
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reg [pLines-1:0] valid8;
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reg [pLines-1:0] valid8;
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reg [pLines-1:0] valid9;
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always @(posedge clk)
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always @(posedge clk)
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if (wr & en[0]) mem[lineno][31:0] <= i[31:0];
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if (wr & en[0]) mem[lineno][31:0] <= i[31:0];
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always @(posedge clk)
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always @(posedge clk)
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if (wr & en[1]) mem[lineno][63:32] <= i[63:32];
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if (wr & en[1]) mem[lineno][63:32] <= i[63:32];
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| Line 78... |
Line 78... |
always @(posedge clk)
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always @(posedge clk)
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if (wr & en[7]) mem[lineno][255:224] <= i[255:224];
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if (wr & en[7]) mem[lineno][255:224] <= i[255:224];
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always @(posedge clk)
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always @(posedge clk)
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if (wr & en[8]) mem[lineno][287:256] <= i[287:256];
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if (wr & en[8]) mem[lineno][287:256] <= i[287:256];
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always @(posedge clk)
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always @(posedge clk)
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if (wr & en[9]) mem[lineno][319:288] <= i[319:288];
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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valid0 <= 64'd0;
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valid0 <= 64'd0;
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valid1 <= 64'd0;
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valid1 <= 64'd0;
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valid2 <= 64'd0;
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valid2 <= 64'd0;
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valid3 <= 64'd0;
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valid3 <= 64'd0;
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valid4 <= 64'd0;
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valid4 <= 64'd0;
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valid5 <= 64'd0;
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valid5 <= 64'd0;
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valid6 <= 64'd0;
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valid6 <= 64'd0;
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valid7 <= 64'd0;
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valid7 <= 64'd0;
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valid8 <= 64'd0;
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valid8 <= 64'd0;
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valid9 <= 64'd0;
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end
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end
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else begin
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else begin
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if (invall) begin
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if (invall) begin
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valid0 <= 64'd0;
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valid0 <= 64'd0;
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valid1 <= 64'd0;
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valid1 <= 64'd0;
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| Line 103... |
Line 100... |
valid4 <= 64'd0;
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valid4 <= 64'd0;
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valid5 <= 64'd0;
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valid5 <= 64'd0;
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valid6 <= 64'd0;
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valid6 <= 64'd0;
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valid7 <= 64'd0;
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valid7 <= 64'd0;
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valid8 <= 64'd0;
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valid8 <= 64'd0;
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valid9 <= 64'd0;
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end
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end
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else if (invline) begin
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else if (invline) begin
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valid0[lineno] <= 1'b0;
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valid0[lineno] <= 1'b0;
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valid1[lineno] <= 1'b0;
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valid1[lineno] <= 1'b0;
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valid2[lineno] <= 1'b0;
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valid2[lineno] <= 1'b0;
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| Line 115... |
Line 111... |
valid4[lineno] <= 1'b0;
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valid4[lineno] <= 1'b0;
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valid5[lineno] <= 1'b0;
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valid5[lineno] <= 1'b0;
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valid6[lineno] <= 1'b0;
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valid6[lineno] <= 1'b0;
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valid7[lineno] <= 1'b0;
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valid7[lineno] <= 1'b0;
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valid8[lineno] <= 1'b0;
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valid8[lineno] <= 1'b0;
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valid9[lineno] <= 1'b0;
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end
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end
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else if (wr) begin
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else if (wr) begin
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if (en[0]) valid0[lineno] <= 1'b1;
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if (en[0]) valid0[lineno] <= 1'b1;
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if (en[1]) valid1[lineno] <= 1'b1;
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if (en[1]) valid1[lineno] <= 1'b1;
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if (en[2]) valid2[lineno] <= 1'b1;
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if (en[2]) valid2[lineno] <= 1'b1;
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| Line 127... |
Line 122... |
if (en[4]) valid4[lineno] <= 1'b1;
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if (en[4]) valid4[lineno] <= 1'b1;
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if (en[5]) valid5[lineno] <= 1'b1;
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if (en[5]) valid5[lineno] <= 1'b1;
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if (en[6]) valid6[lineno] <= 1'b1;
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if (en[6]) valid6[lineno] <= 1'b1;
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if (en[7]) valid7[lineno] <= 1'b1;
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if (en[7]) valid7[lineno] <= 1'b1;
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if (en[8]) valid8[lineno] <= 1'b1;
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if (en[8]) valid8[lineno] <= 1'b1;
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if (en[9]) valid9[lineno] <= 1'b1;
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end
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end
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end
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end
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assign o = mem[lineno];
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assign o = mem[lineno];
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assign ov[0] = valid0[lineno];
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assign ov[0] = valid0[lineno];
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| Line 141... |
Line 135... |
assign ov[4] = valid4[lineno];
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assign ov[4] = valid4[lineno];
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assign ov[5] = valid5[lineno];
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assign ov[5] = valid5[lineno];
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assign ov[6] = valid6[lineno];
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assign ov[6] = valid6[lineno];
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assign ov[7] = valid7[lineno];
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assign ov[7] = valid7[lineno];
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assign ov[8] = valid8[lineno];
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assign ov[8] = valid8[lineno];
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assign ov[9] = valid9[lineno];
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endmodule
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endmodule
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// Fully associative (64 way) tag memory for L1 icache.
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// Fully associative (64 way) tag memory for L1 icache.
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| Line 204... |
Line 197... |
input wr;
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input wr;
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input [37:0] adr;
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input [37:0] adr;
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output reg [5:0] lineno;
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output reg [5:0] lineno;
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output hit;
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output hit;
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(* ram_style="distributed" *)
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reg [32:0] mem0 [0:15];
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reg [32:0] mem0 [0:15];
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reg [32:0] mem1 [0:15];
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reg [32:0] mem1 [0:15];
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reg [32:0] mem2 [0:15];
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reg [32:0] mem2 [0:15];
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reg [32:0] mem3 [0:15];
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reg [32:0] mem3 [0:15];
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reg [37:0] rradr;
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reg [37:0] rradr;
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| Line 313... |
Line 307... |
parameter FOURWAY = 1'b1;
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parameter FOURWAY = 1'b1;
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input rst;
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input rst;
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input clk;
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input clk;
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input nxt;
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input nxt;
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input wr;
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input wr;
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input [9:0] en;
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input [8:0] en;
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input [37:0] adr;
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input [37:0] adr;
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input [37:0] wadr;
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input [37:0] wadr;
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input [319:0] i;
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input [287:0] i;
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output reg [47:0] o;
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output reg [47:0] o;
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output hit;
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output hit;
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input invall;
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input invall;
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input invline;
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input invline;
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wire [319:0] ic;
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wire [287:0] ic;
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reg [319:0] i1, i2;
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reg [287:0] i1, i2;
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wire [9:0] lv; // line valid
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wire [8:0] lv; // line valid
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wire [5:0] lineno;
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wire [5:0] lineno;
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wire [5:0] wlineno;
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wire [5:0] wlineno;
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wire taghit;
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wire taghit;
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reg wr1,wr2;
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reg wr1,wr2;
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reg [9:0] en1, en2;
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reg [8:0] en1, en2;
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reg invline1, invline2;
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reg invline1, invline2;
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// Must update the cache memory on the cycle after a write to the tag memmory.
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// Must update the cache memory on the cycle after a write to the tag memmory.
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// Otherwise lineno won't be valid. Tag memory takes two clock cycles to update.
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// Otherwise lineno won't be valid. Tag memory takes two clock cycles to update.
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always @(posedge clk)
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always @(posedge clk)
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wr1 <= wr;
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wr1 <= wr;
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always @(posedge clk)
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always @(posedge clk)
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wr2 <= wr1;
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wr2 <= wr1;
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always @(posedge clk)
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always @(posedge clk)
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i1 <= i;
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i1 <= i[287:0];
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always @(posedge clk)
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always @(posedge clk)
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i2 <= i1;
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i2 <= i1;
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always @(posedge clk)
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always @(posedge clk)
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en1 <= en;
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en1 <= en;
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always @(posedge clk)
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always @(posedge clk)
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| Line 439... |
Line 433... |
input clk;
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input clk;
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input wr;
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input wr;
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input [8:0] lineno;
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input [8:0] lineno;
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input [2:0] sel;
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input [2:0] sel;
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input [63:0] i;
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input [63:0] i;
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output [319:0] o;
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output [287:0] o;
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output reg ov;
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output reg ov;
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input invall;
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input invall;
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input invline;
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input invline;
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(* ram_style="block" *)
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reg [63:0] mem0 [0:511];
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reg [63:0] mem0 [0:511];
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reg [63:0] mem1 [0:511];
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reg [63:0] mem1 [0:511];
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reg [63:0] mem2 [0:511];
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reg [63:0] mem2 [0:511];
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reg [63:0] mem3 [0:511];
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reg [63:0] mem3 [0:511];
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reg [63:0] mem4 [0:511];
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reg [31:0] mem4 [0:511];
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reg [511:0] valid;
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reg [511:0] valid;
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reg [8:0] rrcl;
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reg [8:0] rrcl;
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// instruction parcels per cache line
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// instruction parcels per cache line
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wire [8:0] cache_line;
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wire [8:0] cache_line;
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| Line 473... |
Line 468... |
case(sel[2:0])
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case(sel[2:0])
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3'd0: mem0[lineno] <= i;
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3'd0: mem0[lineno] <= i;
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3'd1: mem1[lineno] <= i;
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3'd1: mem1[lineno] <= i;
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3'd2: mem2[lineno] <= i;
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3'd2: mem2[lineno] <= i;
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3'd3: mem3[lineno] <= i;
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3'd3: mem3[lineno] <= i;
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3'd4: mem4[lineno] <= i;
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3'd4: mem4[lineno] <= i[31:0];
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endcase
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endcase
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end
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end
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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| Line 509... |
Line 504... |
input [37:0] adr;
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input [37:0] adr;
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input [2:0] cnt;
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input [2:0] cnt;
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input exv_i;
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input exv_i;
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input [63:0] i;
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input [63:0] i;
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input err_i;
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input err_i;
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output [319:0] o;
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output [287:0] o;
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output hit;
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output hit;
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input invall;
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input invall;
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input invline;
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input invline;
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wire lv; // line valid
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wire lv; // line valid
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| Line 534... |
Line 529... |
always @(posedge clk)
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always @(posedge clk)
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sel2 <= sel1;
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sel2 <= sel1;
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// An exception is forced to be stored in the event of an error loading the
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// An exception is forced to be stored in the event of an error loading the
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// the instruction line.
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// the instruction line.
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always @(posedge clk)
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always @(posedge clk)
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i1 <= err_i ? {2{16'd0,1'b0,`FLT_IBE,`BRK}} : exv_i ? {2{16'd0,1'b0,`FLT_EXF,`BRK}} : i;
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i1 <= err_i ? {2{15'd0,1'b0,`FLT_IBE,2'b00,`BRK}} : exv_i ? {2{15'd0,1'b0,`FLT_EXF,2'b00,`BRK}} : i;
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always @(posedge clk)
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always @(posedge clk)
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i2 <= i1;
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i2 <= i1;
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wire pe_wr;
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wire pe_wr;
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edge_det u3 (.rst(rst), .clk(clk), .ce(1'b1), .i(wr && cnt==3'd0), .pe(pe_wr), .ne(), .ee() );
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edge_det u3 (.rst(rst), .clk(clk), .ce(1'b1), .i(wr && cnt==3'd0), .pe(pe_wr), .ne(), .ee() );
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| Line 604... |
Line 599... |
input wr;
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input wr;
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input [37:0] adr;
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input [37:0] adr;
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output reg [8:0] lineno;
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output reg [8:0] lineno;
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output hit;
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output hit;
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(* ram_style="block" *)
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reg [32:0] mem0 [0:127];
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reg [32:0] mem0 [0:127];
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reg [32:0] mem1 [0:127];
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reg [32:0] mem1 [0:127];
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reg [32:0] mem2 [0:127];
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reg [32:0] mem2 [0:127];
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reg [32:0] mem3 [0:127];
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reg [32:0] mem3 [0:127];
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reg [37:0] rradr;
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reg [37:0] rradr;
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