| Line 300... |
Line 300... |
endmodule
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endmodule
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|
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// -----------------------------------------------------------------------------
|
// -----------------------------------------------------------------------------
|
// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
|
|
|
module FT64_L1_icache(rst, clk, nxt, wr, en, wadr, adr, i, o, hit, invall, invline);
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module FT64_L1_icache(rst, clk, nxt, wr, wr_ack, en, wadr, adr, i, o, hit, invall, invline);
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parameter CAMTAGS = 1'b0; // 32 way
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parameter CAMTAGS = 1'b0; // 32 way
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parameter FOURWAY = 1'b1;
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parameter FOURWAY = 1'b1;
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input rst;
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input rst;
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input clk;
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input clk;
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input nxt;
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input nxt;
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input wr;
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input wr;
|
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output wr_ack;
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input [8:0] en;
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input [8:0] en;
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input [37:0] adr;
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input [37:0] adr;
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input [37:0] wadr;
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input [37:0] wadr;
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input [287:0] i;
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input [287:0] i;
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output reg [47:0] o;
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output reg [47:0] o;
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| Line 405... |
Line 406... |
);
|
);
|
end
|
end
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end
|
end
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endgenerate
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endgenerate
|
|
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assign hit = taghit & &lv; //[adr[4:2]];
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// Valid if a 64-bit area encompassing a potential 48-bit instruction is valid.
|
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assign hit = taghit & lv[adr[4:2]] & lv[adr[4:2]+4'd1];
|
|
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//always @(radr or ic0 or ic1)
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//always @(radr or ic0 or ic1)
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always @(adr or ic)
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always @(adr or ic)
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o <= ic >> {adr[4:1],4'h0};
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o <= ic >> {adr[4:1],4'h0};
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/*
|
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case(adr[4:2])
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assign wr_ack = wr2;
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3'd0: o <= ic[31:0];
|
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3'd1: o <= ic[63:32];
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3'd2: o <= ic[95:64];
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3'd3: o <= ic[127:96];
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3'd4: o <= ic[159:128];
|
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3'd5: o <= ic[191:160];
|
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3'd6: o <= ic[223:192];
|
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3'd7: o <= ic[255:224];
|
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endcase
|
|
*/
|
|
endmodule
|
endmodule
|
|
|
// -----------------------------------------------------------------------------
|
// -----------------------------------------------------------------------------
|
// -----------------------------------------------------------------------------
|
// -----------------------------------------------------------------------------
|
|
|
| Line 491... |
Line 484... |
// Otherwise the line number would change in the middle of the line. The
|
// Otherwise the line number would change in the middle of the line. The
|
// first half of the line load is signified by an even hexibyte address (
|
// first half of the line load is signified by an even hexibyte address (
|
// address bit 4).
|
// address bit 4).
|
// -----------------------------------------------------------------------------
|
// -----------------------------------------------------------------------------
|
|
|
module FT64_L2_icache(rst, clk, nxt, wr, xsel, adr, cnt, exv_i, i, err_i, o, hit, invall, invline);
|
module FT64_L2_icache(rst, clk, nxt, wr, wr_ack, rd_ack, xsel, adr, cnt, exv_i, i, err_i, o, hit, invall, invline);
|
parameter CAMTAGS = 1'b0; // 32 way
|
parameter CAMTAGS = 1'b0; // 32 way
|
parameter FOURWAY = 1'b1;
|
parameter FOURWAY = 1'b1;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
input nxt;
|
input nxt;
|
input wr;
|
input wr;
|
|
output wr_ack;
|
|
output rd_ack;
|
input xsel;
|
input xsel;
|
input [37:0] adr;
|
input [37:0] adr;
|
input [2:0] cnt;
|
input [2:0] cnt;
|
input exv_i;
|
input exv_i;
|
input [63:0] i;
|
input [63:0] i;
|
| Line 515... |
Line 510... |
wire [8:0] lineno;
|
wire [8:0] lineno;
|
wire taghit;
|
wire taghit;
|
reg wr1,wr2;
|
reg wr1,wr2;
|
reg [2:0] sel1,sel2;
|
reg [2:0] sel1,sel2;
|
reg [63:0] i1,i2;
|
reg [63:0] i1,i2;
|
|
reg [37:0] last_adr;
|
|
|
// Must update the cache memory on the cycle after a write to the tag memmory.
|
// Must update the cache memory on the cycle after a write to the tag memmory.
|
// Otherwise lineno won't be valid. camTag memory takes two clock cycles to update.
|
// Otherwise lineno won't be valid. camTag memory takes two clock cycles to update.
|
always @(posedge clk)
|
always @(posedge clk)
|
wr1 <= wr;
|
wr1 <= wr;
|
| Line 526... |
Line 522... |
wr2 <= wr1;
|
wr2 <= wr1;
|
always @(posedge clk)
|
always @(posedge clk)
|
sel1 <= {xsel,adr[4:3]};
|
sel1 <= {xsel,adr[4:3]};
|
always @(posedge clk)
|
always @(posedge clk)
|
sel2 <= sel1;
|
sel2 <= sel1;
|
|
always @(posedge clk)
|
|
last_adr <= adr;
|
|
|
|
reg [3:0] rdackx;
|
|
always @(posedge clk)
|
|
if (rst)
|
|
rdackx <= 4'b0;
|
|
else begin
|
|
if (last_adr != adr || wr || wr1 || wr2)
|
|
rdackx <= 4'b0;
|
|
else
|
|
rdackx <= {rdackx,~(wr|wr1|wr2)};
|
|
end
|
|
|
|
assign rd_ack = rdackx[3] & ~(last_adr!=adr || wr || wr1 || wr2);
|
|
|
// An exception is forced to be stored in the event of an error loading the
|
// An exception is forced to be stored in the event of an error loading the
|
// the instruction line.
|
// the instruction line.
|
always @(posedge clk)
|
always @(posedge clk)
|
i1 <= err_i ? {2{15'd0,1'b0,`FLT_IBE,2'b00,`BRK}} : exv_i ? {2{15'd0,1'b0,`FLT_EXF,2'b00,`BRK}} : i;
|
i1 <= err_i ? {2{15'd0,1'b0,`FLT_IBE,2'b00,`BRK}} : exv_i ? {2{15'd0,1'b0,`FLT_EXF,2'b00,`BRK}} : i;
|
always @(posedge clk)
|
always @(posedge clk)
|
| Line 586... |
Line 598... |
);
|
);
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
assign hit = taghit & lv;
|
assign hit = taghit & lv;
|
|
assign wr_ack = wr2;
|
|
|
endmodule
|
endmodule
|
|
|
// Four way set associative tag memory
|
// Four way set associative tag memory
|
module FT64_L2_icache_cmptag4way(rst, clk, nxt, wr, adr, lineno, hit);
|
module FT64_L2_icache_cmptag4way(rst, clk, nxt, wr, adr, lineno, hit);
|
