| Line 738... |
Line 738... |
endmodule
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endmodule
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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|
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module FT64_dcache_tag(wclk, wr, wadr, rclk, radr, hit0, hit1);
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module FT64_dcache_tag(wclk, wr, wadr, rclk, radr, whit, hit0, hit1);
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input wclk;
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input wclk;
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input wr;
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input wr;
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input [37:0] wadr;
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input [37:0] wadr;
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input rclk;
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input rclk;
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input [37:0] radr;
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input [37:0] radr;
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output reg whit;
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output reg hit0;
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output reg hit0;
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output reg hit1;
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output reg hit1;
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wire [31:0] tago0, tago1;
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wire [31:0] tago0, tago1;
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wire [31:0] wtago;
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wire [37:0] radrp8 = radr + 32'd32;
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wire [37:0] radrp8 = radr + 32'd32;
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FT64_dcache_tag2 u1 (
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FT64_dcache_tag2 u1 (
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.clka(wclk), // input wire clka
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.clka(wclk), // input wire clka
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.ena(1'b1), // input wire ena
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.ena(1'b1), // input wire ena
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.wea(wr), // input wire [0 : 0] wea
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.wea(wr), // input wire [0 : 0] wea
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.addra(wadr[13:5]), // input wire [8 : 0] addra
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.addra(wadr[13:5]), // input wire [8 : 0] addra
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.dina(wadr[37:14]), // input wire [31 : 0] dina
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.dina(wadr[37:14]), // input wire [31 : 0] dina
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.douta(wtago),
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.clkb(rclk), // input wire clkb
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.clkb(rclk), // input wire clkb
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.web(1'b0),
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.web(1'b0),
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.dinb(32'd0),
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.dinb(32'd0),
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.enb(1'b1),
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.enb(1'b1),
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.addrb(radr[13:5]), // input wire [8 : 0] addrb
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.addrb(radr[13:5]), // input wire [8 : 0] addrb
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| Line 782... |
Line 785... |
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always @(posedge rclk)
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always @(posedge rclk)
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hit0 <= tago0[23:0]==radr[37:14];
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hit0 <= tago0[23:0]==radr[37:14];
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always @(posedge rclk)
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always @(posedge rclk)
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hit1 <= tago1[23:0]==radrp8[37:14];
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hit1 <= tago1[23:0]==radrp8[37:14];
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always @(posedge wclk)
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whit <= wtago[23:0]==wadr[37:14];
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endmodule
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endmodule
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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|
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module FT64_dcache(rst, wclk, wr, sel, wadr, i, li, rclk, rdsize, radr, o, lo, hit, hit0, hit1);
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module FT64_dcache(rst, wclk, wr, sel, wadr, whit, i, li, rclk, rdsize, radr, o, lo, hit, hit0, hit1);
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input rst;
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input rst;
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input wclk;
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input wclk;
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input wr;
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input wr;
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input [7:0] sel;
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input [7:0] sel;
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input [37:0] wadr;
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input [37:0] wadr;
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output whit;
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input [63:0] i;
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input [63:0] i;
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input [255:0] li; // line input
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input [255:0] li; // line input
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input rclk;
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input rclk;
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input [2:0] rdsize;
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input [2:0] rdsize;
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input [37:0] radr;
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input [37:0] radr;
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| Line 847... |
Line 853... |
.wclk(wclk),
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.wclk(wclk),
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.wr(wr),
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.wr(wr),
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.wadr(wadr),
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.wadr(wadr),
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.rclk(rclk),
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.rclk(rclk),
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.radr(radr),
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.radr(radr),
|
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.whit(whit),
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.hit0(hit0a),
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.hit0(hit0a),
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.hit1(hit1a)
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.hit1(hit1a)
|
);
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);
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|
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wire [7:0] v0a = v0 >> radr[4:0];
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wire [7:0] v0a = v0 >> radr[4:0];
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