| Line 36... |
Line 36... |
// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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module FT64_L1_icache_mem(rst, clk, wr, en, lineno, i, o, ov, invall, invline);
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module FT64_L1_icache_mem(rst, clk, wr, en, lineno, i, o, ov, invall, invline);
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parameter pLines = 64;
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parameter pLines = 64;
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parameter pLineWidth = 288;
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parameter pLineWidth = 288;
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localparam pLNMSB = pLines==128 ? 6 : 5;
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input rst;
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input rst;
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input clk;
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input clk;
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input wr;
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input wr;
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input [8:0] en;
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input [8:0] en;
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input [5:0] lineno;
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input [pLNMSB:0] lineno;
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input [pLineWidth-1:0] i;
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input [pLineWidth-1:0] i;
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output [pLineWidth-1:0] o;
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output [pLineWidth-1:0] o;
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output [8:0] ov;
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output [8:0] ov;
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input invall;
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input invall;
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input invline;
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input invline;
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| Line 189... |
Line 190... |
// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// Four way set associative tag memory for L1 cache.
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// Four way set associative tag memory for L1 cache.
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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module FT64_L1_icache_cmptag4way(rst, clk, nxt, wr, adr, lineno, hit);
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module FT64_L1_icache_cmptag4way(rst, clk, nxt, wr, adr, lineno, hit);
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parameter pLines = 64;
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localparam pLNMSB = pLines==128 ? 6 : 5;
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localparam pMSB = pLines==128 ? 9 : 8;
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input rst;
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input rst;
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input clk;
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input clk;
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input nxt;
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input nxt;
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input wr;
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input wr;
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input [37:0] adr;
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input [37:0] adr;
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output reg [5:0] lineno;
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output reg [pLNMSB:0] lineno;
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output hit;
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output hit;
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(* ram_style="distributed" *)
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(* ram_style="distributed" *)
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reg [32:0] mem0 [0:15];
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reg [32:0] mem0 [0:pLines/4-1];
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reg [32:0] mem1 [0:15];
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reg [32:0] mem1 [0:pLines/4-1];
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reg [32:0] mem2 [0:15];
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reg [32:0] mem2 [0:pLines/4-1];
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reg [32:0] mem3 [0:15];
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reg [32:0] mem3 [0:pLines/4-1];
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reg [37:0] rradr;
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reg [37:0] rradr;
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integer n;
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integer n;
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initial begin
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initial begin
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for (n = 0; n < 16; n = n + 1)
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for (n = 0; n < pLines/4; n = n + 1)
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begin
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begin
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mem0[n] = 0;
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mem0[n] = 0;
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mem1[n] = 0;
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mem1[n] = 0;
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mem2[n] = 0;
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mem2[n] = 0;
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mem3[n] = 0;
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mem3[n] = 0;
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| Line 223... |
Line 227... |
if (rst)
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if (rst)
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wlineno <= 6'h00;
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wlineno <= 6'h00;
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else begin
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else begin
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if (wr) begin
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if (wr) begin
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case(lfsro[1:0])
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case(lfsro[1:0])
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2'b00: begin mem0[adr[8:5]] <= adr[37:5]; wlineno <= {2'b00,adr[8:5]}; end
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2'b00: begin mem0[adr[pMSB:5]] <= adr[37:5]; wlineno <= {2'b00,adr[pMSB:5]}; end
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2'b01: begin mem1[adr[8:5]] <= adr[37:5]; wlineno <= {2'b01,adr[8:5]}; end
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2'b01: begin mem1[adr[pMSB:5]] <= adr[37:5]; wlineno <= {2'b01,adr[pMSB:5]}; end
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2'b10: begin mem2[adr[8:5]] <= adr[37:5]; wlineno <= {2'b10,adr[8:5]}; end
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2'b10: begin mem2[adr[pMSB:5]] <= adr[37:5]; wlineno <= {2'b10,adr[pMSB:5]}; end
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2'b11: begin mem3[adr[8:5]] <= adr[37:5]; wlineno <= {2'b11,adr[8:5]}; end
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2'b11: begin mem3[adr[pMSB:5]] <= adr[37:5]; wlineno <= {2'b11,adr[pMSB:5]}; end
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endcase
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endcase
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end
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end
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end
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end
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wire hit0 = mem0[adr[8:5]]==adr[37:5];
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wire hit0 = mem0[adr[pMSB:5]]==adr[37:5];
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wire hit1 = mem1[adr[8:5]]==adr[37:5];
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wire hit1 = mem1[adr[pMSB:5]]==adr[37:5];
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wire hit2 = mem2[adr[8:5]]==adr[37:5];
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wire hit2 = mem2[adr[pMSB:5]]==adr[37:5];
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wire hit3 = mem3[adr[8:5]]==adr[37:5];
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wire hit3 = mem3[adr[pMSB:5]]==adr[37:5];
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always @*
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always @*
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//if (wr2) lineno = wlineno;
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//if (wr2) lineno = wlineno;
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if (hit0) lineno = {2'b00,adr[8:5]};
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if (hit0) lineno = {2'b00,adr[pMSB:5]};
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else if (hit1) lineno = {2'b01,adr[8:5]};
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else if (hit1) lineno = {2'b01,adr[pMSB:5]};
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else if (hit2) lineno = {2'b10,adr[8:5]};
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else if (hit2) lineno = {2'b10,adr[pMSB:5]};
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else lineno = {2'b11,adr[8:5]};
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else lineno = {2'b11,adr[pMSB:5]};
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assign hit = hit0|hit1|hit2|hit3;
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assign hit = hit0|hit1|hit2|hit3;
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endmodule
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endmodule
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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| Line 301... |
Line 305... |
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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module FT64_L1_icache(rst, clk, nxt, wr, wr_ack, en, wadr, adr, i, o, hit, invall, invline);
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module FT64_L1_icache(rst, clk, nxt, wr, wr_ack, en, wadr, adr, i, o, hit, invall, invline);
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parameter pSize = 2;
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parameter CAMTAGS = 1'b0; // 32 way
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parameter CAMTAGS = 1'b0; // 32 way
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parameter FOURWAY = 1'b1;
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parameter FOURWAY = 1'b1;
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localparam pLines = pSize==4 ? 128 : 64;
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localparam pLNMSB = pSize==4 ? 6 : 5;
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input rst;
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input rst;
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input clk;
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input clk;
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input nxt;
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input nxt;
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input wr;
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input wr;
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output wr_ack;
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output wr_ack;
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| Line 320... |
Line 327... |
input invline;
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input invline;
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wire [287:0] ic;
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wire [287:0] ic;
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reg [287:0] i1, i2;
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reg [287:0] i1, i2;
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wire [8:0] lv; // line valid
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wire [8:0] lv; // line valid
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wire [5:0] lineno;
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wire [pLNMSB:0] lineno;
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wire [5:0] wlineno;
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wire [pLNMSB:0] wlineno;
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wire taghit;
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wire taghit;
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reg wr1,wr2;
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reg wr1,wr2;
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reg [8:0] en1, en2;
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reg [8:0] en1, en2;
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reg invline1, invline2;
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reg invline1, invline2;
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| Line 349... |
Line 356... |
invline2 <= invline1;
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invline2 <= invline1;
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generate begin : tags
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generate begin : tags
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if (FOURWAY) begin
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if (FOURWAY) begin
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FT64_L1_icache_mem u1
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FT64_L1_icache_mem #(.pLines(pLines)) u1
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(
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(
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.rst(rst),
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.rst(rst),
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.clk(clk),
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.clk(clk),
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.wr(wr1),
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.wr(wr1),
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.en(en1),
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.en(en1),
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| Line 363... |
Line 370... |
.ov(lv),
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.ov(lv),
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.invall(invall),
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.invall(invall),
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.invline(invline1)
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.invline(invline1)
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);
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);
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FT64_L1_icache_cmptag4way u3
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FT64_L1_icache_cmptag4way #(.pLines(pLines)) u3
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(
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(
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.rst(rst),
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.rst(rst),
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.clk(clk),
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.clk(clk),
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.nxt(nxt),
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.nxt(nxt),
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.wr(wr),
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.wr(wr),
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