URL
https://opencores.org/ocsvn/thor/thor/trunk
[/] [thor/] [trunk/] [FT64v5/] [rtl/] [common/] [FT64_config.vh] - Diff between revs 51 and 52
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 51 |
Rev 52 |
| Line 26... |
Line 26... |
//`define SUPPORT_SMT 1'b1
|
//`define SUPPORT_SMT 1'b1
|
//`define DEBUG_LOGIC 1'b1
|
//`define DEBUG_LOGIC 1'b1
|
|
|
`define AMSB 31
|
`define AMSB 31
|
`define ABITS `AMSB:0
|
`define ABITS `AMSB:0
|
`define QBITS 2:0
|
`define QBITS 3:0
|
`define QENTRIES 8
|
`define QENTRIES 10
|
`define XBITS 7:0
|
`define XBITS 7:0
|
|
|
//`define SUPPORT_DBG 1'b1
|
//`define SUPPORT_DBG 1'b1
|
`define FULL_ISSUE_LOGIC 1'b1
|
`define FULL_ISSUE_LOGIC 1'b1
|
|
|
| Line 63... |
Line 63... |
`define HAS_WB 1'b1
|
`define HAS_WB 1'b1
|
`define WB_DEPTH 8 // must be one more than desired depth
|
`define WB_DEPTH 8 // must be one more than desired depth
|
|
|
// Uncomment to allow SIMD operations
|
// Uncomment to allow SIMD operations
|
`define SIMD 1'b1
|
`define SIMD 1'b1
|
No newline at end of file
|
No newline at end of file
|
|
|
|
// Comment the following to disable registering the output of instruction decoders.
|
|
`define REGISTER_DECODE
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.