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[/] [thor/] [trunk/] [FT64v5/] [rtl/] [common/] [FT64_idecoder.v] - Diff between revs 48 and 49
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| Rev 48 |
Rev 49 |
| Line 147... |
Line 147... |
reg IsFlowCtrl;
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reg IsFlowCtrl;
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always @*
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always @*
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case(instr[`INSTRUCTION_OP])
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case(instr[`INSTRUCTION_OP])
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`BRK: IsFlowCtrl <= TRUE;
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`BRK: IsFlowCtrl <= TRUE;
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`RR: case(instr[`INSTRUCTION_S2])
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`R2: case(instr[`INSTRUCTION_S2])
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`RTI: IsFlowCtrl <= TRUE;
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`RTI: IsFlowCtrl <= TRUE;
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default: IsFlowCtrl <= FALSE;
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default: IsFlowCtrl <= FALSE;
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endcase
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endcase
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`Bcc: IsFlowCtrl <= TRUE;
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`Bcc: IsFlowCtrl <= TRUE;
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`BBc: IsFlowCtrl <= TRUE;
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`BBc: IsFlowCtrl <= TRUE;
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| Line 222... |
Line 222... |
endcase
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endcase
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`Bcc: fnCanException = TRUE;
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`Bcc: fnCanException = TRUE;
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`BEQI: fnCanException = TRUE;
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`BEQI: fnCanException = TRUE;
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`CHK: fnCanException = TRUE;
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`CHK: fnCanException = TRUE;
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default:
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default:
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// Stores can stil exception if there is a write buffer, but we allow following
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// stores to be issued by ignoring the fact they can exception because the stores
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// can be undone by invalidating the write buffer.
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`ifdef HAS_WB
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fnCanException = IsLoad(isn);
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`else
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fnCanException = IsMem(isn);
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fnCanException = IsMem(isn);
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`endif
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endcase
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endcase
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end
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end
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endfunction
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endfunction
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function IsLoad;
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function IsLoad;
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