// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2017-2018 Robert Finch, Waterloo
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// \\__/ o\ (C) 2017-2018 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// FT64_idecoder.v
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// FT64_idecoder.v
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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`include ".\FT64_defines.vh"
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`include ".\FT64_defines.vh"
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module FT64_idecoder(clk,idv_i,id_i,instr,vl,ven,thrd,predict_taken,Rt,bus,id_o,idv_o);
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module FT64_idecoder(clk,idv_i,id_i,instr,vl,ven,thrd,predict_taken,Rt,bus,id_o,idv_o);
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input clk;
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input clk;
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input idv_i;
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input idv_i;
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input [4:0] id_i;
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input [4:0] id_i;
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input [47:0] instr;
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input [47:0] instr;
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input [7:0] vl;
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input [7:0] vl;
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input [5:0] ven;
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input [5:0] ven;
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input thrd;
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input thrd;
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input predict_taken;
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input predict_taken;
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input [4:0] Rt;
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input [4:0] Rt;
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output reg [127:0] bus;
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output reg [127:0] bus;
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output reg [4:0] id_o;
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output reg [4:0] id_o;
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output reg idv_o;
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output reg idv_o;
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parameter TRUE = 1'b1;
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parameter TRUE = 1'b1;
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parameter FALSE = 1'b0;
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parameter FALSE = 1'b0;
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// Memory access sizes
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parameter byt = 3'd0;
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parameter wyde = 3'd1;
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parameter tetra = 3'd2;
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parameter octa = 3'd3;
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// Really IsPredictableBranch
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// Really IsPredictableBranch
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// Does not include BccR's
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// Does not include BccR's
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//function IsBranch;
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//function IsBranch;
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//input [47:0] isn;
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//input [47:0] isn;
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//casez(isn[`INSTRUCTION_OP])
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//casez(isn[`INSTRUCTION_OP])
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//`Bcc: IsBranch = TRUE;
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//`Bcc: IsBranch = TRUE;
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//`BBc: IsBranch = TRUE;
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//`BBc: IsBranch = TRUE;
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//`BEQI: IsBranch = TRUE;
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//`BEQI: IsBranch = TRUE;
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//`CHK: IsBranch = TRUE;
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//`CHK: IsBranch = TRUE;
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//default: IsBranch = FALSE;
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//default: IsBranch = FALSE;
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//endcase
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//endcase
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//endfunction
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//endfunction
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wire iAlu;
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wire iAlu;
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mIsALU uialu1
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mIsALU uialu1
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(
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(
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.instr(instr),
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.instr(instr),
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.IsALU(iAlu)
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.IsALU(iAlu)
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);
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);
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reg IsALU;
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reg IsALU;
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always @*
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always @*
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case(instr[`INSTRUCTION_OP])
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case(instr[`INSTRUCTION_OP])
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`R2: if (instr[`INSTRUCTION_L2]==2'b00)
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`R2:
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if (instr[`INSTRUCTION_L2]==2'b00)
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case(instr[`INSTRUCTION_S2])
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case(instr[`INSTRUCTION_S2])
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`VMOV: IsALU = TRUE;
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`VMOV: IsALU = TRUE;
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`RTI: IsALU = FALSE;
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`RTI: IsALU = FALSE;
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default: IsALU = TRUE;
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default: IsALU = TRUE;
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endcase
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endcase
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else
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else
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IsALU = TRUE;
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IsALU = TRUE;
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`BRK: IsALU = FALSE;
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`BRK: IsALU = FALSE;
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`Bcc: IsALU = FALSE;
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`Bcc: IsALU = FALSE;
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`BBc: IsALU = FALSE;
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`BBc: IsALU = FALSE;
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`BEQI: IsALU = FALSE;
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`BEQI: IsALU = FALSE;
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`CHK: IsALU = FALSE;
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`CHK: IsALU = FALSE;
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`JAL: IsALU = FALSE;
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`JAL: IsALU = FALSE;
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`JMP: IsALU = FALSE;
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`JMP: IsALU = FALSE;
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`CALL: IsALU = FALSE;
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`CALL: IsALU = FALSE;
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`RET: IsALU = FALSE;
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`RET: IsALU = FALSE;
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`FVECTOR:
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`FVECTOR:
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case(instr[`INSTRUCTION_S2])
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case(instr[`INSTRUCTION_S2])
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`VSHL,`VSHR,`VASR: IsALU = TRUE;
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`VSHL,`VSHR,`VASR: IsALU = TRUE;
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default: IsALU = FALSE; // Integer
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default: IsALU = FALSE; // Integer
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endcase
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endcase
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`IVECTOR:
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`IVECTOR:
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case(instr[`INSTRUCTION_S2])
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case(instr[`INSTRUCTION_S2])
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`VSHL,`VSHR,`VASR: IsALU = TRUE;
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`VSHL,`VSHR,`VASR: IsALU = TRUE;
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default: IsALU = TRUE; // Integer
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default: IsALU = TRUE; // Integer
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endcase
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endcase
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`FLOAT: IsALU = FALSE;
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`FLOAT: IsALU = FALSE;
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default: IsALU = TRUE;
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default: IsALU = TRUE;
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endcase
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endcase
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function IsAlu0Only;
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function IsAlu0Only;
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input [47:0] isn;
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input [47:0] isn;
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begin
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begin
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case(isn[`INSTRUCTION_OP])
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case(isn[`INSTRUCTION_OP])
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`R2:
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`R2:
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if (isn[`INSTRUCTION_L2]==2'b00)
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if (isn[`INSTRUCTION_L2]==2'b00)
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case(isn[`INSTRUCTION_S2])
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case(isn[`INSTRUCTION_S2])
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`R1: IsAlu0Only = TRUE;
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`R1: IsAlu0Only = TRUE;
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`SHIFTR,`SHIFT31,`SHIFT63:
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`SHIFTR,`SHIFT31,`SHIFT63:
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IsAlu0Only = TRUE;
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IsAlu0Only = TRUE;
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`MULU,`MULSU,`MUL,
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`MULU,`MULSU,`MUL,
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`DIVMODU,`DIVMODSU,`DIVMOD: IsAlu0Only = TRUE;
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`MULUH,`MULSUH,`MULH,
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`MODU,`MODSU,`MOD: IsAlu0Only = TRUE;
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`DIVU,`DIVSU,`DIV: IsAlu0Only = TRUE;
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`MIN,`MAX: IsAlu0Only = TRUE;
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`MIN,`MAX: IsAlu0Only = TRUE;
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default: IsAlu0Only = FALSE;
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default: IsAlu0Only = FALSE;
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endcase
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endcase
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else
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else
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IsAlu0Only = FALSE;
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IsAlu0Only = FALSE;
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`MEMNDX: IsAlu0Only = TRUE;
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`MEMNDX: IsAlu0Only = TRUE;
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`IVECTOR,`FVECTOR:
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`IVECTOR,`FVECTOR:
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case(isn[`INSTRUCTION_S2])
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case(isn[`INSTRUCTION_S2])
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`VSHL,`VSHR,`VASR: IsAlu0Only = TRUE;
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`VSHL,`VSHR,`VASR: IsAlu0Only = TRUE;
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default: IsAlu0Only = FALSE;
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default: IsAlu0Only = FALSE;
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endcase
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endcase
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`BITFIELD: IsAlu0Only = TRUE;
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`BITFIELD: IsAlu0Only = TRUE;
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`MULUI,`MULI,
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`MULUI,`MULI,
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`DIVUI,`DIVI,
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`DIVUI,`DIVI,
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`MODI: IsAlu0Only = TRUE;
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`MODI: IsAlu0Only = TRUE;
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`CSRRW: IsAlu0Only = TRUE;
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`CSRRW: IsAlu0Only = TRUE;
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default: IsAlu0Only = FALSE;
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default: IsAlu0Only = FALSE;
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endcase
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endcase
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end
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end
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endfunction
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endfunction
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function IsFPU;
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function IsFPU;
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input [47:0] isn;
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input [47:0] isn;
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begin
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begin
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case(isn[`INSTRUCTION_OP])
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case(isn[`INSTRUCTION_OP])
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`FLOAT: IsFPU = TRUE;
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`FLOAT: IsFPU = TRUE;
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`FVECTOR:
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`FVECTOR:
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case(isn[`INSTRUCTION_S2])
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case(isn[`INSTRUCTION_S2])
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`VSHL,`VSHR,`VASR: IsFPU = FALSE;
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`VSHL,`VSHR,`VASR: IsFPU = FALSE;
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default: IsFPU = TRUE;
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default: IsFPU = TRUE;
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endcase
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endcase
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default: IsFPU = FALSE;
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default: IsFPU = FALSE;
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endcase
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endcase
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end
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end
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endfunction
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endfunction
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reg IsFlowCtrl;
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reg IsFlowCtrl;
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always @*
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always @*
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case(instr[`INSTRUCTION_OP])
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case(instr[`INSTRUCTION_OP])
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`BRK: IsFlowCtrl <= TRUE;
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`BRK: IsFlowCtrl <= TRUE;
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`R2: case(instr[`INSTRUCTION_S2])
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`R2: case(instr[`INSTRUCTION_S2])
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`RTI: IsFlowCtrl <= TRUE;
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`RTI: IsFlowCtrl <= TRUE;
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default: IsFlowCtrl <= FALSE;
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default: IsFlowCtrl <= FALSE;
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endcase
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endcase
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`Bcc: IsFlowCtrl <= TRUE;
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`Bcc: IsFlowCtrl <= TRUE;
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`BBc: IsFlowCtrl <= TRUE;
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`BBc: IsFlowCtrl <= TRUE;
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`BEQI: IsFlowCtrl <= TRUE;
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`BEQI: IsFlowCtrl <= TRUE;
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`CHK: IsFlowCtrl <= TRUE;
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`CHK: IsFlowCtrl <= TRUE;
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`JAL: IsFlowCtrl <= TRUE;
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`JAL: IsFlowCtrl <= TRUE;
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`JMP: IsFlowCtrl <= TRUE;
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`JMP: IsFlowCtrl <= TRUE;
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`CALL: IsFlowCtrl <= TRUE;
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`CALL: IsFlowCtrl <= TRUE;
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`RET: IsFlowCtrl <= TRUE;
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`RET: IsFlowCtrl <= TRUE;
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default: IsFlowCtrl <= FALSE;
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default: IsFlowCtrl <= FALSE;
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endcase
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endcase
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//function IsFlowCtrl;
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//function IsFlowCtrl;
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//input [47:0] isn;
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//input [47:0] isn;
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//begin
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//begin
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//case(isn[`INSTRUCTION_OP])
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//case(isn[`INSTRUCTION_OP])
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//`BRK: IsFlowCtrl = TRUE;
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//`BRK: IsFlowCtrl = TRUE;
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//`RR: case(isn[`INSTRUCTION_S2])
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//`RR: case(isn[`INSTRUCTION_S2])
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// `RTI: IsFlowCtrl = TRUE;
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// `RTI: IsFlowCtrl = TRUE;
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// default: IsFlowCtrl = FALSE;
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// default: IsFlowCtrl = FALSE;
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// endcase
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// endcase
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//`Bcc: IsFlowCtrl = TRUE;
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//`Bcc: IsFlowCtrl = TRUE;
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//`BBc: IsFlowCtrl = TRUE;
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//`BBc: IsFlowCtrl = TRUE;
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//`BEQI: IsFlowCtrl = TRUE;
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//`BEQI: IsFlowCtrl = TRUE;
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//`CHK: IsFlowCtrl = TRUE;
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//`CHK: IsFlowCtrl = TRUE;
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//`JAL: IsFlowCtrl = TRUE;
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//`JAL: IsFlowCtrl = TRUE;
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//`JMP: IsFlowCtrl = TRUE;
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//`JMP: IsFlowCtrl = TRUE;
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//`CALL: IsFlowCtrl = TRUE;
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//`CALL: IsFlowCtrl = TRUE;
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//`RET: IsFlowCtrl = TRUE;
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//`RET: IsFlowCtrl = TRUE;
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//default: IsFlowCtrl = FALSE;
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//default: IsFlowCtrl = FALSE;
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//endcase
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//endcase
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//end
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//end
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//endfunction
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//endfunction
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// fnCanException
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// fnCanException
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//
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//
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// Used by memory issue logic.
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// Used by memory issue logic.
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// Returns TRUE if the instruction can cause an exception.
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// Returns TRUE if the instruction can cause an exception.
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// In debug mode any instruction could potentially cause a breakpoint exception.
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// In debug mode any instruction could potentially cause a breakpoint exception.
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// Rather than check all the addresses for potential debug exceptions it's
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// Rather than check all the addresses for potential debug exceptions it's
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// simpler to just have it so that all instructions could exception. This will
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// simpler to just have it so that all instructions could exception. This will
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// slow processing down somewhat as stores will only be done at the head of the
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// slow processing down somewhat as stores will only be done at the head of the
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// instruction queue, but it's debug mode so we probably don't care.
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// instruction queue, but it's debug mode so we probably don't care.
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//
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//
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function fnCanException;
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function fnCanException;
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input [47:0] isn;
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input [47:0] isn;
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begin
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begin
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// ToDo add debug_on as input
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// ToDo add debug_on as input
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`ifdef SUPPORT_DBG
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`ifdef SUPPORT_DBG
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if (debug_on)
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if (debug_on)
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fnCanException = `TRUE;
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fnCanException = `TRUE;
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else
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else
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`endif
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`endif
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case(isn[`INSTRUCTION_OP])
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case(isn[`INSTRUCTION_OP])
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`FLOAT:
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`FLOAT:
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case(isn[`INSTRUCTION_S2])
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case(isn[`INSTRUCTION_S2])
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`FDIV,`FMUL,`FADD,`FSUB,`FTX:
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`FDIV,`FMUL,`FADD,`FSUB,`FTX:
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fnCanException = `TRUE;
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fnCanException = `TRUE;
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default: fnCanException = `FALSE;
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default: fnCanException = `FALSE;
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endcase
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endcase
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`ADDI,`DIVI,`MODI,`MULI:
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`ADDI,`DIVI,`MODI,`MULI:
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fnCanException = `TRUE;
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fnCanException = `TRUE;
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`R2:
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`R2:
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case(isn[`INSTRUCTION_S2])
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case(isn[`INSTRUCTION_S2])
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`ADD,`SUB,`MUL,`DIVMOD,`MULSU,`DIVMODSU: fnCanException = TRUE;
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`ADD,`SUB,`MUL,
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`DIV,`MULSU,`DIVSU,
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`MOD,`MODSU:
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fnCanException = TRUE;
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`RTI: fnCanException = TRUE;
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`RTI: fnCanException = TRUE;
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default: fnCanException = FALSE;
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default: fnCanException = FALSE;
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endcase
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endcase
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`Bcc: fnCanException = TRUE;
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`Bcc: fnCanException = TRUE;
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`BEQI: fnCanException = TRUE;
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`BEQI: fnCanException = TRUE;
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`CHK: fnCanException = TRUE;
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`CHK: fnCanException = TRUE;
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default:
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default:
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// Stores can stil exception if there is a write buffer, but we allow following
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// Stores can stil exception if there is a write buffer, but we allow following
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// stores to be issued by ignoring the fact they can exception because the stores
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// stores to be issued by ignoring the fact they can exception because the stores
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// can be undone by invalidating the write buffer.
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// can be undone by invalidating the write buffer.
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`ifdef HAS_WB
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`ifdef HAS_WB
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fnCanException = IsLoad(isn);
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fnCanException = IsLoad(isn);
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`else
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`else
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fnCanException = IsMem(isn);
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fnCanException = IsMem(isn);
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`endif
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`endif
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endcase
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endcase
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end
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end
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endfunction
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endfunction
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function IsLoad;
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function IsLoad;
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input [47:0] isn;
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input [47:0] isn;
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case(isn[`INSTRUCTION_OP])
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case(isn[`INSTRUCTION_OP])
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`MEMNDX:
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`MEMNDX:
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if (isn[`INSTRUCTION_L2]==2'b00)
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if (isn[`INSTRUCTION_L2]==2'b00)
|
case(isn[`INSTRUCTION_S2])
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case(isn[`INSTRUCTION_S2])
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`LBX: IsLoad = TRUE;
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`LBX: IsLoad = TRUE;
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`LBUX: IsLoad = TRUE;
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`LBUX: IsLoad = TRUE;
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`LCX: IsLoad = TRUE;
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`LCX: IsLoad = TRUE;
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`LCUX: IsLoad = TRUE;
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`LCUX: IsLoad = TRUE;
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`LHX: IsLoad = TRUE;
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`LHX: IsLoad = TRUE;
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`LHUX: IsLoad = TRUE;
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`LHUX: IsLoad = TRUE;
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`LWX: IsLoad = TRUE;
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`LWX: IsLoad = TRUE;
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`LVBX: IsLoad = TRUE;
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`LVBUX: IsLoad = TRUE;
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`LVCX: IsLoad = TRUE;
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`LVCUX: IsLoad = TRUE;
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`LVHX: IsLoad = TRUE;
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`LVHUX: IsLoad = TRUE;
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`LVWX: IsLoad = TRUE;
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`LWRX: IsLoad = TRUE;
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`LWRX: IsLoad = TRUE;
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`LVX: IsLoad = TRUE;
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`LVX: IsLoad = TRUE;
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`LVx: IsLoad = TRUE;
|
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default: IsLoad = FALSE;
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default: IsLoad = FALSE;
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endcase
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endcase
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else
|
else
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IsLoad = FALSE;
|
IsLoad = FALSE;
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`LB: IsLoad = TRUE;
|
`LB: IsLoad = TRUE;
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`LBU: IsLoad = TRUE;
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`LBU: IsLoad = TRUE;
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`Lx: IsLoad = TRUE;
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`Lx: IsLoad = TRUE;
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`LxU: IsLoad = TRUE;
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`LxU: IsLoad = TRUE;
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`LWR: IsLoad = TRUE;
|
`LWR: IsLoad = TRUE;
|
`LV: IsLoad = TRUE;
|
`LV: IsLoad = TRUE;
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`LVx: IsLoad = TRUE;
|
`LVx: IsLoad = TRUE;
|
default: IsLoad = FALSE;
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default: IsLoad = FALSE;
|
endcase
|
endcase
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endfunction
|
endfunction
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|
|
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function IsVolatileLoad;
|
|
input [47:0] isn;
|
|
case(isn[`INSTRUCTION_OP])
|
|
`MEMNDX:
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
|
case(isn[`INSTRUCTION_S2])
|
|
`LWRX: IsVolatileLoad = TRUE;
|
|
`LVBX: IsVolatileLoad = TRUE;
|
|
`LVBUX: IsVolatileLoad = TRUE;
|
|
`LVCX: IsVolatileLoad = TRUE;
|
|
`LVCUX: IsVolatileLoad = TRUE;
|
|
`LVHX: IsVolatileLoad = TRUE;
|
|
`LVHUX: IsVolatileLoad = TRUE;
|
|
`LVWX: IsVolatileLoad = TRUE;
|
|
default: IsVolatileLoad = FALSE;
|
|
endcase
|
|
else
|
|
IsVolatileLoad = FALSE;
|
|
`LWR: IsVolatileLoad = TRUE;
|
|
`LVx: IsVolatileLoad = TRUE;
|
|
default: IsVolatileLoad = FALSE;
|
|
endcase
|
|
endfunction
|
|
|
|
function IsStore;
|
|
input [47:0] isn;
|
|
case(isn[`INSTRUCTION_OP])
|
|
`MEMNDX:
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
|
case(isn[`INSTRUCTION_S2])
|
|
`SBX: IsStore = TRUE;
|
|
`SCX: IsStore = TRUE;
|
|
`SHX: IsStore = TRUE;
|
|
`SWX: IsStore = TRUE;
|
|
`SWCX: IsStore = TRUE;
|
|
`SVX: IsStore = TRUE;
|
|
`CASX: IsStore = TRUE;
|
|
`INC: IsStore = TRUE;
|
|
default: IsStore = FALSE;
|
|
endcase
|
|
else
|
|
IsStore = FALSE;
|
|
`SB: IsStore = TRUE;
|
|
`Sx: IsStore = TRUE;
|
|
`SWC: IsStore = TRUE;
|
|
`INC: IsStore = TRUE;
|
|
`SV: IsStore = TRUE;
|
|
`CAS: IsStore = TRUE;
|
|
`AMO: IsStore = TRUE;
|
|
default: IsStore = FALSE;
|
|
endcase
|
|
endfunction
|
|
|
function [0:0] IsMem;
|
function [0:0] IsMem;
|
input [47:0] isn;
|
input [47:0] isn;
|
case(isn[`INSTRUCTION_OP])
|
case(isn[`INSTRUCTION_OP])
|
`MEMNDX: IsMem = TRUE;
|
`MEMNDX: IsMem = TRUE;
|
`AMO: IsMem = TRUE;
|
`AMO: IsMem = TRUE;
|
`LB: IsMem = TRUE;
|
`LB: IsMem = TRUE;
|
`LBU: IsMem = TRUE;
|
`LBU: IsMem = TRUE;
|
`Lx: IsMem = TRUE;
|
`Lx: IsMem = TRUE;
|
`LxU: IsMem = TRUE;
|
`LxU: IsMem = TRUE;
|
`LWR: IsMem = TRUE;
|
`LWR: IsMem = TRUE;
|
`LV,`SV: IsMem = TRUE;
|
`LV,`SV: IsMem = TRUE;
|
`INC: IsMem = TRUE;
|
`INC: IsMem = TRUE;
|
`SB: IsMem = TRUE;
|
`SB: IsMem = TRUE;
|
`Sx: IsMem = TRUE;
|
`Sx: IsMem = TRUE;
|
`SWC: IsMem = TRUE;
|
`SWC: IsMem = TRUE;
|
`CAS: IsMem = TRUE;
|
`CAS: IsMem = TRUE;
|
`LVx: IsMem = TRUE;
|
`LVx: IsMem = TRUE;
|
default: IsMem = FALSE;
|
default: IsMem = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function IsMemNdx;
|
function IsMemNdx;
|
input [47:0] isn;
|
input [47:0] isn;
|
case(isn[`INSTRUCTION_OP])
|
case(isn[`INSTRUCTION_OP])
|
`MEMNDX: IsMemNdx = TRUE;
|
`MEMNDX: IsMemNdx = TRUE;
|
default: IsMemNdx = FALSE;
|
default: IsMemNdx = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
|
function [2:0] MemSize;
|
|
input [47:0] isn;
|
|
case(isn[`INSTRUCTION_OP])
|
|
`MEMNDX:
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
|
case(isn[`INSTRUCTION_S2])
|
|
`LVBX,`LVBUX: MemSize = byt;
|
|
`LBX,`LBUX,`SBX: MemSize = byt;
|
|
`LVCX,`LVCUX: MemSize = wyde;
|
|
`LCX,`LCUX,`SCX: MemSize = wyde;
|
|
`LVHX,`LVHUX: MemSize = tetra;
|
|
`LHX,`SHX: MemSize = tetra;
|
|
`LHUX: MemSize = tetra;
|
|
`LVWX: MemSize = octa;
|
|
`LWX,`SWX: MemSize = octa;
|
|
`LWRX,`SWCX: MemSize = octa;
|
|
`LVX,`SVX: MemSize = octa;
|
|
`LVx:
|
|
case(isn[25:23])
|
|
3'd0,3'd1: MemSize = byt;
|
|
3'd2,3'd3: MemSize = wyde;
|
|
3'd4,3'd5: MemSize = tetra;
|
|
default: MemSize = octa;
|
|
endcase
|
|
default: MemSize = octa;
|
|
endcase
|
|
else
|
|
MemSize = octa;
|
|
`LB,`LBU,`SB: MemSize = byt;
|
|
`Lx,`LxU,`Sx,`LVx:
|
|
casez(isn[20:18])
|
|
3'b100: MemSize = octa;
|
|
3'b?10: MemSize = tetra;
|
|
3'b??1: MemSize = wyde;
|
|
default: MemSize = octa;
|
|
endcase
|
|
`LWR,`SWC: MemSize = octa;
|
|
`LV,`SV: MemSize = octa;
|
|
`AMO:
|
|
case(isn[23:21])
|
|
3'd0: MemSize = byt;
|
|
3'd1: MemSize = wyde;
|
|
3'd2: MemSize = tetra;
|
|
3'd3: MemSize = octa;
|
|
default: MemSize = octa;
|
|
endcase
|
|
default: MemSize = octa;
|
|
endcase
|
|
endfunction
|
|
|
function IsCAS;
|
function IsCAS;
|
input [47:0] isn;
|
input [47:0] isn;
|
case(isn[`INSTRUCTION_OP])
|
case(isn[`INSTRUCTION_OP])
|
`MEMNDX:
|
`MEMNDX:
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`CASX: IsCAS = TRUE;
|
`CASX: IsCAS = TRUE;
|
default: IsCAS = FALSE;
|
default: IsCAS = FALSE;
|
endcase
|
endcase
|
else
|
else
|
IsCAS = FALSE;
|
IsCAS = FALSE;
|
`CAS: IsCAS = TRUE;
|
`CAS: IsCAS = TRUE;
|
default: IsCAS = FALSE;
|
default: IsCAS = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function IsAMO;
|
function IsAMO;
|
input [47:0] isn;
|
input [47:0] isn;
|
case(isn[`INSTRUCTION_OP])
|
case(isn[`INSTRUCTION_OP])
|
`AMO: IsAMO = TRUE;
|
`AMO: IsAMO = TRUE;
|
default: IsAMO = FALSE;
|
default: IsAMO = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function IsInc;
|
function IsInc;
|
input [47:0] isn;
|
input [47:0] isn;
|
case(isn[`INSTRUCTION_OP])
|
case(isn[`INSTRUCTION_OP])
|
`MEMNDX:
|
`MEMNDX:
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`INC: IsInc = TRUE;
|
`INC: IsInc = TRUE;
|
default: IsInc = FALSE;
|
default: IsInc = FALSE;
|
endcase
|
endcase
|
else
|
else
|
IsInc = FALSE;
|
IsInc = FALSE;
|
`INC: IsInc = TRUE;
|
`INC: IsInc = TRUE;
|
default: IsInc = FALSE;
|
default: IsInc = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function IsSync;
|
function IsSync;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsSync = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`SYNC);
|
IsSync = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`SYNC);
|
endfunction
|
endfunction
|
|
|
function IsFSync;
|
function IsFSync;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsFSync = (isn[`INSTRUCTION_OP]==`FLOAT && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`FSYNC);
|
IsFSync = (isn[`INSTRUCTION_OP]==`FLOAT && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`FSYNC);
|
endfunction
|
endfunction
|
|
|
function IsMemdb;
|
function IsMemdb;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsMemdb = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`MEMDB);
|
IsMemdb = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`MEMDB);
|
endfunction
|
endfunction
|
|
|
function IsMemsb;
|
function IsMemsb;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsMemsb = (isn[`INSTRUCTION_OP]==`RR && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`MEMSB);
|
IsMemsb = (isn[`INSTRUCTION_OP]==`RR && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`MEMSB);
|
endfunction
|
endfunction
|
|
|
function IsSEI;
|
function IsSEI;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsSEI = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`SEI);
|
IsSEI = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`SEI);
|
endfunction
|
endfunction
|
|
|
function IsShift48;
|
function IsShift48;
|
input [47:0] isn;
|
input [47:0] isn;
|
case(isn[`INSTRUCTION_OP])
|
case(isn[`INSTRUCTION_OP])
|
`R2:
|
`R2:
|
if (isn[`INSTRUCTION_L2]==2'b01)
|
if (isn[`INSTRUCTION_L2]==2'b01)
|
case(isn[47:42])
|
case(isn[47:42])
|
`SHIFTR: IsShift48 = TRUE;
|
`SHIFTR: IsShift48 = TRUE;
|
default: IsShift48 = FALSE;
|
default: IsShift48 = FALSE;
|
endcase
|
endcase
|
else
|
else
|
IsShift48 = FALSE;
|
IsShift48 = FALSE;
|
default: IsShift48 = FALSE;
|
default: IsShift48 = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function IsLWRX;
|
function IsLWRX;
|
input [47:0] isn;
|
input [47:0] isn;
|
case(isn[`INSTRUCTION_OP])
|
case(isn[`INSTRUCTION_OP])
|
`MEMNDX:
|
`MEMNDX:
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`LWRX: IsLWRX = TRUE;
|
`LWRX: IsLWRX = TRUE;
|
default: IsLWRX = FALSE;
|
default: IsLWRX = FALSE;
|
endcase
|
endcase
|
else
|
else
|
IsLWRX = FALSE;
|
IsLWRX = FALSE;
|
default: IsLWRX = FALSE;
|
default: IsLWRX = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
// Aquire / release bits are only available on indexed SWC / LWR
|
// Aquire / release bits are only available on indexed SWC / LWR
|
function IsSWCX;
|
function IsSWCX;
|
input [47:0] isn;
|
input [47:0] isn;
|
case(isn[`INSTRUCTION_OP])
|
case(isn[`INSTRUCTION_OP])
|
`MEMNDX:
|
`MEMNDX:
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`SWCX: IsSWCX = TRUE;
|
`SWCX: IsSWCX = TRUE;
|
default: IsSWCX = FALSE;
|
default: IsSWCX = FALSE;
|
endcase
|
endcase
|
else
|
else
|
IsSWCX = FALSE;
|
IsSWCX = FALSE;
|
default: IsSWCX = FALSE;
|
default: IsSWCX = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function IsJmp;
|
function IsJmp;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsJmp = isn[`INSTRUCTION_OP]==`JMP && isn[7]==1'b0;
|
IsJmp = isn[`INSTRUCTION_OP]==`JMP && isn[7]==1'b0;
|
endfunction
|
endfunction
|
|
|
// Really IsPredictableBranch
|
// Really IsPredictableBranch
|
// Does not include BccR's
|
// Does not include BccR's
|
function IsBranch;
|
function IsBranch;
|
input [47:0] isn;
|
input [47:0] isn;
|
casez(isn[`INSTRUCTION_OP])
|
casez(isn[`INSTRUCTION_OP])
|
`Bcc: IsBranch = TRUE;
|
`Bcc: IsBranch = TRUE;
|
`BBc: IsBranch = TRUE;
|
`BBc: IsBranch = TRUE;
|
`BEQI: IsBranch = TRUE;
|
`BEQI: IsBranch = TRUE;
|
`CHK: IsBranch = TRUE;
|
`CHK: IsBranch = TRUE;
|
default: IsBranch = FALSE;
|
default: IsBranch = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function IsBrk;
|
function IsBrk;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsBrk = isn[`INSTRUCTION_OP]==`BRK && isn[`INSTRUCTION_L2]==2'b00;
|
IsBrk = isn[`INSTRUCTION_OP]==`BRK && isn[`INSTRUCTION_L2]==2'b00;
|
endfunction
|
endfunction
|
|
|
function IsRti;
|
function IsRti;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsRti = isn[`INSTRUCTION_OP]==`RR && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`RTI;
|
IsRti = isn[`INSTRUCTION_OP]==`RR && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`RTI;
|
endfunction
|
endfunction
|
|
|
// Has an extendable 14-bit constant
|
// Has an extendable 14-bit constant
|
function HasConst;
|
function HasConst;
|
input [47:0] isn;
|
input [47:0] isn;
|
casez(isn[`INSTRUCTION_OP])
|
casez(isn[`INSTRUCTION_OP])
|
`ADDI: HasConst = TRUE;
|
`ADDI: HasConst = TRUE;
|
`SLTI: HasConst = TRUE;
|
`SLTI: HasConst = TRUE;
|
`SLTUI: HasConst = TRUE;
|
`SLTUI: HasConst = TRUE;
|
`SGTI: HasConst = TRUE;
|
`SGTI: HasConst = TRUE;
|
`SGTUI: HasConst = TRUE;
|
`SGTUI: HasConst = TRUE;
|
`ANDI: HasConst = TRUE;
|
`ANDI: HasConst = TRUE;
|
`ORI: HasConst = TRUE;
|
`ORI: HasConst = TRUE;
|
`XORI: HasConst = TRUE;
|
`XORI: HasConst = TRUE;
|
`XNORI: HasConst = TRUE;
|
`XNORI: HasConst = TRUE;
|
`MULUI: HasConst = TRUE;
|
`MULUI: HasConst = TRUE;
|
`MULI: HasConst = TRUE;
|
`MULI: HasConst = TRUE;
|
`DIVUI: HasConst = TRUE;
|
`DIVUI: HasConst = TRUE;
|
`DIVI: HasConst = TRUE;
|
`DIVI: HasConst = TRUE;
|
`MODI: HasConst = TRUE;
|
`MODI: HasConst = TRUE;
|
`LB: HasConst = TRUE;
|
`LB: HasConst = TRUE;
|
`LBU: HasConst = TRUE;
|
`LBU: HasConst = TRUE;
|
`Lx: HasConst = TRUE;
|
`Lx: HasConst = TRUE;
|
`LWR: HasConst = TRUE;
|
`LWR: HasConst = TRUE;
|
`LV: HasConst = TRUE;
|
`LV: HasConst = TRUE;
|
`SB: HasConst = TRUE;
|
`SB: HasConst = TRUE;
|
`Sx: HasConst = TRUE;
|
`Sx: HasConst = TRUE;
|
`SWC: HasConst = TRUE;
|
`SWC: HasConst = TRUE;
|
`INC: HasConst = TRUE;
|
`INC: HasConst = TRUE;
|
`SV: HasConst = TRUE;
|
`SV: HasConst = TRUE;
|
`CAS: HasConst = TRUE;
|
`CAS: HasConst = TRUE;
|
`JAL: HasConst = TRUE;
|
`JAL: HasConst = TRUE;
|
`CALL: HasConst = TRUE;
|
`CALL: HasConst = TRUE;
|
`RET: HasConst = TRUE;
|
`RET: HasConst = TRUE;
|
`LVx: HasConst = TRUE;
|
`LVx: HasConst = TRUE;
|
default: HasConst = FALSE;
|
default: HasConst = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
|
function IsOddball;
|
|
input [47:0] instr;
|
|
//if (|iqentry_exc[head])
|
|
// IsOddball = TRUE;
|
|
//else
|
|
case(instr[`INSTRUCTION_OP])
|
|
`BRK: IsOddball = TRUE;
|
|
`IVECTOR:
|
|
case(instr[`INSTRUCTION_S2])
|
|
`VSxx: IsOddball = TRUE;
|
|
default: IsOddball = FALSE;
|
|
endcase
|
|
`RR:
|
|
case(instr[`INSTRUCTION_S2])
|
|
`VMOV: IsOddball = TRUE;
|
|
`SEI,`RTI: IsOddball = TRUE;
|
|
default: IsOddball = FALSE;
|
|
endcase
|
|
`MEMNDX:
|
|
case(instr[`INSTRUCTION_S2])
|
|
`CACHEX: IsOddball = TRUE;
|
|
default: IsOddball = FALSE;
|
|
endcase
|
|
`CSRRW,`REX,`CACHE,`FLOAT: IsOddball = TRUE;
|
|
default: IsOddball = FALSE;
|
|
endcase
|
|
endfunction
|
|
|
function IsRFW;
|
function IsRFW;
|
input [47:0] isn;
|
input [47:0] isn;
|
casez(isn[`INSTRUCTION_OP])
|
casez(isn[`INSTRUCTION_OP])
|
`IVECTOR: IsRFW = TRUE;
|
`IVECTOR: IsRFW = TRUE;
|
`FVECTOR: IsRFW = TRUE;
|
`FVECTOR: IsRFW = TRUE;
|
`R2:
|
`R2:
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`R1: IsRFW = TRUE;
|
`R1: IsRFW = TRUE;
|
`ADD: IsRFW = TRUE;
|
`ADD: IsRFW = TRUE;
|
`SUB: IsRFW = TRUE;
|
`SUB: IsRFW = TRUE;
|
`SLT: IsRFW = TRUE;
|
`SLT: IsRFW = TRUE;
|
`SLTU: IsRFW = TRUE;
|
`SLTU: IsRFW = TRUE;
|
`SLE: IsRFW = TRUE;
|
`SLE: IsRFW = TRUE;
|
`SLEU: IsRFW = TRUE;
|
`SLEU: IsRFW = TRUE;
|
`AND: IsRFW = TRUE;
|
`AND: IsRFW = TRUE;
|
`OR: IsRFW = TRUE;
|
`OR: IsRFW = TRUE;
|
`XOR: IsRFW = TRUE;
|
`XOR: IsRFW = TRUE;
|
`MULU: IsRFW = TRUE;
|
`MULU: IsRFW = TRUE;
|
`MULSU: IsRFW = TRUE;
|
`MULSU: IsRFW = TRUE;
|
`MUL: IsRFW = TRUE;
|
`MUL: IsRFW = TRUE;
|
`DIVMODU: IsRFW = TRUE;
|
`MULUH: IsRFW = TRUE;
|
`DIVMODSU: IsRFW = TRUE;
|
`MULSUH: IsRFW = TRUE;
|
`DIVMOD:IsRFW = TRUE;
|
`MULH: IsRFW = TRUE;
|
|
`DIVU: IsRFW = TRUE;
|
|
`DIVSU: IsRFW = TRUE;
|
|
`DIV:IsRFW = TRUE;
|
|
`MODU: IsRFW = TRUE;
|
|
`MODSU: IsRFW = TRUE;
|
|
`MOD:IsRFW = TRUE;
|
`MOV: IsRFW = TRUE;
|
`MOV: IsRFW = TRUE;
|
`VMOV: IsRFW = TRUE;
|
`VMOV: IsRFW = TRUE;
|
`SHIFTR,`SHIFT31,`SHIFT63:
|
`SHIFTR,`SHIFT31,`SHIFT63:
|
IsRFW = TRUE;
|
IsRFW = TRUE;
|
`MIN,`MAX: IsRFW = TRUE;
|
`MIN,`MAX: IsRFW = TRUE;
|
`SEI: IsRFW = TRUE;
|
`SEI: IsRFW = TRUE;
|
default: IsRFW = FALSE;
|
default: IsRFW = FALSE;
|
endcase
|
endcase
|
else
|
else
|
IsRFW = FALSE;
|
IsRFW = FALSE;
|
`MEMNDX:
|
`MEMNDX:
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`LBX: IsRFW = TRUE;
|
`LBX: IsRFW = TRUE;
|
`LBUX: IsRFW = TRUE;
|
`LBUX: IsRFW = TRUE;
|
`LCX: IsRFW = TRUE;
|
`LCX: IsRFW = TRUE;
|
`LCUX: IsRFW = TRUE;
|
`LCUX: IsRFW = TRUE;
|
`LHX: IsRFW = TRUE;
|
`LHX: IsRFW = TRUE;
|
`LHUX: IsRFW = TRUE;
|
`LHUX: IsRFW = TRUE;
|
`LWX: IsRFW = TRUE;
|
`LWX: IsRFW = TRUE;
|
|
`LVBX: IsRFW = TRUE;
|
|
`LVBUX: IsRFW = TRUE;
|
|
`LVCX: IsRFW = TRUE;
|
|
`LVCUX: IsRFW = TRUE;
|
|
`LVHX: IsRFW = TRUE;
|
|
`LVHUX: IsRFW = TRUE;
|
|
`LVWX: IsRFW = TRUE;
|
|
`LWX: IsRFW = TRUE;
|
`LWRX: IsRFW = TRUE;
|
`LWRX: IsRFW = TRUE;
|
`LVX: IsRFW = TRUE;
|
`LVX: IsRFW = TRUE;
|
`LVx: IsRFW = TRUE;
|
|
`CASX: IsRFW = TRUE;
|
`CASX: IsRFW = TRUE;
|
default: IsRFW = FALSE;
|
default: IsRFW = FALSE;
|
endcase
|
endcase
|
else
|
else
|
IsRFW = FALSE;
|
IsRFW = FALSE;
|
`BBc:
|
`BBc:
|
case(isn[20:19])
|
case(isn[20:19])
|
`IBNE: IsRFW = TRUE;
|
`IBNE: IsRFW = TRUE;
|
`DBNZ: IsRFW = TRUE;
|
`DBNZ: IsRFW = TRUE;
|
default: IsRFW = FALSE;
|
default: IsRFW = FALSE;
|
endcase
|
endcase
|
`BITFIELD: IsRFW = TRUE;
|
`BITFIELD: IsRFW = TRUE;
|
`ADDI: IsRFW = TRUE;
|
`ADDI: IsRFW = TRUE;
|
`SLTI: IsRFW = TRUE;
|
`SLTI: IsRFW = TRUE;
|
`SLTUI: IsRFW = TRUE;
|
`SLTUI: IsRFW = TRUE;
|
`SGTI: IsRFW = TRUE;
|
`SGTI: IsRFW = TRUE;
|
`SGTUI: IsRFW = TRUE;
|
`SGTUI: IsRFW = TRUE;
|
`ANDI: IsRFW = TRUE;
|
`ANDI: IsRFW = TRUE;
|
`ORI: IsRFW = TRUE;
|
`ORI: IsRFW = TRUE;
|
`XORI: IsRFW = TRUE;
|
`XORI: IsRFW = TRUE;
|
`MULUI: IsRFW = TRUE;
|
`MULUI: IsRFW = TRUE;
|
`MULI: IsRFW = TRUE;
|
`MULI: IsRFW = TRUE;
|
`DIVUI: IsRFW = TRUE;
|
`DIVUI: IsRFW = TRUE;
|
`DIVI: IsRFW = TRUE;
|
`DIVI: IsRFW = TRUE;
|
`MODI: IsRFW = TRUE;
|
`MODI: IsRFW = TRUE;
|
`JAL: IsRFW = TRUE;
|
`JAL: IsRFW = TRUE;
|
`CALL: IsRFW = TRUE;
|
`CALL: IsRFW = TRUE;
|
`RET: IsRFW = TRUE;
|
`RET: IsRFW = TRUE;
|
`LB: IsRFW = TRUE;
|
`LB: IsRFW = TRUE;
|
`LBU: IsRFW = TRUE;
|
`LBU: IsRFW = TRUE;
|
`Lx: IsRFW = TRUE;
|
`Lx: IsRFW = TRUE;
|
`LWR: IsRFW = TRUE;
|
`LWR: IsRFW = TRUE;
|
`LV: IsRFW = TRUE;
|
`LV: IsRFW = TRUE;
|
`LVx: IsRFW = TRUE;
|
`LVx: IsRFW = TRUE;
|
`CAS: IsRFW = TRUE;
|
`CAS: IsRFW = TRUE;
|
`AMO: IsRFW = TRUE;
|
`AMO: IsRFW = TRUE;
|
`CSRRW: IsRFW = TRUE;
|
`CSRRW: IsRFW = TRUE;
|
default: IsRFW = FALSE;
|
default: IsRFW = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
// Determines which lanes of the target register get updated.
|
// Determines which lanes of the target register get updated.
|
function [7:0] fnWe;
|
function [7:0] fnWe;
|
input [47:0] isn;
|
input [47:0] isn;
|
casez(isn[`INSTRUCTION_OP])
|
casez(isn[`INSTRUCTION_OP])
|
`R2:
|
`R2:
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`R1:
|
`R1:
|
case(isn[22:18])
|
case(isn[22:18])
|
`ABS,`CNTLZ,`CNTLO,`CNTPOP:
|
`ABS,`CNTLZ,`CNTLO,`CNTPOP:
|
case(isn[25:23])
|
case(isn[25:23])
|
3'b000: fnWe = 8'h01;
|
3'b000: fnWe = 8'h01;
|
3'b001: fnWe = 8'h03;
|
3'b001: fnWe = 8'h03;
|
3'b010: fnWe = 8'h0F;
|
3'b010: fnWe = 8'h0F;
|
3'b011: fnWe = 8'hFF;
|
3'b011: fnWe = 8'hFF;
|
default: fnWe = 8'hFF;
|
default: fnWe = 8'hFF;
|
endcase
|
endcase
|
default: fnWe = 8'hFF;
|
default: fnWe = 8'hFF;
|
endcase
|
endcase
|
`SHIFT31: fnWe = (~isn[25] & isn[21]) ? 8'hFF : 8'hFF;
|
`SHIFT31: fnWe = (~isn[25] & isn[21]) ? 8'hFF : 8'hFF;
|
`SHIFT63: fnWe = (~isn[25] & isn[21]) ? 8'hFF : 8'hFF;
|
`SHIFT63: fnWe = (~isn[25] & isn[21]) ? 8'hFF : 8'hFF;
|
`SLT,`SLTU,`SLE,`SLEU,
|
`SLT,`SLTU,`SLE,`SLEU,
|
`ADD,`SUB,
|
`ADD,`SUB,
|
`AND,`OR,`XOR,
|
`AND,`OR,`XOR,
|
`NAND,`NOR,`XNOR,
|
`NAND,`NOR,`XNOR,
|
`DIVMOD,`DIVMODU,`DIVMODSU,
|
`DIV,`DIVU,`DIVSU,
|
`MUL,`MULU,`MULSU:
|
`MOD,`MODU,`MODSU,
|
|
`MUL,`MULU,`MULSU,
|
|
`MULH,`MULUH,`MULSUH:
|
case(isn[25:23])
|
case(isn[25:23])
|
3'b000: fnWe = 8'h01;
|
3'b000: fnWe = 8'h01;
|
3'b001: fnWe = 8'h03;
|
3'b001: fnWe = 8'h03;
|
3'b010: fnWe = 8'h0F;
|
3'b010: fnWe = 8'h0F;
|
3'b011: fnWe = 8'hFF;
|
3'b011: fnWe = 8'hFF;
|
default: fnWe = 8'hFF;
|
default: fnWe = 8'hFF;
|
endcase
|
endcase
|
default: fnWe = 8'hFF;
|
default: fnWe = 8'hFF;
|
endcase
|
endcase
|
default: fnWe = 8'hFF;
|
default: fnWe = 8'hFF;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
// Detect if a source is automatically valid
|
// Detect if a source is automatically valid
|
function Source1Valid;
|
function Source1Valid;
|
input [47:0] isn;
|
input [47:0] isn;
|
casez(isn[`INSTRUCTION_OP])
|
casez(isn[`INSTRUCTION_OP])
|
`BRK: Source1Valid = TRUE;
|
`BRK: Source1Valid = TRUE;
|
`Bcc: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`Bcc: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`BBc: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`BBc: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`BEQI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`BEQI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`CHK: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`CHK: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`R2: case(isn[`INSTRUCTION_S2])
|
`R2: case(isn[`INSTRUCTION_S2])
|
`SHIFT31: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SHIFT31: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SHIFT63: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SHIFT63: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SHIFTR: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SHIFTR: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
default: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
default: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
endcase
|
endcase
|
`MEMNDX: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`MEMNDX: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`ADDI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`ADDI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SLTI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SLTI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SLTUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SLTUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SGTI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SGTI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SGTUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SGTUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`ANDI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`ANDI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`ORI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`ORI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`XORI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`XORI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`XNORI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`XNORI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`MULUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`MULUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`AMO: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`AMO: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`LB: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`LB: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`LBU: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`LBU: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`Lx: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`Lx: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`LxU: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`LxU: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`LWR: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`LWR: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`LV: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`LV: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`LVx: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`LVx: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SB: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SB: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`Sx: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`Sx: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SWC: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SWC: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SV: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`SV: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`INC: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`INC: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`CAS: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`CAS: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`JAL: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`JAL: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`RET: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`RET: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`CSRRW: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`CSRRW: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`BITFIELD: case(isn[31:28])
|
`BITFIELD: case(isn[31:28])
|
`BFINSI: Source1Valid = TRUE;
|
`BFINSI: Source1Valid = TRUE;
|
default: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
default: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
endcase
|
endcase
|
`IVECTOR:
|
`IVECTOR:
|
Source1Valid = FALSE;
|
Source1Valid = FALSE;
|
default: Source1Valid = TRUE;
|
default: Source1Valid = TRUE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function Source2Valid;
|
function Source2Valid;
|
input [47:0] isn;
|
input [47:0] isn;
|
casez(isn[`INSTRUCTION_OP])
|
casez(isn[`INSTRUCTION_OP])
|
`BRK: Source2Valid = TRUE;
|
`BRK: Source2Valid = TRUE;
|
`Bcc: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`Bcc: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`BBc: Source2Valid = TRUE;
|
`BBc: Source2Valid = TRUE;
|
`BEQI: Source2Valid = TRUE;
|
`BEQI: Source2Valid = TRUE;
|
`CHK: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`CHK: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`R2: case(isn[`INSTRUCTION_S2])
|
`R2: case(isn[`INSTRUCTION_S2])
|
`R1: Source2Valid = TRUE;
|
`R1: Source2Valid = TRUE;
|
`SHIFTR: Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
|
`SHIFTR: Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
|
`SHIFT31: Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
|
`SHIFT31: Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
|
`SHIFT63: Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
|
`SHIFT63: Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
|
default: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
default: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
endcase
|
endcase
|
`MEMNDX: case(isn[`INSTRUCTION_S2])
|
`MEMNDX: case(isn[`INSTRUCTION_S2])
|
`LVX,`SVX: Source2Valid = FALSE;
|
`LVX,`SVX: Source2Valid = FALSE;
|
default: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
default: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
endcase
|
endcase
|
`ADDI: Source2Valid = TRUE;
|
`ADDI: Source2Valid = TRUE;
|
`SLTI: Source2Valid = TRUE;
|
`SLTI: Source2Valid = TRUE;
|
`SLTUI: Source2Valid = TRUE;
|
`SLTUI: Source2Valid = TRUE;
|
`SGTI: Source2Valid = TRUE;
|
`SGTI: Source2Valid = TRUE;
|
`SGTUI: Source2Valid = TRUE;
|
`SGTUI: Source2Valid = TRUE;
|
`ANDI: Source2Valid = TRUE;
|
`ANDI: Source2Valid = TRUE;
|
`ORI: Source2Valid = TRUE;
|
`ORI: Source2Valid = TRUE;
|
`XORI: Source2Valid = TRUE;
|
`XORI: Source2Valid = TRUE;
|
`XNORI: Source2Valid = TRUE;
|
`XNORI: Source2Valid = TRUE;
|
`MULUI: Source2Valid = TRUE;
|
`MULUI: Source2Valid = TRUE;
|
`LB: Source2Valid = TRUE;
|
`LB: Source2Valid = TRUE;
|
`LBU: Source2Valid = TRUE;
|
`LBU: Source2Valid = TRUE;
|
`Lx: Source2Valid = TRUE;
|
`Lx: Source2Valid = TRUE;
|
`LxU: Source2Valid = TRUE;
|
`LxU: Source2Valid = TRUE;
|
`LWR: Source2Valid = TRUE;
|
`LWR: Source2Valid = TRUE;
|
`LVx: Source2Valid = TRUE;
|
`LVx: Source2Valid = TRUE;
|
`INC: Source2Valid = TRUE;
|
`INC: Source2Valid = TRUE;
|
`SB: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`SB: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`Sx: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`Sx: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`SWC: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`SWC: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`CAS: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`CAS: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`JAL: Source2Valid = TRUE;
|
`JAL: Source2Valid = TRUE;
|
`RET: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`RET: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`IVECTOR:
|
`IVECTOR:
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`VABS: Source2Valid = TRUE;
|
`VABS: Source2Valid = TRUE;
|
`VMAND,`VMOR,`VMXOR,`VMXNOR,`VMPOP:
|
`VMAND,`VMOR,`VMXOR,`VMXNOR,`VMPOP:
|
Source2Valid = FALSE;
|
Source2Valid = FALSE;
|
`VADDS,`VSUBS,`VANDS,`VORS,`VXORS:
|
`VADDS,`VSUBS,`VANDS,`VORS,`VXORS:
|
Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`VBITS2V: Source2Valid = TRUE;
|
`VBITS2V: Source2Valid = TRUE;
|
`V2BITS: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`V2BITS: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
`VSHL,`VSHR,`VASR: Source2Valid = isn[22:21]==2'd2;
|
`VSHL,`VSHR,`VASR: Source2Valid = isn[22:21]==2'd2;
|
default: Source2Valid = FALSE;
|
default: Source2Valid = FALSE;
|
endcase
|
endcase
|
`LV: Source2Valid = TRUE;
|
`LV: Source2Valid = TRUE;
|
`SV: Source2Valid = FALSE;
|
`SV: Source2Valid = FALSE;
|
`AMO: Source2Valid = isn[31] || isn[`INSTRUCTION_RB]==5'd0;
|
`AMO: Source2Valid = isn[31] || isn[`INSTRUCTION_RB]==5'd0;
|
default: Source2Valid = TRUE;
|
default: Source2Valid = TRUE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function Source3Valid;
|
function Source3Valid;
|
input [47:0] isn;
|
input [47:0] isn;
|
case(isn[`INSTRUCTION_OP])
|
case(isn[`INSTRUCTION_OP])
|
`IVECTOR:
|
`IVECTOR:
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`VEX: Source3Valid = TRUE;
|
`VEX: Source3Valid = TRUE;
|
default: Source3Valid = TRUE;
|
default: Source3Valid = TRUE;
|
endcase
|
endcase
|
`CHK: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`CHK: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`R2:
|
`R2:
|
if (isn[`INSTRUCTION_L2]==2'b01)
|
if (isn[`INSTRUCTION_L2]==2'b01)
|
case(isn[47:42])
|
case(isn[47:42])
|
`CMOVEZ,`CMOVNZ: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`CMOVEZ,`CMOVNZ: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
default: Source3Valid = TRUE;
|
default: Source3Valid = TRUE;
|
endcase
|
endcase
|
else
|
else
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`MAJ: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`MAJ: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
default: Source3Valid = TRUE;
|
default: Source3Valid = TRUE;
|
endcase
|
endcase
|
`MEMNDX:
|
`MEMNDX:
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`SBX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`SBX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`SCX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`SCX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`SHX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`SHX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`SWX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`SWX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`SWCX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`SWCX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`CASX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`CASX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
default: Source3Valid = TRUE;
|
default: Source3Valid = TRUE;
|
endcase
|
endcase
|
default: Source3Valid = TRUE;
|
default: Source3Valid = TRUE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
bus <= 128'h0;
|
bus <= 128'h0;
|
bus[`IB_CONST] <= instr[7:6]==2'b01 ? {{34{instr[47]}},instr[47:18]} :
|
bus[`IB_CONST] <= instr[7:6]==2'b01 ? {{34{instr[47]}},instr[47:18]} :
|
{{50{instr[31]}},instr[31:18]};
|
{{50{instr[31]}},instr[31:18]};
|
case(instr[7:6])
|
case(instr[7:6])
|
2'b00: bus[`IB_LN] <= 3'd4;
|
2'b00: bus[`IB_LN] <= 3'd4;
|
2'b01: bus[`IB_LN] <= 3'd6;
|
2'b01: bus[`IB_LN] <= 3'd6;
|
default: bus[`IB_LN] <= 3'd2;
|
default: bus[`IB_LN] <= 3'd2;
|
endcase
|
endcase
|
// bus[`IB_RT] <= fnRt(instr,ven,vl,thrd) | {thrd,7'b0};
|
// bus[`IB_RT] <= fnRt(instr,ven,vl,thrd) | {thrd,7'b0};
|
// bus[`IB_RC] <= fnRc(instr,ven,thrd) | {thrd,7'b0};
|
// bus[`IB_RC] <= fnRc(instr,ven,thrd) | {thrd,7'b0};
|
// bus[`IB_RA] <= fnRa(instr,ven,vl,thrd) | {thrd,7'b0};
|
// bus[`IB_RA] <= fnRa(instr,ven,vl,thrd) | {thrd,7'b0};
|
bus[`IB_IMM] <= HasConst(instr);
|
bus[`IB_IMM] <= HasConst(instr);
|
bus[`IB_A3V] <= Source3Valid(instr);
|
// bus[`IB_A3V] <= Source3Valid(instr);
|
bus[`IB_A2V] <= Source2Valid(instr);
|
// bus[`IB_A2V] <= Source2Valid(instr);
|
bus[`IB_A1V] <= Source1Valid(instr);
|
// bus[`IB_A1V] <= Source1Valid(instr);
|
bus[`IB_BT] <= (IsBranch(instr) && predict_taken);
|
bus[`IB_BT] <= (IsBranch(instr) && predict_taken);
|
bus[`IB_ALU] <= IsALU;
|
bus[`IB_ALU] <= IsALU;
|
bus[`IB_ALU0] <= IsAlu0Only(instr);
|
bus[`IB_ALU0] <= IsAlu0Only(instr);
|
bus[`IB_FPU] <= IsFPU(instr);
|
bus[`IB_FPU] <= IsFPU(instr);
|
bus[`IB_FC] <= IsFlowCtrl;
|
bus[`IB_FC] <= IsFlowCtrl;
|
bus[`IB_CANEX] <= fnCanException(instr);
|
bus[`IB_CANEX] <= fnCanException(instr);
|
|
bus[`IB_LOADV] <= IsVolatileLoad(instr);
|
bus[`IB_LOAD] <= IsLoad(instr);
|
bus[`IB_LOAD] <= IsLoad(instr);
|
bus[`IB_PRELOAD] <= IsLoad(instr) && Rt==5'd0;
|
bus[`IB_PRELOAD] <= IsLoad(instr) && Rt==5'd0;
|
|
bus[`IB_STORE] <= IsStore(instr);
|
|
bus[`IB_ODDBALL] <= IsOddball(instr);
|
|
bus[`IB_MEMSZ] <= MemSize(instr);
|
bus[`IB_MEM] <= IsMem(instr);
|
bus[`IB_MEM] <= IsMem(instr);
|
bus[`IB_MEMNDX] <= IsMemNdx(instr);
|
bus[`IB_MEMNDX] <= IsMemNdx(instr);
|
bus[`IB_RMW] <= IsCAS(instr) || IsAMO(instr) || IsInc(instr);
|
bus[`IB_RMW] <= IsCAS(instr) || IsAMO(instr) || IsInc(instr);
|
bus[`IB_MEMDB] <= IsMemdb(instr);
|
bus[`IB_MEMDB] <= IsMemdb(instr);
|
bus[`IB_MEMSB] <= IsMemsb(instr);
|
bus[`IB_MEMSB] <= IsMemsb(instr);
|
bus[`IB_SHFT48] <= IsShift48(instr);
|
bus[`IB_SHFT48] <= IsShift48(instr);
|
bus[`IB_SEI] <= IsSEI(instr);
|
bus[`IB_SEI] <= IsSEI(instr);
|
bus[`IB_AQ] <= (IsAMO(instr)|IsLWRX(instr)|IsSWCX(instr)) & instr[25];
|
bus[`IB_AQ] <= (IsAMO(instr)|IsLWRX(instr)|IsSWCX(instr)) & instr[25];
|
bus[`IB_RL] <= (IsAMO(instr)|IsLWRX(instr)|IsSWCX(instr)) & instr[24];
|
bus[`IB_RL] <= (IsAMO(instr)|IsLWRX(instr)|IsSWCX(instr)) & instr[24];
|
bus[`IB_JMP] <= IsJmp(instr);
|
bus[`IB_JMP] <= IsJmp(instr);
|
bus[`IB_BR] <= IsBranch(instr);
|
bus[`IB_BR] <= IsBranch(instr);
|
bus[`IB_SYNC] <= IsSync(instr)||IsBrk(instr)||IsRti(instr);
|
bus[`IB_SYNC] <= IsSync(instr)||IsBrk(instr)||IsRti(instr);
|
bus[`IB_FSYNC] <= IsFSync(instr);
|
bus[`IB_FSYNC] <= IsFSync(instr);
|
bus[`IB_RFW] <= Rt==5'd0 ? 1'b0 : IsRFW(instr);
|
bus[`IB_RFW] <= Rt==5'd0 ? 1'b0 : IsRFW(instr);
|
bus[`IB_WE] <= fnWe(instr);
|
bus[`IB_WE] <= fnWe(instr);
|
id_o <= id_i;
|
id_o <= id_i;
|
idv_o <= idv_i;
|
idv_o <= idv_i;
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
module mIsALU(instr, IsALU);
|
module mIsALU(instr, IsALU);
|
input [47:0] instr;
|
input [47:0] instr;
|
output reg IsALU;
|
output reg IsALU;
|
parameter TRUE = 1'b1;
|
parameter TRUE = 1'b1;
|
parameter FALSE = 1'b0;
|
parameter FALSE = 1'b0;
|
|
|
always @*
|
always @*
|
casez(instr[`INSTRUCTION_OP])
|
casez(instr[`INSTRUCTION_OP])
|
`R2: if (instr[`INSTRUCTION_L2]==2'b00)
|
`R2:
|
|
if (instr[`INSTRUCTION_L2]==2'b00)
|
case(instr[`INSTRUCTION_S2])
|
case(instr[`INSTRUCTION_S2])
|
`VMOV: IsALU = TRUE;
|
`VMOV: IsALU = TRUE;
|
`RTI: IsALU = FALSE;
|
`RTI: IsALU = FALSE;
|
default: IsALU = TRUE;
|
default: IsALU = TRUE;
|
endcase
|
endcase
|
else
|
else
|
IsALU = TRUE;
|
IsALU = TRUE;
|
`BRK: IsALU = FALSE;
|
`BRK: IsALU = FALSE;
|
`Bcc: IsALU = FALSE;
|
`Bcc: IsALU = FALSE;
|
`BBc: IsALU = FALSE;
|
`BBc: IsALU = FALSE;
|
`BEQI: IsALU = FALSE;
|
`BEQI: IsALU = FALSE;
|
`CHK: IsALU = FALSE;
|
`CHK: IsALU = FALSE;
|
`JAL: IsALU = FALSE;
|
`JAL: IsALU = FALSE;
|
`JMP: IsALU = FALSE;
|
`JMP: IsALU = FALSE;
|
`CALL: IsALU = FALSE;
|
`CALL: IsALU = FALSE;
|
`RET: IsALU = FALSE;
|
`RET: IsALU = FALSE;
|
`FVECTOR:
|
`FVECTOR:
|
case(instr[`INSTRUCTION_S2])
|
case(instr[`INSTRUCTION_S2])
|
`VSHL,`VSHR,`VASR: IsALU = TRUE;
|
`VSHL,`VSHR,`VASR: IsALU = TRUE;
|
default: IsALU = FALSE; // Integer
|
default: IsALU = FALSE; // Integer
|
endcase
|
endcase
|
`IVECTOR:
|
`IVECTOR:
|
case(instr[`INSTRUCTION_S2])
|
case(instr[`INSTRUCTION_S2])
|
`VSHL,`VSHR,`VASR: IsALU = TRUE;
|
`VSHL,`VSHR,`VASR: IsALU = TRUE;
|
default: IsALU = TRUE; // Integer
|
default: IsALU = TRUE; // Integer
|
endcase
|
endcase
|
`FLOAT: IsALU = FALSE;
|
`FLOAT: IsALU = FALSE;
|
default: IsALU = TRUE;
|
default: IsALU = TRUE;
|
endcase
|
endcase
|
|
|
endmodule
|
endmodule
|
|
|
