| Line 32... |
Line 32... |
input [7:0] vl;
|
input [7:0] vl;
|
input [5:0] ven;
|
input [5:0] ven;
|
input thrd;
|
input thrd;
|
input predict_taken;
|
input predict_taken;
|
input [4:0] Rt;
|
input [4:0] Rt;
|
output reg [127:0] bus;
|
output reg [143:0] bus;
|
output reg [4:0] id_o;
|
output reg [4:0] id_o;
|
output reg idv_o;
|
output reg idv_o;
|
|
|
parameter TRUE = 1'b1;
|
parameter TRUE = 1'b1;
|
parameter FALSE = 1'b0;
|
parameter FALSE = 1'b0;
|
| Line 109... |
Line 109... |
`R2:
|
`R2:
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`R1: IsAlu0Only = TRUE;
|
`R1: IsAlu0Only = TRUE;
|
`SHIFTR,`SHIFT31,`SHIFT63:
|
`SHIFTR,`SHIFT31,`SHIFT63:
|
IsAlu0Only = TRUE;
|
IsAlu0Only = !(instr[25:23]==`SHL || instr[25:23]==`ASL);
|
`MULU,`MULSU,`MUL,
|
`MULU,`MULSU,`MUL,
|
`MULUH,`MULSUH,`MULH,
|
`MULUH,`MULSUH,`MULH,
|
`MODU,`MODSU,`MOD: IsAlu0Only = TRUE;
|
`MODU,`MODSU,`MOD: IsAlu0Only = TRUE;
|
`DIVU,`DIVSU,`DIV: IsAlu0Only = TRUE;
|
`DIVU,`DIVSU,`DIV: IsAlu0Only = TRUE;
|
`MIN,`MAX: IsAlu0Only = TRUE;
|
`MIN,`MAX: IsAlu0Only = TRUE;
|
| Line 527... |
Line 527... |
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function IsJmp;
|
function IsJmp;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsJmp = isn[`INSTRUCTION_OP]==`JMP && isn[7]==1'b0;
|
IsJmp = isn[`INSTRUCTION_OP]==`JMP;// && isn[7]==1'b0;
|
endfunction
|
endfunction
|
|
|
// Really IsPredictableBranch
|
// Really IsPredictableBranch
|
// Does not include BccR's
|
// Does not include BccR's
|
function IsBranch;
|
function IsBranch;
|
| Line 543... |
Line 543... |
`CHK: IsBranch = TRUE;
|
`CHK: IsBranch = TRUE;
|
default: IsBranch = FALSE;
|
default: IsBranch = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
|
function IsJAL;
|
|
input [47:0] isn;
|
|
IsJAL = isn[`INSTRUCTION_OP]==`JAL;// && isn[7]==1'b0;
|
|
endfunction
|
|
|
|
function IsRet;
|
|
input [47:0] isn;
|
|
IsRet = isn[`INSTRUCTION_OP]==`RET;// && isn[7]==1'b0;
|
|
endfunction
|
|
|
|
function IsIrq;
|
|
input [47:0] isn;
|
|
IsIrq = isn[`INSTRUCTION_OP]==`BRK /*&& isn[`INSTRUCTION_L2]==2'b00*/ && isn[23:20]==4'h0;
|
|
endfunction
|
|
|
function IsBrk;
|
function IsBrk;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsBrk = isn[`INSTRUCTION_OP]==`BRK && isn[`INSTRUCTION_L2]==2'b00;
|
IsBrk = isn[`INSTRUCTION_OP]==`BRK;// && isn[`INSTRUCTION_L2]==2'b00;
|
endfunction
|
endfunction
|
|
|
function IsRti;
|
function IsRti;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsRti = isn[`INSTRUCTION_OP]==`RR && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`RTI;
|
IsRti = isn[`INSTRUCTION_OP]==`RR /*&& isn[`INSTRUCTION_L2]==2'b00*/ && isn[`INSTRUCTION_S2]==`RTI;
|
endfunction
|
endfunction
|
|
|
// Has an extendable 14-bit constant
|
// Has an extendable 14-bit constant
|
function HasConst;
|
function HasConst;
|
input [47:0] isn;
|
input [47:0] isn;
|
| Line 911... |
Line 926... |
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
bus <= 128'h0;
|
bus <= 144'h0;
|
bus[`IB_CONST] <= instr[7:6]==2'b01 ? {{34{instr[47]}},instr[47:18]} :
|
bus[`IB_CONST] <= instr[6]==1'b1 ? {{34{instr[47]}},instr[47:18]} :
|
{{50{instr[31]}},instr[31:18]};
|
{{50{instr[31]}},instr[31:18]};
|
case(instr[7:6])
|
case(instr[7:6])
|
2'b00: bus[`IB_LN] <= 3'd4;
|
2'b00: bus[`IB_LN] <= 3'd4;
|
2'b01: bus[`IB_LN] <= 3'd6;
|
2'b01: bus[`IB_LN] <= 3'd6;
|
default: bus[`IB_LN] <= 3'd2;
|
default: bus[`IB_LN] <= 3'd2;
|
| Line 926... |
Line 941... |
// bus[`IB_RA] <= fnRa(instr,ven,vl,thrd) | {thrd,7'b0};
|
// bus[`IB_RA] <= fnRa(instr,ven,vl,thrd) | {thrd,7'b0};
|
bus[`IB_IMM] <= HasConst(instr);
|
bus[`IB_IMM] <= HasConst(instr);
|
// bus[`IB_A3V] <= Source3Valid(instr);
|
// bus[`IB_A3V] <= Source3Valid(instr);
|
// bus[`IB_A2V] <= Source2Valid(instr);
|
// bus[`IB_A2V] <= Source2Valid(instr);
|
// bus[`IB_A1V] <= Source1Valid(instr);
|
// bus[`IB_A1V] <= Source1Valid(instr);
|
|
bus[`IB_IRQ] <= IsIrq(instr);
|
|
bus[`IB_BRK] <= IsBrk(instr);
|
|
bus[`IB_RTI] <= IsRti(instr);
|
|
bus[`IB_RET] <= IsRet(instr);
|
|
bus[`IB_JAL] <= IsJAL(instr);
|
bus[`IB_BT] <= (IsBranch(instr) && predict_taken);
|
bus[`IB_BT] <= (IsBranch(instr) && predict_taken);
|
bus[`IB_ALU] <= IsALU;
|
bus[`IB_ALU] <= IsALU;
|
bus[`IB_ALU0] <= IsAlu0Only(instr);
|
bus[`IB_ALU0] <= IsAlu0Only(instr);
|
bus[`IB_FPU] <= IsFPU(instr);
|
bus[`IB_FPU] <= IsFPU(instr);
|
bus[`IB_FC] <= IsFlowCtrl;
|
bus[`IB_FC] <= IsFlowCtrl;
|
