URL https://opencores.org/ocsvn/thor/thor/trunk

Subversion Repositories thor

[/] [thor/] [trunk/] [FT64v5/] [rtl/] [common/] [FT64_idecoder.v] - Diff between revs 53 and 55

Rev 53	Rev 55
Line 735...	Line 735...
`LV: IsRFW = TRUE;	`LV: IsRFW = TRUE;
`LVx: IsRFW = TRUE;	`LVx: IsRFW = TRUE;
`CAS: IsRFW = TRUE;	`CAS: IsRFW = TRUE;
`AMO: IsRFW = TRUE;	`AMO: IsRFW = TRUE;
`CSRRW: IsRFW = TRUE;	`CSRRW: IsRFW = TRUE;
	`LUI: IsRFW = TRUE;
`default: IsRFW = FALSE;`	`default: IsRFW = FALSE;`
`endcase`	`endcase`
`endfunction`	`endfunction`

`// Determines which lanes of the target register get updated.`	`// Determines which lanes of the target register get updated.`
Line 938...	Line 939...
`endif	`endif
`begin`	`begin`
`bus <= 144'h0;`	`bus <= 144'h0;`
bus[`IB_CONST] <= instr[6]==1'b1 ? {{34{instr[47]}},instr[47:18]} :	bus[`IB_CONST] <= instr[6]==1'b1 ? {{34{instr[47]}},instr[47:18]} :
`{{50{instr[31]}},instr[31:18]};`	`{{50{instr[31]}},instr[31:18]};`
	if (instr[`INSTRUCTION_OP]==`CMPRSSD)
	bus[`IB_LN] <= 3'd2;
	`else`
`case(instr[7:6])`	`case(instr[7:6])`
2'b00: bus[`IB_LN] <= 3'd4;	2'b00: bus[`IB_LN] <= 3'd4;
2'b01: bus[`IB_LN] <= 3'd6;	2'b01: bus[`IB_LN] <= 3'd6;
default: bus[`IB_LN] <= 3'd2;	default: bus[`IB_LN] <= 3'd2;
`endcase`	`endcase`