| Line 77... |
Line 77... |
output vol_o, // volatile register selected
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output vol_o, // volatile register selected
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input i1, i2, i3, i4, i5, i6, i7,
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input i1, i2, i3, i4, i5, i6, i7,
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i8, i9, i10, i11, i12, i13, i14, i15,
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i8, i9, i10, i11, i12, i13, i14, i15,
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i16, i17, i18, i19, i20, i21, i22, i23,
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i16, i17, i18, i19, i20, i21, i22, i23,
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i24, i25, i26, i27, i28, i29, i30, i31,
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i24, i25, i26, i27, i28, i29, i30, i31,
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output [2:0] irqo, // normally connected to the processor irq
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output [3:0] irqo, // normally connected to the processor irq
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input nmii, // nmi input connected to nmi requester
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input nmii, // nmi input connected to nmi requester
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output nmio, // normally connected to the nmi of cpu
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output nmio, // normally connected to the nmi of cpu
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output [6:0] causeo
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output [6:0] causeo
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);
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);
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parameter pIOAddress = 32'hFFDC_0F00;
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parameter pIOAddress = 32'hFFDC_0F00;
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| Line 94... |
Line 94... |
reg [31:0] ib;
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reg [31:0] ib;
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reg [31:0] iedge;
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reg [31:0] iedge;
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reg [31:0] rste;
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reg [31:0] rste;
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reg [31:0] es;
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reg [31:0] es;
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reg [5:0] cause_base;
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reg [5:0] cause_base;
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reg [2:0] irq [0:31];
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reg [3:0] irq [0:31];
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reg [6:0] cause [0:31];
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reg [6:0] cause [0:31];
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|
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wire cs = cyc_i && stb_i && adr_i[31:8]==pIOAddress[31:8];
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wire cs = cyc_i && stb_i && adr_i[31:8]==pIOAddress[31:8];
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assign vol_o = cs;
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assign vol_o = cs;
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| Line 126... |
Line 126... |
6'd4: es <= dat_i[31:0];
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6'd4: es <= dat_i[31:0];
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6'd5: rste[dat_i[4:0]] <= 1'b1;
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6'd5: rste[dat_i[4:0]] <= 1'b1;
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6'b1xxxxx:
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6'b1xxxxx:
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begin
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begin
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cause[adr_i[6:2]] <= dat_i[6:0];
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cause[adr_i[6:2]] <= dat_i[6:0];
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irq[adr_i[6:2]] <= dat_i[10:8];
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irq[adr_i[6:2]] <= dat_i[11:8];
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ie[adr_i[6:2]] <= dat_i[16];
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ie[adr_i[6:2]] <= dat_i[16];
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es[adr_i[6:2]] <= dat_i[17];
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es[adr_i[6:2]] <= dat_i[17];
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end
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end
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endcase
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endcase
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end
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end
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| Line 142... |
Line 142... |
if (irqenc!=5'd0)
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if (irqenc!=5'd0)
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$display("PIC: %d",irqenc);
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$display("PIC: %d",irqenc);
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if (cs)
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if (cs)
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casex (adr_i[7:2])
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casex (adr_i[7:2])
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6'd0: dat_o <= {cause_base,3'd0} + irqenc;
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6'd0: dat_o <= {cause_base,3'd0} + irqenc;
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6'b1xxxxx: dat_o <= {es[adr_i[6:2]],ie[adr_i[6:2]],5'b0,irq[adr_i[6:2]],1'b0,cause[adr_i[6:2]]};
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6'b1xxxxx: dat_o <= {es[adr_i[6:2]],ie[adr_i[6:2]],4'b0,irq[adr_i[6:2]],1'b0,cause[adr_i[6:2]]};
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default: dat_o <= ie;
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default: dat_o <= ie;
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endcase
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endcase
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else
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else
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dat_o <= 32'h0000;
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dat_o <= 32'h0000;
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end
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end
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assign irqo = (irqenc == 5'h0) ? 3'd0 : irq[irqenc];
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assign irqo = (irqenc == 5'h0) ? 4'd0 : irq[irqenc];
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assign causeo = (irqenc == 5'h0) ? 7'd0 : cause[irqenc];
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assign causeo = (irqenc == 5'h0) ? 7'd0 : cause[irqenc];
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assign nmio = nmii & ie[0];
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assign nmio = nmii & ie[0];
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// Edge detect circuit
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// Edge detect circuit
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integer n;
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integer n;
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