URL https://opencores.org/ocsvn/thor/thor/trunk

Subversion Repositories thor

[/] [thor/] [trunk/] [FT64v5/] [rtl/] [common/] [FT64_pic.v] - Diff between revs 49 and 51

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 49	Rev 51
Line 96...	Line 96...
`reg [31:0] rste;`	`reg [31:0] rste;`
`reg [31:0] es;`	`reg [31:0] es;`
`reg [5:0] cause_base;`	`reg [5:0] cause_base;`
`reg [3:0] irq [0:31];`	`reg [3:0] irq [0:31];`
`reg [6:0] cause [0:31];`	`reg [6:0] cause [0:31];`
	`integer n;`

	`initial begin`
	`ie <= 32'h0;`
	`es <= 32'hFFFFFFFF;`
	`rste <= 32'h0;`
	`for (n = 0; n < 32; n = n + 1) begin`
	`cause[n] <= 7'h00;`
	`irq[n] <= 4'h8;`
	`end`
	`end`

`wire cs = cyc_i && stb_i && adr_i[31:8]==pIOAddress[31:8];`	`wire cs = cyc_i && stb_i && adr_i[31:8]==pIOAddress[31:8];`
`assign vol_o = cs;`	`assign vol_o = cs;`

`always @(posedge clk_i)`	`always @(posedge clk_i)`
Line 113...	Line 124...
`rste <= 32'h0;`	`rste <= 32'h0;`
`end`	`end`
`else begin`	`else begin`
`rste <= 32'h0;`	`rste <= 32'h0;`
`if (cs & wr_i) begin`	`if (cs & wr_i) begin`
`casex (adr_i[7:2])`	`casez (adr_i[7:2])`
`6'd0: ;`	`6'd0: ;`
`6'd1:`	`6'd1:`
`begin`	`begin`
`ie[31:0] <= dat_i[31:0];`	`ie[31:0] <= dat_i[31:0];`
`end`	`end`
`6'd2,6'd3:`	`6'd2,6'd3:`
`ie[dat_i[4:0]] <= adr_i[2];`	`ie[dat_i[4:0]] <= adr_i[2];`
`6'd4: es <= dat_i[31:0];`	`6'd4: es <= dat_i[31:0];`
`6'd5: rste[dat_i[4:0]] <= 1'b1;`	`6'd5: rste[dat_i[4:0]] <= 1'b1;`
`6'b1xxxxx:`	`6'b1?????:`
`begin`	`begin`
`cause[adr_i[6:2]] <= dat_i[6:0];`	`cause[adr_i[6:2]] <= dat_i[6:0];`
`irq[adr_i[6:2]] <= dat_i[11:8];`	`irq[adr_i[6:2]] <= dat_i[11:8];`
`ie[adr_i[6:2]] <= dat_i[16];`	`ie[adr_i[6:2]] <= dat_i[16];`
`es[adr_i[6:2]] <= dat_i[17];`	`es[adr_i[6:2]] <= dat_i[17];`
Line 140...	Line 151...
`always @(posedge clk_i)`	`always @(posedge clk_i)`
`begin`	`begin`
`if (irqenc!=5'd0)`	`if (irqenc!=5'd0)`
`$display("PIC: %d",irqenc);`	`$display("PIC: %d",irqenc);`
`if (cs)`	`if (cs)`
`casex (adr_i[7:2])`	`casez (adr_i[7:2])`
`6'd0: dat_o <= {cause_base,3'd0} + irqenc;`	`6'd0: dat_o <= {cause_base,3'd0} + irqenc;`
`6'b1xxxxx: dat_o <= {es[adr_i[6:2]],ie[adr_i[6:2]],4'b0,irq[adr_i[6:2]],1'b0,cause[adr_i[6:2]]};`	`6'b1?????: dat_o <= {es[adr_i[6:2]],ie[adr_i[6:2]],4'b0,irq[adr_i[6:2]],1'b0,cause[adr_i[6:2]]};`
`default: dat_o <= ie;`	`default: dat_o <= ie;`
`endcase`	`endcase`
`else`	`else`
`dat_o <= 32'h0000;`	`dat_o <= 32'h0000;`
`end`	`end`
Line 154...	Line 165...
`assign irqo = (irqenc == 5'h0) ? 4'd0 : irq[irqenc];`	`assign irqo = (irqenc == 5'h0) ? 4'd0 : irq[irqenc];`
`assign causeo = (irqenc == 5'h0) ? 7'd0 : cause[irqenc];`	`assign causeo = (irqenc == 5'h0) ? 7'd0 : cause[irqenc];`
`assign nmio = nmii & ie[0];`	`assign nmio = nmii & ie[0];`

`// Edge detect circuit`	`// Edge detect circuit`
`integer n;`
`always @(posedge clk_i)`	`always @(posedge clk_i)`
`begin`	`begin`
`for (n = 1; n < 32; n = n + 1)`	`for (n = 1; n < 32; n = n + 1)`
`begin`	`begin`
`ib[n] <= i[n];`	`ib[n] <= i[n];`

Browse

Tools

Subversion Repositories thor

[/] [thor/] [trunk/] [FT64v5/] [rtl/] [common/] [FT64_pic.v] - Diff between revs 49 and 51