| Line 38... |
Line 38... |
// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// Approx. 100,000 LUTs. 160,000 LC's.
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// Approx. 100,000 LUTs. 160,000 LC's.
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// ============================================================================
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// ============================================================================
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//
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//
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`include "FT64_config.vh"
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`include "FT64_defines.vh"
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`include "FT64_defines.vh"
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//`define SUPPORT_DBG 1'b1
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//`define FULL_ISSUE_LOGIC 1'b1
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`define QBITS 2:0
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`define QENTRIES 8
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`define ID1_AVAIL 1'b1
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`define ID2_AVAIL 1'b1
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`define ALU0_AVAIL 1'b1
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`define ALU1_AVAIL 1'b1
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`define FPU1_AVAIL 1'b1
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`define FPU2_AVAIL 1'b0
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module FT64(hartid, rst, clk_i, clk4x, tm_clk_i, irq_i, vec_i, bte_o, cti_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_o, dat_i,
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module FT64(hartid, rst, clk_i, clk4x, tm_clk_i, irq_i, vec_i, bte_o, cti_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_o, dat_i,
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ol_o, pcr_o, pcr2_o, exv_i, rdv_i, wrv_i, icl_o, sr_o, cr_o, rbi_i, signal_i);
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ol_o, pcr_o, pcr2_o, exv_i, rdv_i, wrv_i, icl_o, sr_o, cr_o, rbi_i, signal_i);
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input [63:0] hartid;
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input [63:0] hartid;
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input rst;
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input rst;
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input clk_i;
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input clk_i;
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input clk4x;
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input clk4x;
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input tm_clk_i;
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input tm_clk_i;
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input [2:0] irq_i;
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input [3:0] irq_i;
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input [7:0] vec_i;
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input [7:0] vec_i;
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output reg [1:0] bte_o;
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output reg [1:0] bte_o;
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output reg [2:0] cti_o;
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output reg [2:0] cti_o;
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output reg cyc_o;
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output reg cyc_o;
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output reg stb_o;
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output reg stb_o;
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input ack_i;
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input ack_i;
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input err_i;
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input err_i;
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output reg we_o;
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output reg we_o;
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output reg [7:0] sel_o;
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output reg [7:0] sel_o;
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output reg [31:0] adr_o;
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output reg [`ABITS] adr_o;
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output reg [63:0] dat_o;
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output reg [63:0] dat_o;
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input [63:0] dat_i;
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input [63:0] dat_i;
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output reg [1:0] ol_o;
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output reg [1:0] ol_o;
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output [31:0] pcr_o;
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output [31:0] pcr_o;
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output [63:0] pcr2_o;
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output [63:0] pcr2_o;
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| Line 177... |
Line 168... |
reg [4:0] rf_source[0:AREGS-1];
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reg [4:0] rf_source[0:AREGS-1];
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initial begin
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initial begin
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for (n = 0; n < AREGS; n = n + 1)
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for (n = 0; n < AREGS; n = n + 1)
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rf_source[n] = 5'd0;
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rf_source[n] = 5'd0;
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end
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end
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wire [31:0] pc0;
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wire [`ABITS] pc0;
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wire [31:0] pc1;
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wire [`ABITS] pc1;
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wire [`ABITS] pc2;
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reg excmiss;
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reg excmiss;
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reg [31:0] excmisspc;
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reg [`ABITS] excmisspc;
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reg excthrd;
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reg excthrd;
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reg exception_set;
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reg exception_set;
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reg rdvq; // accumulated read violation
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reg rdvq; // accumulated read violation
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reg errq; // accumulated err_i input status
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reg errq; // accumulated err_i input status
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reg exvq;
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reg exvq;
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| Line 195... |
Line 187... |
reg [5:0] vqet0, vqet1;
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reg [5:0] vqet0, vqet1;
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reg [7:0] vl; // vector length
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reg [7:0] vl; // vector length
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reg [63:0] vm [0:7]; // vector mask registers
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reg [63:0] vm [0:7]; // vector mask registers
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reg [1:0] m2;
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reg [1:0] m2;
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reg [31:0] wb_merges;
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// CSR's
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// CSR's
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reg [63:0] cr0;
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reg [63:0] cr0;
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wire snr = cr0[17]; // sequence number reset
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wire snr = cr0[17]; // sequence number reset
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wire dce = cr0[30]; // data cache enable
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wire dce = cr0[30]; // data cache enable
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wire bpe = cr0[32]; // branch predictor enable
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wire bpe = cr0[32]; // branch predictor enable
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wire ctgtxe = cr0[33];
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wire ctgtxe = cr0[33];
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reg [63:0] pmr;
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wire id1_available = pmr[0];
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wire id2_available = pmr[1];
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wire id3_available = pmr[2];
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wire alu0_available = pmr[8];
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wire alu1_available = pmr[9];
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wire fpu1_available = pmr[16];
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wire fpu2_available = pmr[17];
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wire mem1_available = pmr[24];
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wire mem2_available = pmr[25];
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wire mem3_available = pmr[26];
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wire fcu_available = pmr[32];
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// Simply setting this flag to zero should strip out almost all the logic
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// Simply setting this flag to zero should strip out almost all the logic
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// associated SMT.
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// associated SMT.
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`ifdef SUPPORT_SMT
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`ifdef SUPPORT_SMT
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wire thread_en = cr0[16];
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wire thread_en = cr0[16];
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`else
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`else
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| Line 219... |
Line 224... |
assign pcr_o = pcr;
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assign pcr_o = pcr;
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assign pcr2_o = pcr2;
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assign pcr2_o = pcr2;
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reg [63:0] aec;
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reg [63:0] aec;
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reg [15:0] cause[0:15];
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reg [15:0] cause[0:15];
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`ifdef SUPPORT_SMT
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`ifdef SUPPORT_SMT
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reg [31:0] epc [0:NTHREAD];
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reg [`ABITS] epc [0:NTHREAD];
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reg [31:0] epc0 [0:NTHREAD];
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reg [`ABITS] epc0 [0:NTHREAD];
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reg [31:0] epc1 [0:NTHREAD];
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reg [`ABITS] epc1 [0:NTHREAD];
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reg [31:0] epc2 [0:NTHREAD];
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reg [`ABITS] epc2 [0:NTHREAD];
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reg [31:0] epc3 [0:NTHREAD];
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reg [`ABITS] epc3 [0:NTHREAD];
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reg [31:0] epc4 [0:NTHREAD];
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reg [`ABITS] epc4 [0:NTHREAD];
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reg [31:0] epc5 [0:NTHREAD];
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reg [`ABITS] epc5 [0:NTHREAD];
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reg [31:0] epc6 [0:NTHREAD];
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reg [`ABITS] epc6 [0:NTHREAD];
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reg [31:0] epc7 [0:NTHREAD];
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reg [`ABITS] epc7 [0:NTHREAD];
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reg [31:0] epc8 [0:NTHREAD]; // exception pc and stack
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reg [`ABITS] epc8 [0:NTHREAD]; // exception pc and stack
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reg [63:0] mstatus [0:NTHREAD]; // machine status
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reg [63:0] mstatus [0:NTHREAD]; // machine status
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wire [2:0] im = mstatus[0][2:0];
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wire [3:0] im = mstatus[0][3:0];
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wire [1:0] ol [0:NTHREAD];
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wire [1:0] ol [0:NTHREAD];
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wire [1:0] dl [0:NTHREAD];
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wire [1:0] dl [0:NTHREAD];
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assign ol[0] = mstatus[0][5:3]; // operating level
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assign ol[0] = mstatus[0][5:3]; // operating level
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assign dl[0] = mstatus[0][21:20];
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assign dl[0] = mstatus[0][21:20];
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wire [7:0] cpl [0:NTHREAD];
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wire [7:0] cpl [0:NTHREAD];
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| Line 253... |
Line 258... |
wire mprv = mstatus[0][55];
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wire mprv = mstatus[0][55];
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wire [5:0] fprgs = mstatus[0][25:20];
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wire [5:0] fprgs = mstatus[0][25:20];
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//assign ol_o = mprv ? ol_stack[0][2:0] : ol[0];
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//assign ol_o = mprv ? ol_stack[0][2:0] : ol[0];
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wire vca = mstatus[0][32]; // vector chaining active
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wire vca = mstatus[0][32]; // vector chaining active
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`else
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`else
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reg [31:0] epc ;
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reg [`ABITS] epc ;
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reg [31:0] epc0 ;
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reg [`ABITS] epc0 ;
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reg [31:0] epc1 ;
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reg [`ABITS] epc1 ;
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reg [31:0] epc2 ;
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reg [`ABITS] epc2 ;
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reg [31:0] epc3 ;
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reg [`ABITS] epc3 ;
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reg [31:0] epc4 ;
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reg [`ABITS] epc4 ;
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reg [31:0] epc5 ;
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reg [`ABITS] epc5 ;
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reg [31:0] epc6 ;
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reg [`ABITS] epc6 ;
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reg [31:0] epc7 ;
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reg [`ABITS] epc7 ;
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reg [31:0] epc8 ; // exception pc and stack
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reg [`ABITS] epc8 ; // exception pc and stack
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reg [63:0] mstatus ; // machine status
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reg [63:0] mstatus ; // machine status
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wire [2:0] im = mstatus[2:0];
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wire [3:0] im = mstatus[3:0];
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wire [1:0] ol ;
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wire [1:0] ol ;
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wire [1:0] dl;
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wire [1:0] dl;
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assign ol = mstatus[5:3]; // operating level
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assign ol = mstatus[5:3]; // operating level
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assign dl = mstatus[21:20];
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assign dl = mstatus[21:20];
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wire [7:0] cpl ;
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wire [7:0] cpl ;
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| Line 284... |
Line 289... |
wire [5:0] fprgs = mstatus[25:20];
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wire [5:0] fprgs = mstatus[25:20];
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//assign ol_o = mprv ? ol_stack[2:0] : ol;
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//assign ol_o = mprv ? ol_stack[2:0] : ol;
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wire vca = mstatus[32]; // vector chaining active
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wire vca = mstatus[32]; // vector chaining active
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`endif
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`endif
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reg [63:0] tcb;
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reg [63:0] tcb;
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reg [31:0] badaddr[0:15];
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reg [`ABITS] badaddr[0:15];
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reg [31:0] tvec[0:7];
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reg [`ABITS] tvec[0:7];
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reg [63:0] sema;
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reg [63:0] sema;
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reg [63:0] vm_sema;
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reg [63:0] vm_sema;
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reg [63:0] cas; // compare and swap
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reg [63:0] cas; // compare and swap
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reg [63:0] ve_hold;
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reg [63:0] ve_hold;
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reg isCAS, isAMO, isInc, isSpt, isRMW;
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reg isCAS, isAMO, isInc, isSpt, isRMW;
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reg [`QBITS] casid;
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reg [`QBITS] casid;
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reg [31:0] sbl, sbu;
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reg [`ABITS] sbl, sbu;
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reg [4:0] regLR = 5'd29;
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reg [4:0] regLR = 5'd29;
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reg [2:0] fp_rm;
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reg [2:0] fp1_rm;
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reg fp_inexe;
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reg fp1_inexe;
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reg fp_dbzxe;
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reg fp1_dbzxe;
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reg fp_underxe;
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reg fp1_underxe;
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reg fp_overxe;
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reg fp1_overxe;
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reg fp_invopxe;
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reg fp1_invopxe;
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reg fp_giopxe;
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reg fp1_giopxe;
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reg fp_nsfp = 1'b0;
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reg fp1_nsfp = 1'b0;
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reg fp_fractie;
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reg fp1_fractie;
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reg fp_raz;
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reg fp1_raz;
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reg fp_neg;
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reg fp1_neg;
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reg fp_pos;
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reg fp1_pos;
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reg fp_zero;
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reg fp1_zero;
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reg fp_inf;
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reg fp1_inf;
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reg fp_inex; // inexact exception
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reg fp1_inex; // inexact exception
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reg fp_dbzx; // divide by zero exception
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reg fp1_dbzx; // divide by zero exception
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reg fp_underx; // underflow exception
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reg fp1_underx; // underflow exception
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reg fp_overx; // overflow exception
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reg fp1_overx; // overflow exception
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reg fp_giopx; // global invalid operation exception
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reg fp1_giopx; // global invalid operation exception
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reg fp_sx; // summary exception
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reg fp1_sx; // summary exception
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reg fp_swtx; // software triggered exception
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reg fp1_swtx; // software triggered exception
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reg fp_gx;
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reg fp1_gx;
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reg fp_invopx;
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reg fp1_invopx;
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reg fp_infzerox;
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reg fp1_infzerox;
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reg fp_zerozerox;
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reg fp1_zerozerox;
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reg fp_subinfx;
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reg fp1_subinfx;
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reg fp_infdivx;
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reg fp1_infdivx;
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reg fp_NaNCmpx;
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reg fp1_NaNCmpx;
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reg fp_cvtx;
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reg fp1_cvtx;
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reg fp_sqrtx;
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reg fp1_sqrtx;
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reg fp_snanx;
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reg fp1_snanx;
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wire [31:0] fp_status = {
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reg [2:0] fp2_rm;
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reg fp2_inexe;
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fp_rm,
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reg fp2_dbzxe;
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fp_inexe,
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reg fp2_underxe;
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fp_dbzxe,
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reg fp2_overxe;
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fp_underxe,
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reg fp2_invopxe;
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fp_overxe,
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reg fp2_giopxe;
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fp_invopxe,
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reg fp2_nsfp = 1'b0;
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fp_nsfp,
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reg fp2_fractie;
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reg fp2_raz;
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reg fp2_neg;
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reg fp2_pos;
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reg fp2_zero;
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reg fp2_inf;
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reg fp2_inex; // inexact exception
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reg fp2_dbzx; // divide by zero exception
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reg fp2_underx; // underflow exception
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reg fp2_overx; // overflow exception
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reg fp2_giopx; // global invalid operation exception
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reg fp2_sx; // summary exception
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reg fp2_swtx; // software triggered exception
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reg fp2_gx;
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reg fp2_invopx;
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reg fp2_infzerox;
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reg fp2_zerozerox;
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reg fp2_subinfx;
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reg fp2_infdivx;
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reg fp2_NaNCmpx;
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reg fp2_cvtx;
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reg fp2_sqrtx;
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reg fp2_snanx;
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wire [31:0] fp1_status = {
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fp1_rm,
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fp1_inexe,
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fp1_dbzxe,
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fp1_underxe,
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fp1_overxe,
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fp1_invopxe,
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fp1_nsfp,
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fp_fractie,
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fp1_fractie,
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fp_raz,
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fp1_raz,
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1'b0,
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1'b0,
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fp_neg,
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fp1_neg,
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fp_pos,
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fp1_pos,
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fp_zero,
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fp1_zero,
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fp_inf,
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fp1_inf,
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fp_swtx,
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fp1_swtx,
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fp_inex,
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fp1_inex,
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fp_dbzx,
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fp1_dbzx,
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fp_underx,
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fp1_underx,
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fp_overx,
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fp1_overx,
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fp_giopx,
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fp1_giopx,
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fp_gx,
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fp1_gx,
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fp_sx,
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fp1_sx,
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fp_cvtx,
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fp1_cvtx,
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fp_sqrtx,
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fp1_sqrtx,
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fp_NaNCmpx,
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fp1_NaNCmpx,
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fp_infzerox,
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fp1_infzerox,
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fp_zerozerox,
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fp1_zerozerox,
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fp_infdivx,
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fp1_infdivx,
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fp_subinfx,
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fp1_subinfx,
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fp_snanx
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fp1_snanx
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};
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};
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reg [63:0] fpu_csr;
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wire [31:0] fp2_status = {
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wire [5:0] fp_rgs = fpu_csr[37:32];
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fp2_rm,
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fp2_inexe,
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fp2_dbzxe,
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fp2_underxe,
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fp2_overxe,
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fp2_invopxe,
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fp2_nsfp,
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fp2_fractie,
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fp2_raz,
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1'b0,
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fp2_neg,
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fp2_pos,
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fp2_zero,
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fp2_inf,
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fp2_swtx,
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fp2_inex,
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fp2_dbzx,
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fp2_underx,
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fp2_overx,
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fp2_giopx,
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fp2_gx,
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fp2_sx,
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fp2_cvtx,
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fp2_sqrtx,
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fp2_NaNCmpx,
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fp2_infzerox,
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fp2_zerozerox,
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fp2_infdivx,
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fp2_subinfx,
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fp2_snanx
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};
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reg [63:0] fpu1_csr;
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wire [5:0] fp1_rgs = fpu1_csr[37:32];
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//reg [25:0] m[0:8191];
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//reg [25:0] m[0:8191];
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reg [3:0] panic; // indexes the message structure
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reg [3:0] panic; // indexes the message structure
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reg [128:0] message [0:15]; // indexed by panic
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reg [128:0] message [0:15]; // indexed by panic
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wire int_commit;
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wire int_commit;
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reg StatusHWI;
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reg StatusHWI;
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reg [47:0] insn0, insn1;
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reg [47:0] insn0, insn1, insn2;
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wire [47:0] insn0a, insn1a, insn1b;
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wire [47:0] insn0a, insn1a, insn1b, insn2a, insn2b;
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reg tgtq;
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reg tgtq;
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// Only need enough bits in the seqnence number to cover the instructions in
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// Only need enough bits in the seqnence number to cover the instructions in
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// the queue plus an extra count for skipping on branch misses. In this case
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// the queue plus an extra count for skipping on branch misses. In this case
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// that would be four bits minimum (count 0 to 8).
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// that would be four bits minimum (count 0 to 8).
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reg [31:0] seq_num;
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reg [31:0] seq_num;
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| Line 413... |
Line 490... |
reg [QENTRIES-1:0] iqentry_alu = 8'h00; // alu type instruction
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reg [QENTRIES-1:0] iqentry_alu = 8'h00; // alu type instruction
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reg [QENTRIES-1:0] iqentry_alu0; // only valid on alu #0
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reg [QENTRIES-1:0] iqentry_alu0; // only valid on alu #0
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reg [QENTRIES-1:0] iqentry_fpu; // floating point instruction
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reg [QENTRIES-1:0] iqentry_fpu; // floating point instruction
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reg [QENTRIES-1:0] iqentry_fc; // flow control instruction
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reg [QENTRIES-1:0] iqentry_fc; // flow control instruction
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reg [QENTRIES-1:0] iqentry_canex = 8'h00; // true if it's an instruction that can exception
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reg [QENTRIES-1:0] iqentry_canex = 8'h00; // true if it's an instruction that can exception
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reg iqentry_load [0:QENTRIES-1]; // is a memory load instruction
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reg [QENTRIES-1:0] iqentry_load; // is a memory load instruction
|
reg iqentry_preload [0:QENTRIES-1]; // is a memory preload instruction
|
reg [QENTRIES-1:0] iqentry_preload; // is a memory preload instruction
|
reg iqentry_ldcmp [0:QENTRIES-1];
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reg [QENTRIES-1:0] iqentry_ldcmp;
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reg iqentry_mem [0:QENTRIES-1]; // touches memory: 1 if LW/SW
|
reg [QENTRIES-1:0] iqentry_mem; // touches memory: 1 if LW/SW
|
reg iqentry_memndx [0:QENTRIES-1]; // indexed memory operation
|
reg [QENTRIES-1:0] iqentry_memndx; // indexed memory operation
|
reg iqentry_rmw [0:QENTRIES-1]; // memory RMW op
|
reg [QENTRIES-1:0] iqentry_rmw; // memory RMW op
|
reg iqentry_memdb [0:QENTRIES-1];
|
reg [QENTRIES-1:0] iqentry_memdb;
|
reg iqentry_memsb [0:QENTRIES-1];
|
reg [QENTRIES-1:0] iqentry_memsb;
|
reg iqentry_rtop [0:QENTRIES-1];
|
reg [QENTRIES-1:0] iqentry_rtop;
|
reg [QENTRIES-1:0] iqentry_sei;
|
reg [QENTRIES-1:0] iqentry_sei;
|
reg [QENTRIES-1:0] iqentry_aq; // memory aquire
|
reg [QENTRIES-1:0] iqentry_aq; // memory aquire
|
reg [QENTRIES-1:0] iqentry_rl; // memory release
|
reg [QENTRIES-1:0] iqentry_rl; // memory release
|
reg iqentry_shft48[0:QENTRIES-1];
|
reg [QENTRIES-1:0] iqentry_shft48;
|
reg iqentry_jmp [0:QENTRIES-1]; // changes control flow: 1 if BEQ/JALR
|
reg [QENTRIES-1:0] iqentry_jmp; // changes control flow: 1 if BEQ/JALR
|
reg [QENTRIES-1:0] iqentry_br; // Bcc (for predictor)
|
reg [QENTRIES-1:0] iqentry_br; // Bcc (for predictor)
|
reg iqentry_sync [0:QENTRIES-1]; // sync instruction
|
reg [QENTRIES-1:0] iqentry_sync; // sync instruction
|
reg iqentry_fsync[0:QENTRIES-1];
|
reg [QENTRIES-1:0] iqentry_fsync;
|
reg [QENTRIES-1:0] iqentry_rfw = 8'h00; // writes to register file
|
reg [QENTRIES-1:0] iqentry_rfw = 8'h00; // writes to register file
|
reg [7:0] iqentry_we [0:QENTRIES-1]; // enable strobe
|
reg [7:0] iqentry_we [0:QENTRIES-1]; // enable strobe
|
reg [63:0] iqentry_res [0:QENTRIES-1]; // instruction result
|
reg [63:0] iqentry_res [0:QENTRIES-1]; // instruction result
|
reg [47:0] iqentry_instr[0:QENTRIES-1]; // instruction opcode
|
reg [47:0] iqentry_instr[0:QENTRIES-1]; // instruction opcode
|
reg [2:0] iqentry_insln[0:QENTRIES-1]; // instruction length
|
reg [2:0] iqentry_insln[0:QENTRIES-1]; // instruction length
|
| Line 449... |
Line 526... |
reg iqentry_a2_v [0:QENTRIES-1]; // arg2 valid
|
reg iqentry_a2_v [0:QENTRIES-1]; // arg2 valid
|
reg [4:0] iqentry_a2_s [0:QENTRIES-1]; // arg2 source (iq entry # with top bit representing ALU/DRAM bus)
|
reg [4:0] iqentry_a2_s [0:QENTRIES-1]; // arg2 source (iq entry # with top bit representing ALU/DRAM bus)
|
reg [63:0] iqentry_a3 [0:QENTRIES-1]; // argument 3
|
reg [63:0] iqentry_a3 [0:QENTRIES-1]; // argument 3
|
reg iqentry_a3_v [0:QENTRIES-1]; // arg3 valid
|
reg iqentry_a3_v [0:QENTRIES-1]; // arg3 valid
|
reg [4:0] iqentry_a3_s [0:QENTRIES-1]; // arg3 source (iq entry # with top bit representing ALU/DRAM bus)
|
reg [4:0] iqentry_a3_s [0:QENTRIES-1]; // arg3 source (iq entry # with top bit representing ALU/DRAM bus)
|
reg [31:0] iqentry_pc [0:QENTRIES-1]; // program counter for this instruction
|
reg [`ABITS] iqentry_pc [0:QENTRIES-1]; // program counter for this instruction
|
reg [RBIT:0] iqentry_Ra [0:QENTRIES-1];
|
reg [RBIT:0] iqentry_Ra [0:QENTRIES-1];
|
reg [RBIT:0] iqentry_Rb [0:QENTRIES-1];
|
reg [RBIT:0] iqentry_Rb [0:QENTRIES-1];
|
reg [RBIT:0] iqentry_Rc [0:QENTRIES-1];
|
reg [RBIT:0] iqentry_Rc [0:QENTRIES-1];
|
// debugging
|
// debugging
|
//reg [4:0] iqentry_ra [0:7]; // Ra
|
//reg [4:0] iqentry_ra [0:7]; // Ra
|
| Line 475... |
Line 552... |
reg [QENTRIES-1:0] iqentry_memissue;
|
reg [QENTRIES-1:0] iqentry_memissue;
|
wire [QENTRIES-1:0] iqentry_stomp;
|
wire [QENTRIES-1:0] iqentry_stomp;
|
reg [3:0] stompedOnRets;
|
reg [3:0] stompedOnRets;
|
reg [QENTRIES-1:0] iqentry_alu0_issue;
|
reg [QENTRIES-1:0] iqentry_alu0_issue;
|
reg [QENTRIES-1:0] iqentry_alu1_issue;
|
reg [QENTRIES-1:0] iqentry_alu1_issue;
|
|
reg [QENTRIES-1:0] iqentry_alu2_issue;
|
reg [QENTRIES-1:0] iqentry_id1issue;
|
reg [QENTRIES-1:0] iqentry_id1issue;
|
reg [QENTRIES-1:0] iqentry_id2issue;
|
reg [QENTRIES-1:0] iqentry_id2issue;
|
|
reg [QENTRIES-1:0] iqentry_id3issue;
|
reg [1:0] iqentry_mem_islot [0:QENTRIES-1];
|
reg [1:0] iqentry_mem_islot [0:QENTRIES-1];
|
reg [1:0] iqentry_fpu_islot [0:QENTRIES-1];
|
|
reg [QENTRIES-1:0] iqentry_fcu_issue;
|
reg [QENTRIES-1:0] iqentry_fcu_issue;
|
reg [QENTRIES-1:0] iqentry_fpu_issue;
|
reg [QENTRIES-1:0] iqentry_fpu1_issue;
|
|
reg [QENTRIES-1:0] iqentry_fpu2_issue;
|
|
|
wire [PREGS-1:1] livetarget;
|
wire [PREGS-1:1] livetarget;
|
wire [PREGS-1:1] iqentry_0_livetarget;
|
wire [PREGS-1:1] iqentry_0_livetarget;
|
wire [PREGS-1:1] iqentry_1_livetarget;
|
wire [PREGS-1:1] iqentry_1_livetarget;
|
wire [PREGS-1:1] iqentry_2_livetarget;
|
wire [PREGS-1:1] iqentry_2_livetarget;
|
| Line 532... |
Line 611... |
wire take_branch0;
|
wire take_branch0;
|
wire take_branch1;
|
wire take_branch1;
|
|
|
reg [3:0] nop_fetchbuf;
|
reg [3:0] nop_fetchbuf;
|
wire fetchbuf; // determines which pair to read from & write to
|
wire fetchbuf; // determines which pair to read from & write to
|
|
wire [3:0] fb_panic;
|
|
|
wire [47:0] fetchbuf0_instr;
|
wire [47:0] fetchbuf0_instr;
|
wire [2:0] fetchbuf0_insln;
|
wire [2:0] fetchbuf0_insln;
|
wire [31:0] fetchbuf0_pc;
|
wire [`ABITS] fetchbuf0_pc;
|
wire fetchbuf0_v;
|
wire fetchbuf0_v;
|
wire fetchbuf0_thrd;
|
wire fetchbuf0_thrd;
|
wire fetchbuf0_mem;
|
wire fetchbuf0_mem;
|
wire fetchbuf0_memld;
|
wire fetchbuf0_memld;
|
wire fetchbuf0_jmp;
|
wire fetchbuf0_jmp;
|
wire fetchbuf0_rfw;
|
wire fetchbuf0_rfw;
|
wire [47:0] fetchbuf1_instr;
|
wire [47:0] fetchbuf1_instr;
|
wire [2:0] fetchbuf1_insln;
|
wire [2:0] fetchbuf1_insln;
|
wire [31:0] fetchbuf1_pc;
|
wire [`ABITS] fetchbuf1_pc;
|
wire fetchbuf1_v;
|
wire fetchbuf1_v;
|
wire fetchbuf1_thrd;
|
wire fetchbuf1_thrd;
|
wire fetchbuf1_mem;
|
wire fetchbuf1_mem;
|
wire fetchbuf1_memld;
|
wire fetchbuf1_memld;
|
wire fetchbuf1_jmp;
|
wire fetchbuf1_jmp;
|
wire fetchbuf1_rfw;
|
wire fetchbuf1_rfw;
|
|
|
wire [47:0] fetchbufA_instr;
|
wire [47:0] fetchbufA_instr;
|
wire [31:0] fetchbufA_pc;
|
wire [`ABITS] fetchbufA_pc;
|
wire fetchbufA_v;
|
wire fetchbufA_v;
|
wire [47:0] fetchbufB_instr;
|
wire [47:0] fetchbufB_instr;
|
wire [31:0] fetchbufB_pc;
|
wire [`ABITS] fetchbufB_pc;
|
wire fetchbufB_v;
|
wire fetchbufB_v;
|
wire [47:0] fetchbufC_instr;
|
wire [47:0] fetchbufC_instr;
|
wire [31:0] fetchbufC_pc;
|
wire [`ABITS] fetchbufC_pc;
|
wire fetchbufC_v;
|
wire fetchbufC_v;
|
wire [47:0] fetchbufD_instr;
|
wire [47:0] fetchbufD_instr;
|
wire [31:0] fetchbufD_pc;
|
wire [`ABITS] fetchbufD_pc;
|
wire fetchbufD_v;
|
wire fetchbufD_v;
|
|
|
//reg did_branchback0;
|
//reg did_branchback0;
|
//reg did_branchback1;
|
//reg did_branchback1;
|
|
|
reg id1_available;
|
|
reg id1_v;
|
reg id1_v;
|
reg [4:0] id1_id;
|
reg [4:0] id1_id;
|
reg [47:0] id1_instr;
|
reg [47:0] id1_instr;
|
reg [5:0] id1_ven;
|
reg [5:0] id1_ven;
|
reg [7:0] id1_vl;
|
reg [7:0] id1_vl;
|
reg id1_thrd;
|
reg id1_thrd;
|
reg id1_pt;
|
reg id1_pt;
|
reg [4:0] id1_Rt;
|
reg [4:0] id1_Rt;
|
wire [127:0] id1_bus;
|
wire [127:0] id1_bus;
|
|
|
reg id2_available;
|
|
reg id2_v;
|
reg id2_v;
|
reg [4:0] id2_id;
|
reg [4:0] id2_id;
|
reg [47:0] id2_instr;
|
reg [47:0] id2_instr;
|
reg [5:0] id2_ven;
|
reg [5:0] id2_ven;
|
reg [7:0] id2_vl;
|
reg [7:0] id2_vl;
|
reg id2_thrd;
|
reg id2_thrd;
|
reg id2_pt;
|
reg id2_pt;
|
reg [4:0] id2_Rt;
|
reg [4:0] id2_Rt;
|
wire [127:0] id2_bus;
|
wire [127:0] id2_bus;
|
|
|
|
reg id3_v;
|
|
reg [4:0] id3_id;
|
|
reg [47:0] id3_instr;
|
|
reg [5:0] id3_ven;
|
|
reg [7:0] id3_vl;
|
|
reg id3_thrd;
|
|
reg id3_pt;
|
|
reg [4:0] id3_Rt;
|
|
wire [127:0] id3_bus;
|
|
|
reg alu0_ld;
|
reg alu0_ld;
|
reg alu0_available;
|
|
reg alu0_dataready;
|
reg alu0_dataready;
|
wire alu0_done;
|
wire alu0_done;
|
wire alu0_idle;
|
wire alu0_idle;
|
reg [3:0] alu0_sourceid;
|
reg [3:0] alu0_sourceid;
|
reg [47:0] alu0_instr;
|
reg [47:0] alu0_instr;
|
| Line 607... |
Line 694... |
reg [63:0] alu0_argC;
|
reg [63:0] alu0_argC;
|
reg [63:0] alu0_argI; // only used by BEQ
|
reg [63:0] alu0_argI; // only used by BEQ
|
reg [RBIT:0] alu0_tgt;
|
reg [RBIT:0] alu0_tgt;
|
reg [5:0] alu0_ven;
|
reg [5:0] alu0_ven;
|
reg alu0_thrd;
|
reg alu0_thrd;
|
reg [31:0] alu0_pc;
|
reg [`ABITS] alu0_pc;
|
wire [63:0] alu0_bus;
|
wire [63:0] alu0_bus;
|
wire [63:0] alu0b_bus;
|
wire [63:0] alu0b_bus;
|
wire [3:0] alu0_id;
|
wire [3:0] alu0_id;
|
wire [8:0] alu0_exc;
|
wire [`XBITS] alu0_exc;
|
wire alu0_v;
|
wire alu0_v;
|
wire alu0_branchmiss;
|
wire alu0_branchmiss;
|
wire [31:0] alu0_misspc;
|
wire [`ABITS] alu0_misspc;
|
|
|
reg alu1_ld;
|
reg alu1_ld;
|
reg alu1_available;
|
|
reg alu1_dataready;
|
reg alu1_dataready;
|
wire alu1_done;
|
wire alu1_done;
|
wire alu1_idle;
|
wire alu1_idle;
|
reg [3:0] alu1_sourceid;
|
reg [3:0] alu1_sourceid;
|
reg [47:0] alu1_instr;
|
reg [47:0] alu1_instr;
|
| Line 632... |
Line 718... |
reg [63:0] alu1_argB;
|
reg [63:0] alu1_argB;
|
reg [63:0] alu1_argC;
|
reg [63:0] alu1_argC;
|
reg [63:0] alu1_argI; // only used by BEQ
|
reg [63:0] alu1_argI; // only used by BEQ
|
reg [RBIT:0] alu1_tgt;
|
reg [RBIT:0] alu1_tgt;
|
reg [5:0] alu1_ven;
|
reg [5:0] alu1_ven;
|
reg [31:0] alu1_pc;
|
reg [`ABITS] alu1_pc;
|
reg alu1_thrd;
|
reg alu1_thrd;
|
wire [63:0] alu1_bus;
|
wire [63:0] alu1_bus;
|
wire [63:0] alu1b_bus;
|
wire [63:0] alu1b_bus;
|
wire [3:0] alu1_id;
|
wire [3:0] alu1_id;
|
wire [8:0] alu1_exc;
|
wire [`XBITS] alu1_exc;
|
wire alu1_v;
|
wire alu1_v;
|
wire alu1_branchmiss;
|
wire alu1_branchmiss;
|
wire [31:0] alu1_misspc;
|
wire [`ABITS] alu1_misspc;
|
|
|
reg fpu_ld;
|
reg fpu1_ld;
|
reg fpu1_available = 1'b1;
|
reg fpu1_dataready = 1'b1;
|
reg fpu_dataready = 1'b1;
|
wire fpu1_done = 1'b1;
|
wire fpu_done = 1'b1;
|
wire fpu1_idle;
|
wire fpu_idle;
|
reg [3:0] fpu1_sourceid;
|
reg [3:0] fpu_sourceid;
|
reg [47:0] fpu1_instr;
|
reg [47:0] fpu_instr;
|
reg [63:0] fpu1_argA;
|
reg [63:0] fpu_argA;
|
reg [63:0] fpu1_argB;
|
reg [63:0] fpu_argB;
|
reg [63:0] fpu1_argC;
|
reg [63:0] fpu_argC;
|
reg [63:0] fpu1_argI; // only used by BEQ
|
reg [63:0] fpu_argI; // only used by BEQ
|
reg [RBIT:0] fpu1_tgt;
|
reg [RBIT:0] fpu_tgt;
|
reg [`ABITS] fpu1_pc;
|
reg [31:0] fpu_pc;
|
wire [63:0] fpu1_bus;
|
wire [63:0] fpu_bus;
|
wire [3:0] fpu1_id;
|
wire [3:0] fpu_id;
|
wire [`XBITS] fpu1_exc = 9'h000;
|
wire [8:0] fpu_exc = 9'h000;
|
wire fpu1_v;
|
wire fpu_v;
|
wire [31:0] fpu1_status;
|
wire [31:0] fpu_status;
|
|
|
reg fpu2_ld;
|
|
reg fpu2_dataready = 1'b1;
|
|
wire fpu2_done = 1'b1;
|
|
wire fpu2_idle;
|
|
reg [3:0] fpu2_sourceid;
|
|
reg [47:0] fpu2_instr;
|
|
reg [63:0] fpu2_argA;
|
|
reg [63:0] fpu2_argB;
|
|
reg [63:0] fpu2_argC;
|
|
reg [63:0] fpu2_argI; // only used by BEQ
|
|
reg [RBIT:0] fpu2_tgt;
|
|
reg [`ABITS] fpu2_pc;
|
|
wire [63:0] fpu2_bus;
|
|
wire [3:0] fpu2_id;
|
|
wire [`XBITS] fpu2_exc = 9'h000;
|
|
wire fpu2_v;
|
|
wire [31:0] fpu2_status;
|
|
|
reg [63:0] waitctr;
|
reg [63:0] waitctr;
|
reg fcu_ld;
|
reg fcu_ld;
|
reg fcu_dataready;
|
reg fcu_dataready;
|
reg fcu_done;
|
reg fcu_done;
|
| Line 677... |
Line 780... |
reg [63:0] fcu_argB;
|
reg [63:0] fcu_argB;
|
reg [63:0] fcu_argC;
|
reg [63:0] fcu_argC;
|
reg [63:0] fcu_argI; // only used by BEQ
|
reg [63:0] fcu_argI; // only used by BEQ
|
reg [63:0] fcu_argT;
|
reg [63:0] fcu_argT;
|
reg [63:0] fcu_argT2;
|
reg [63:0] fcu_argT2;
|
reg [31:0] fcu_retadr;
|
reg [`ABITS] fcu_retadr;
|
reg fcu_retadr_v;
|
reg fcu_retadr_v;
|
reg [31:0] fcu_pc;
|
reg [`ABITS] fcu_pc;
|
reg [31:0] fcu_nextpc;
|
reg [`ABITS] fcu_nextpc;
|
reg [31:0] fcu_brdisp;
|
reg [`ABITS] fcu_brdisp;
|
wire [63:0] fcu_bus;
|
wire [63:0] fcu_bus;
|
wire [3:0] fcu_id;
|
wire [3:0] fcu_id;
|
reg [8:0] fcu_exc;
|
reg [`XBITS] fcu_exc;
|
wire fcu_v;
|
wire fcu_v;
|
reg fcu_thrd;
|
reg fcu_thrd;
|
reg fcu_branchmiss;
|
reg fcu_branchmiss;
|
reg fcu_clearbm;
|
reg fcu_clearbm;
|
reg [31:0] fcu_misspc;
|
reg [`ABITS] fcu_misspc;
|
|
|
reg [63:0] rmw_argA;
|
reg [63:0] rmw_argA;
|
reg [63:0] rmw_argB;
|
reg [63:0] rmw_argB;
|
reg [63:0] rmw_argC;
|
reg [63:0] rmw_argC;
|
wire [63:0] rmw_res;
|
wire [63:0] rmw_res;
|
reg [31:0] rmw_instr;
|
reg [31:0] rmw_instr;
|
|
|
|
// write buffer
|
|
reg [63:0] wb_data [0:`WB_DEPTH-1];
|
|
reg [`ABITS] wb_addr [0:`WB_DEPTH-1];
|
|
reg [1:0] wb_ol [0:`WB_DEPTH-1];
|
|
reg [`WB_DEPTH-1:0] wb_v;
|
|
reg [`WB_DEPTH-1:0] wb_rmw;
|
|
reg [QENTRIES-1:0] wb_id [0:`WB_DEPTH-1];
|
|
reg [QENTRIES-1:0] wbo_id;
|
|
reg [7:0] wb_sel [0:`WB_DEPTH-1];
|
|
reg wb_en;
|
|
|
reg branchmiss = 1'b0;
|
reg branchmiss = 1'b0;
|
reg branchmiss_thrd = 1'b0;
|
reg branchmiss_thrd = 1'b0;
|
reg [31:0] misspc;
|
reg [`ABITS] misspc;
|
reg [`QBITS] missid;
|
reg [`QBITS] missid;
|
|
|
wire take_branch;
|
wire take_branch;
|
wire take_branchA;
|
wire take_branchA;
|
wire take_branchB;
|
wire take_branchB;
|
| Line 713... |
Line 827... |
wire dram_avail;
|
wire dram_avail;
|
reg [2:0] dram0; // state of the DRAM request (latency = 4; can have three in pipeline)
|
reg [2:0] dram0; // state of the DRAM request (latency = 4; can have three in pipeline)
|
reg [2:0] dram1; // state of the DRAM request (latency = 4; can have three in pipeline)
|
reg [2:0] dram1; // state of the DRAM request (latency = 4; can have three in pipeline)
|
reg [2:0] dram2; // state of the DRAM request (latency = 4; can have three in pipeline)
|
reg [2:0] dram2; // state of the DRAM request (latency = 4; can have three in pipeline)
|
reg [63:0] dram0_data;
|
reg [63:0] dram0_data;
|
reg [31:0] dram0_addr;
|
reg [`ABITS] dram0_addr;
|
reg [31:0] dram0_seg;
|
reg [31:0] dram0_seg;
|
reg [47:0] dram0_instr;
|
reg [47:0] dram0_instr;
|
reg dram0_rmw;
|
reg dram0_rmw;
|
reg dram0_preload;
|
reg dram0_preload;
|
reg [RBIT:0] dram0_tgt;
|
reg [RBIT:0] dram0_tgt;
|
reg [3:0] dram0_id;
|
reg [3:0] dram0_id;
|
reg [8:0] dram0_exc;
|
reg [`XBITS] dram0_exc;
|
reg dram0_unc;
|
reg dram0_unc;
|
reg [2:0] dram0_memsize;
|
reg [2:0] dram0_memsize;
|
reg dram0_load; // is a load operation
|
reg dram0_load; // is a load operation
|
reg [1:0] dram0_ol;
|
reg [1:0] dram0_ol;
|
reg [63:0] dram1_data;
|
reg [63:0] dram1_data;
|
reg [31:0] dram1_addr;
|
reg [`ABITS] dram1_addr;
|
reg [31:0] dram1_seg;
|
reg [31:0] dram1_seg;
|
reg [47:0] dram1_instr;
|
reg [47:0] dram1_instr;
|
reg dram1_rmw;
|
reg dram1_rmw;
|
reg dram1_preload;
|
reg dram1_preload;
|
reg [RBIT:0] dram1_tgt;
|
reg [RBIT:0] dram1_tgt;
|
reg [3:0] dram1_id;
|
reg [3:0] dram1_id;
|
reg [8:0] dram1_exc;
|
reg [`XBITS] dram1_exc;
|
reg dram1_unc;
|
reg dram1_unc;
|
reg [2:0] dram1_memsize;
|
reg [2:0] dram1_memsize;
|
reg dram1_load;
|
reg dram1_load;
|
reg [1:0] dram1_ol;
|
reg [1:0] dram1_ol;
|
reg [63:0] dram2_data;
|
reg [63:0] dram2_data;
|
reg [31:0] dram2_addr;
|
reg [`ABITS] dram2_addr;
|
reg [31:0] dram2_seg;
|
reg [31:0] dram2_seg;
|
reg [47:0] dram2_instr;
|
reg [47:0] dram2_instr;
|
reg dram2_rmw;
|
reg dram2_rmw;
|
reg dram2_preload;
|
reg dram2_preload;
|
reg [RBIT:0] dram2_tgt;
|
reg [RBIT:0] dram2_tgt;
|
reg [3:0] dram2_id;
|
reg [3:0] dram2_id;
|
reg [8:0] dram2_exc;
|
reg [`XBITS] dram2_exc;
|
reg dram2_unc;
|
reg dram2_unc;
|
reg [2:0] dram2_memsize;
|
reg [2:0] dram2_memsize;
|
reg dram2_load;
|
reg dram2_load;
|
reg [1:0] dram2_ol;
|
reg [1:0] dram2_ol;
|
|
|
reg dramA_v;
|
reg dramA_v;
|
reg [3:0] dramA_id;
|
reg [3:0] dramA_id;
|
reg [63:0] dramA_bus;
|
reg [63:0] dramA_bus;
|
reg [8:0] dramA_exc;
|
reg [`XBITS] dramA_exc;
|
reg dramB_v;
|
reg dramB_v;
|
reg [3:0] dramB_id;
|
reg [3:0] dramB_id;
|
reg [63:0] dramB_bus;
|
reg [63:0] dramB_bus;
|
reg [8:0] dramB_exc;
|
reg [`XBITS] dramB_exc;
|
reg dramC_v;
|
reg dramC_v;
|
reg [3:0] dramC_id;
|
reg [3:0] dramC_id;
|
reg [63:0] dramC_bus;
|
reg [63:0] dramC_bus;
|
reg [8:0] dramC_exc;
|
reg [`XBITS] dramC_exc;
|
|
|
wire outstanding_stores;
|
wire outstanding_stores;
|
reg [63:0] I; // instruction count
|
reg [63:0] I; // instruction count
|
|
|
reg commit0_v;
|
reg commit0_v;
|
| Line 821... |
Line 935... |
parameter IC8 = 4'd8;
|
parameter IC8 = 4'd8;
|
parameter IC9 = 4'd9;
|
parameter IC9 = 4'd9;
|
parameter IC10 = 4'd10;
|
parameter IC10 = 4'd10;
|
parameter IC3a = 4'd11;
|
parameter IC3a = 4'd11;
|
reg invic, invdc;
|
reg invic, invdc;
|
reg icwhich,icnxt,L2_nxt;
|
reg [1:0] icwhich;
|
wire ihit0,ihit1,ihit2;
|
reg icnxt,L2_nxt;
|
wire ihit = ihit0&ihit1;
|
wire ihit0,ihit1,ihit2,ihitL2;
|
|
wire ihit = ihit0&ihit1&ihit2;
|
reg phit;
|
reg phit;
|
wire threadx;
|
wire threadx;
|
always @*
|
always @*
|
phit <= ihit&&icstate==IDLE;
|
phit <= ihit&&icstate==IDLE;
|
reg [2:0] iccnt;
|
reg [2:0] iccnt;
|
reg L1_wr0,L1_wr1;
|
reg L1_wr0,L1_wr1,L1_wr2;
|
reg L1_invline;
|
reg L1_invline;
|
reg [9:0] L1_en;
|
reg [8:0] L1_en;
|
reg [37:0] L1_adr, L2_adr;
|
reg [37:0] L1_adr, L2_adr;
|
reg [319:0] L2_rdat;
|
reg [287:0] L2_rdat;
|
wire [319:0] L2_dato;
|
wire [287:0] L2_dato;
|
reg L2_xsel;
|
reg L2_xsel;
|
|
|
FT64_regfile2w6r_oc #(.RBIT(RBIT)) urf1
|
FT64_regfile2w6r_oc #(.RBIT(RBIT)) urf1
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
| Line 876... |
Line 991... |
2'b10: fnInsLength = 3'd2;
|
2'b10: fnInsLength = 3'd2;
|
2'b11: fnInsLength = 3'd2;
|
2'b11: fnInsLength = 3'd2;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
wire [31:0] pc0plus6 = pc0 + 32'd6;
|
wire [`ABITS] pc0plus6 = pc0 + 32'd6;
|
|
wire [`ABITS] pc0plus12 = pc0 + 32'd12;
|
|
|
`ifdef SUPPORT_SMT
|
`ifdef SUPPORT_SMT
|
|
generate begin : gInsnVar
|
|
if (`WAYS > 1) begin
|
assign insn1a = insn1b;
|
assign insn1a = insn1b;
|
|
end
|
|
if (`WAYS > 2) begin
|
|
assign insn2a = insn2b;
|
|
end
|
|
end
|
|
endgenerate
|
`else
|
`else
|
|
generate begin : gInsnVar
|
|
if (`WAYS > 1) begin
|
assign insn1a = {insn1b,insn0a} >> {fnInsLength(insn0a),3'b0};
|
assign insn1a = {insn1b,insn0a} >> {fnInsLength(insn0a),3'b0};
|
|
end
|
|
if (`WAYS > 2) begin
|
|
assign insn2a = {insn2b,insn1b,insn0a} >> {fnInsLength(insn0a) + fnInsLength(insn1a),3'b0};
|
|
end
|
|
end
|
|
endgenerate
|
`endif
|
`endif
|
|
|
FT64_L1_icache uic0
|
FT64_L1_icache uic0
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
| Line 899... |
Line 1031... |
.o(insn0a),
|
.o(insn0a),
|
.hit(ihit0),
|
.hit(ihit0),
|
.invall(invic),
|
.invall(invic),
|
.invline(L1_invline)
|
.invline(L1_invline)
|
);
|
);
|
|
generate begin : gICacheInst
|
|
if (`WAYS > 1) begin
|
FT64_L1_icache uic1
|
FT64_L1_icache uic1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.clk(clk),
|
.clk(clk),
|
.nxt(icnxt),
|
.nxt(icnxt),
|
| Line 918... |
Line 1052... |
.o(insn1b),
|
.o(insn1b),
|
.hit(ihit1),
|
.hit(ihit1),
|
.invall(invic),
|
.invall(invic),
|
.invline(L1_invline)
|
.invline(L1_invline)
|
);
|
);
|
|
end
|
|
else begin
|
|
assign ihit1 = 1'b1;
|
|
end
|
|
if (`WAYS > 2) begin
|
|
FT64_L1_icache uic2
|
|
(
|
|
.rst(rst),
|
|
.clk(clk),
|
|
.nxt(icnxt),
|
|
.wr(L1_wr2),
|
|
.en(L1_en),
|
|
`ifdef SUPPORT_SMT
|
|
.adr(icstate==IDLE||icstate==IC8 ? {pcr[5:0],pc2} : L1_adr),
|
|
`else
|
|
.adr(icstate==IDLE||icstate==IC8 ? {pcr[5:0],pc0plus12} : L1_adr),
|
|
`endif
|
|
.wadr(L1_adr),
|
|
.i(L2_rdat),
|
|
.o(insn2b),
|
|
.hit(ihit2),
|
|
.invall(invic),
|
|
.invline(L1_invline)
|
|
);
|
|
end
|
|
else
|
|
assign ihit2 = 1'b1;
|
|
end
|
|
endgenerate
|
|
|
FT64_L2_icache uic2
|
FT64_L2_icache uic2
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.clk(clk),
|
.clk(clk),
|
.nxt(L2_nxt),
|
.nxt(L2_nxt),
|
| Line 931... |
Line 1095... |
.cnt(iccnt),
|
.cnt(iccnt),
|
.exv_i(exvq),
|
.exv_i(exvq),
|
.i(dat_i),
|
.i(dat_i),
|
.err_i(errq),
|
.err_i(errq),
|
.o(L2_dato),
|
.o(L2_dato),
|
.hit(ihit2),
|
.hit(ihitL2),
|
.invall(invic),
|
.invall(invic),
|
.invline()
|
.invline()
|
);
|
);
|
|
|
wire predict_taken;
|
wire predict_taken;
|
| Line 948... |
Line 1112... |
wire predict_takenA1;
|
wire predict_takenA1;
|
wire predict_takenB1;
|
wire predict_takenB1;
|
wire predict_takenC1;
|
wire predict_takenC1;
|
wire predict_takenD1;
|
wire predict_takenD1;
|
|
|
wire [31:0] btgtA, btgtB, btgtC, btgtD;
|
wire [`ABITS] btgtA, btgtB, btgtC, btgtD;
|
wire btbwr0 = iqentry_v[head0] && iqentry_done[head0] &&
|
wire btbwr0 = iqentry_v[head0] && iqentry_done[head0] &&
|
(
|
(
|
iqentry_instr[head0][`INSTRUCTION_OP]==`JAL ||
|
iqentry_instr[head0][`INSTRUCTION_OP]==`JAL ||
|
iqentry_instr[head0][`INSTRUCTION_OP]==`BRK ||
|
iqentry_instr[head0][`INSTRUCTION_OP]==`BRK ||
|
IsRTI(iqentry_instr[head0]));
|
IsRTI(iqentry_instr[head0]));
|
| Line 960... |
Line 1124... |
(
|
(
|
iqentry_instr[head1][`INSTRUCTION_OP]==`JAL ||
|
iqentry_instr[head1][`INSTRUCTION_OP]==`JAL ||
|
iqentry_instr[head1][`INSTRUCTION_OP]==`BRK ||
|
iqentry_instr[head1][`INSTRUCTION_OP]==`BRK ||
|
IsRTI(iqentry_instr[head1]));
|
IsRTI(iqentry_instr[head1]));
|
|
|
|
`ifdef FCU_ENH
|
|
wire fcu_clk;
|
|
BUFGCE ufcuclk
|
|
(
|
|
.I(clk_i),
|
|
.CE(fcu_available),
|
|
.O(fcu_clk)
|
|
);
|
|
`endif
|
|
|
|
`ifdef FCU_ENH
|
FT64_BTB ubtb1
|
FT64_BTB ubtb1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.wclk(clk),
|
.wclk(fcu_clk),
|
.wr(btbwr0 | btbwr1),
|
.wr(btbwr0 | btbwr1),
|
.wadr(btbwr0 ? iqentry_pc[head0] : iqentry_pc[head1]),
|
.wadr(btbwr0 ? iqentry_pc[head0] : iqentry_pc[head1]),
|
.wdat(btbwr0 ? iqentry_a0[head0] : iqentry_a0[head1]),
|
.wdat(btbwr0 ? iqentry_a0[head0] : iqentry_a0[head1]),
|
.valid(btbwr0 ? iqentry_bt[head0] & iqentry_v[head0] : iqentry_bt[head1] & iqentry_v[head1]),
|
.valid(btbwr0 ? iqentry_bt[head0] & iqentry_v[head0] : iqentry_bt[head1] & iqentry_v[head1]),
|
.rclk(~clk),
|
.rclk(~clk),
|
| Line 982... |
Line 1157... |
.npcA(BRKPC),
|
.npcA(BRKPC),
|
.npcB(BRKPC),
|
.npcB(BRKPC),
|
.npcC(BRKPC),
|
.npcC(BRKPC),
|
.npcD(BRKPC)
|
.npcD(BRKPC)
|
);
|
);
|
|
`else
|
|
// Branch tergets are picked up by fetchbuf logic and need to be present.
|
|
// Without a target predictor they are just set to the reset address.
|
|
// This virtually guarentees a miss.
|
|
assign btgtA = RSTPC;
|
|
assign btgtB = RSTPC;
|
|
assign btgtC = RSTPC;
|
|
assign btgtD = RSTPC;
|
|
`endif
|
|
|
|
`ifdef FCU_ENH
|
FT64_BranchPredictor ubp1
|
FT64_BranchPredictor ubp1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.clk(clk),
|
.clk(fcu_clk),
|
.en(bpe),
|
.en(bpe),
|
.xisBranch0(iqentry_br[head0] & commit0_v),
|
.xisBranch0(iqentry_br[head0] & commit0_v),
|
.xisBranch1(iqentry_br[head1] & commit1_v),
|
.xisBranch1(iqentry_br[head1] & commit1_v),
|
.pcA(fetchbufA_pc),
|
.pcA(fetchbufA_pc),
|
.pcB(fetchbufB_pc),
|
.pcB(fetchbufB_pc),
|
| Line 1003... |
Line 1188... |
.predict_takenA(predict_takenA),
|
.predict_takenA(predict_takenA),
|
.predict_takenB(predict_takenB),
|
.predict_takenB(predict_takenB),
|
.predict_takenC(predict_takenC),
|
.predict_takenC(predict_takenC),
|
.predict_takenD(predict_takenD)
|
.predict_takenD(predict_takenD)
|
);
|
);
|
|
`else
|
|
// Predict based on sign of displacement
|
|
assign predict_takenA = fetchbufA_instr[31];
|
|
assign predict_takenB = fetchbufB_instr[31];
|
|
assign predict_takenC = fetchbufC_instr[31];
|
|
assign predict_takenD = fetchbufD_instr[31];
|
|
`endif
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Debug
|
// Debug
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
| Line 1247... |
Line 1439... |
|
|
// hirq squashes the pc increment if there's an irq.
|
// hirq squashes the pc increment if there's an irq.
|
wire hirq = (irq_i > im) && ~int_commit;
|
wire hirq = (irq_i > im) && ~int_commit;
|
always @*
|
always @*
|
if (hirq)
|
if (hirq)
|
insn0 <= {8'd0,4'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
|
insn0 <= {8'd0,3'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
|
else if (phit) begin
|
else if (phit) begin
|
if (insn0a[`INSTRUCTION_OP]==`BRK && insn0a[23:20]==4'd0)
|
if (insn0a[`INSTRUCTION_OP]==`BRK && insn0a[23:21]==3'd0 && insn0a[7:6]==2'b00)
|
insn0 <= {8'd1,4'd0,3'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
insn0 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
else
|
else
|
insn0 <= insn0a;
|
insn0 <= insn0a;
|
end
|
end
|
else
|
else
|
insn0 <= `NOP_INSN;
|
insn0 <= `NOP_INSN;
|
|
generate begin : gInsnMux
|
|
if (`WAYS > 1) begin
|
always @*
|
always @*
|
if (phit) begin
|
if (phit) begin
|
if (insn1a[`INSTRUCTION_OP]==`BRK && insn1a[23:20]==4'd0)
|
if (insn1a[`INSTRUCTION_OP]==`BRK && insn1a[23:21]==3'd0 && insn1a[7:6]==2'b00)
|
insn1 <= {8'd1,4'd0,3'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
insn1 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
else
|
else
|
insn1 <= insn1a;
|
insn1 <= insn1a;
|
end
|
end
|
else
|
else
|
insn1 <= `NOP_INSN;
|
insn1 <= `NOP_INSN;
|
|
end
|
|
if (`WAYS > 2) begin
|
|
always @*
|
|
if (phit) begin
|
|
if (insn2a[`INSTRUCTION_OP]==`BRK && insn1a[23:21]==3'd0 && insn2a[7:6]==2'b00)
|
|
insn2 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
|
else
|
|
insn2 <= insn2a;
|
|
end
|
|
else
|
|
insn2 <= `NOP_INSN;
|
|
end
|
|
end
|
|
endgenerate
|
|
|
wire [63:0] dc0_out, dc1_out, dc2_out;
|
wire [63:0] dc0_out, dc1_out, dc2_out;
|
assign rdat0 = dram0_unc ? xdati : dc0_out;
|
assign rdat0 = dram0_unc ? xdati : dc0_out;
|
assign rdat1 = dram1_unc ? xdati : dc1_out;
|
assign rdat1 = dram1_unc ? xdati : dc1_out;
|
assign rdat2 = dram2_unc ? xdati : dc2_out;
|
assign rdat2 = dram2_unc ? xdati : dc2_out;
|
| Line 1276... |
Line 1484... |
reg preload;
|
reg preload;
|
reg [1:0] dccnt;
|
reg [1:0] dccnt;
|
wire dhit0, dhit1, dhit2;
|
wire dhit0, dhit1, dhit2;
|
wire dhit00, dhit10, dhit20;
|
wire dhit00, dhit10, dhit20;
|
wire dhit01, dhit11, dhit21;
|
wire dhit01, dhit11, dhit21;
|
reg [31:0] dc_wadr;
|
reg [`ABITS] dc_wadr;
|
reg [63:0] dc_wdat;
|
reg [63:0] dc_wdat;
|
reg isStore;
|
reg isStore;
|
|
|
FT64_dcache udc0
|
FT64_dcache udc0
|
(
|
(
|
| Line 1296... |
Line 1504... |
.o(dc0_out),
|
.o(dc0_out),
|
.hit(),
|
.hit(),
|
.hit0(dhit0),
|
.hit0(dhit0),
|
.hit1()
|
.hit1()
|
);
|
);
|
|
generate begin : gDCacheInst
|
|
if (`NUM_MEM > 1) begin
|
FT64_dcache udc1
|
FT64_dcache udc1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.wclk(clk),
|
.wclk(clk),
|
.wr((bstate==B2d && ack_i)||((bstate==B1||(bstate==B19 && isStore)) && dhit1)),
|
.wr((bstate==B2d && ack_i)||((bstate==B1||(bstate==B19 && isStore)) && dhit1)),
|
| Line 1312... |
Line 1522... |
.o(dc1_out),
|
.o(dc1_out),
|
.hit(),
|
.hit(),
|
.hit0(dhit1),
|
.hit0(dhit1),
|
.hit1()
|
.hit1()
|
);
|
);
|
|
end
|
|
if (`NUM_MEM > 2) begin
|
FT64_dcache udc2
|
FT64_dcache udc2
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.wclk(clk),
|
.wclk(clk),
|
.wr((bstate==B2d && ack_i)||((bstate==B1||(bstate==B19 && isStore)) && dhit2)),
|
.wr((bstate==B2d && ack_i)||((bstate==B1||(bstate==B19 && isStore)) && dhit2)),
|
| Line 1328... |
Line 1540... |
.o(dc2_out),
|
.o(dc2_out),
|
.hit(),
|
.hit(),
|
.hit0(dhit2),
|
.hit0(dhit2),
|
.hit1()
|
.hit1()
|
);
|
);
|
|
end
|
|
end
|
|
endgenerate
|
|
|
function [`QBITS] idp1;
|
function [`QBITS] idp1;
|
input [`QBITS] id;
|
input [`QBITS] id;
|
case(id)
|
case(id)
|
3'd0: idp1 = 3'd1;
|
3'd0: idp1 = 3'd1;
|
| Line 1471... |
Line 1686... |
3'd0: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd0: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd1: fnRa = {isn[22:18],1'b0,isn[`INSTRUCTION_RA]};
|
3'd1: fnRa = {isn[22:18],1'b0,isn[`INSTRUCTION_RA]};
|
3'd2: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd2: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd3: fnRa = {rs_stack[thrd][5:0],1'b0,isn[`INSTRUCTION_RA]};
|
3'd3: fnRa = {rs_stack[thrd][5:0],1'b0,isn[`INSTRUCTION_RA]};
|
3'd4: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd4: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd5: fnRa = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd5: fnRa = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd6: fnRa = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd6: fnRa = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
default:fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
default:fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
`VMOV:
|
`VMOV:
|
case (isn[`INSTRUCTION_S1])
|
case (isn[`INSTRUCTION_S1])
|
5'h0: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
5'h0: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
5'h1: fnRa = {6'h3F,1'b1,isn[`INSTRUCTION_RA]};
|
5'h1: fnRa = {6'h3F,1'b1,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
default: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
default: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
`FLOAT: fnRa = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
`FLOAT: fnRa = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
default: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
default: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [RBIT:0] fnRb;
|
function [RBIT:0] fnRb;
|
| Line 1517... |
Line 1732... |
fnRb = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
fnRb = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
`VSHL,`VSHR,`VASR:
|
`VSHL,`VSHR,`VASR:
|
fnRb = {isn[25],isn[22]}==2'b00 ? {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]} : {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
fnRb = {isn[25],isn[22]}==2'b00 ? {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]} : {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
default: fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
default: fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
`FLOAT: fnRb = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
`FLOAT: fnRb = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
default: fnRb = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
default: fnRb = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [RBIT:0] fnRc;
|
function [RBIT:0] fnRc;
|
| Line 1540... |
Line 1755... |
`IVECTOR:
|
`IVECTOR:
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`VSxx,`VSxxS,`VSxxU,`VSxxSU: fnRc = {6'h3F,1'b1,2'b0,isn[18:16]};
|
`VSxx,`VSxxS,`VSxxU,`VSxxSU: fnRc = {6'h3F,1'b1,2'b0,isn[18:16]};
|
default: fnRc = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
default: fnRc = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
endcase
|
endcase
|
`FLOAT: fnRc = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
`FLOAT: fnRc = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
default: fnRc = {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
default: fnRc = {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [RBIT:0] fnRt;
|
function [RBIT:0] fnRt;
|
| Line 1576... |
Line 1791... |
case(isn[25:23])
|
case(isn[25:23])
|
3'd0: fnRt = {isn[22:18],1'b0,isn[`INSTRUCTION_RB]};
|
3'd0: fnRt = {isn[22:18],1'b0,isn[`INSTRUCTION_RB]};
|
3'd1: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd1: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd2: fnRt = {rs_stack[thrd][5:0],1'b0,isn[`INSTRUCTION_RB]};
|
3'd2: fnRt = {rs_stack[thrd][5:0],1'b0,isn[`INSTRUCTION_RB]};
|
3'd3: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd3: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd4: fnRt = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd4: fnRt = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd5: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd5: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd6: fnRt = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd6: fnRt = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
default:fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
default:fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
`VMOV:
|
`VMOV:
|
case (isn[`INSTRUCTION_S1])
|
case (isn[`INSTRUCTION_S1])
|
5'h0: fnRt = {6'h3F,1'b1,isn[`INSTRUCTION_RB]};
|
5'h0: fnRt = {6'h3F,1'b1,isn[`INSTRUCTION_RB]};
|
| Line 1620... |
Line 1835... |
`FLOAT:
|
`FLOAT:
|
case(isn[31:26])
|
case(isn[31:26])
|
`FTX,`FCX,`FEX,`FDX,`FRM:
|
`FTX,`FCX,`FEX,`FDX,`FRM:
|
fnRt = 12'd0;
|
fnRt = 12'd0;
|
`FSYNC: fnRt = 12'd0;
|
`FSYNC: fnRt = 12'd0;
|
default: fnRt = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
default: fnRt = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
endcase
|
endcase
|
`BRK: fnRt = 12'd0;
|
`BRK: fnRt = 12'd0;
|
`REX: fnRt = 12'd0;
|
`REX: fnRt = 12'd0;
|
`CHK: fnRt = 12'd0;
|
`CHK: fnRt = 12'd0;
|
`EXEC: fnRt = 12'd0;
|
`EXEC: fnRt = 12'd0;
|
| Line 1673... |
Line 1888... |
3'd0: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd0: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd1: fnRa = {isn[22:18],1'b0,isn[`INSTRUCTION_RA]};
|
3'd1: fnRa = {isn[22:18],1'b0,isn[`INSTRUCTION_RA]};
|
3'd2: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd2: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd3: fnRa = {rs_stack[5:0],1'b0,isn[`INSTRUCTION_RA]};
|
3'd3: fnRa = {rs_stack[5:0],1'b0,isn[`INSTRUCTION_RA]};
|
3'd4: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd4: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd5: fnRa = {fp_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd5: fnRa = {fp1_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd6: fnRa = {fp_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd6: fnRa = {fp1_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
default:fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
default:fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
`VMOV:
|
`VMOV:
|
case (isn[`INSTRUCTION_S1])
|
case (isn[`INSTRUCTION_S1])
|
5'h0: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
5'h0: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
5'h1: fnRa = {6'h3F,1'b1,isn[`INSTRUCTION_RA]};
|
5'h1: fnRa = {6'h3F,1'b1,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
default: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
default: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
`FLOAT: fnRa = {fp_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
`FLOAT: fnRa = {fp1_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
default: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
default: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [RBIT:0] fnRb;
|
function [RBIT:0] fnRb;
|
| Line 1719... |
Line 1934... |
fnRb = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
fnRb = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
`VSHL,`VSHR,`VASR:
|
`VSHL,`VSHR,`VASR:
|
fnRb = {isn[25],isn[22]}==2'b00 ? {rgs,1'b0,isn[`INSTRUCTION_RB]} : {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
fnRb = {isn[25],isn[22]}==2'b00 ? {rgs,1'b0,isn[`INSTRUCTION_RB]} : {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
default: fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
default: fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
`FLOAT: fnRb = {fp_rgs,1'b0,isn[`INSTRUCTION_RB]};
|
`FLOAT: fnRb = {fp1_rgs,1'b0,isn[`INSTRUCTION_RB]};
|
default: fnRb = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
default: fnRb = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [RBIT:0] fnRc;
|
function [RBIT:0] fnRc;
|
| Line 1742... |
Line 1957... |
`IVECTOR:
|
`IVECTOR:
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`VSxx,`VSxxS,`VSxxU,`VSxxSU: fnRc = {6'h3F,1'b1,2'b0,isn[18:16]};
|
`VSxx,`VSxxS,`VSxxU,`VSxxSU: fnRc = {6'h3F,1'b1,2'b0,isn[18:16]};
|
default: fnRc = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
default: fnRc = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
endcase
|
endcase
|
`FLOAT: fnRc = {fp_rgs,1'b0,isn[`INSTRUCTION_RC]};
|
`FLOAT: fnRc = {fp1_rgs,1'b0,isn[`INSTRUCTION_RC]};
|
default: fnRc = {rgs,1'b0,isn[`INSTRUCTION_RC]};
|
default: fnRc = {rgs,1'b0,isn[`INSTRUCTION_RC]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [RBIT:0] fnRt;
|
function [RBIT:0] fnRt;
|
| Line 1796... |
Line 2011... |
case(isn[25:23])
|
case(isn[25:23])
|
3'd0: fnRt = {isn[22:18],1'b0,isn[`INSTRUCTION_RB]};
|
3'd0: fnRt = {isn[22:18],1'b0,isn[`INSTRUCTION_RB]};
|
3'd1: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd1: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd2: fnRt = {rs_stack[5:0],1'b0,isn[`INSTRUCTION_RB]};
|
3'd2: fnRt = {rs_stack[5:0],1'b0,isn[`INSTRUCTION_RB]};
|
3'd3: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd3: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd4: fnRt = {fp_rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd4: fnRt = {fp1_rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd5: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd5: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd6: fnRt = {fp_rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd6: fnRt = {fp1_rgs,1'b0,isn[`INSTRUCTION_RB]};
|
default:fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
default:fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
`VMOV:
|
`VMOV:
|
case (isn[`INSTRUCTION_S1])
|
case (isn[`INSTRUCTION_S1])
|
5'h0: fnRt = {6'h3F,1'b1,isn[`INSTRUCTION_RB]};
|
5'h0: fnRt = {6'h3F,1'b1,isn[`INSTRUCTION_RB]};
|
| Line 1840... |
Line 2055... |
`FLOAT:
|
`FLOAT:
|
case(isn[31:26])
|
case(isn[31:26])
|
`FTX,`FCX,`FEX,`FDX,`FRM:
|
`FTX,`FCX,`FEX,`FDX,`FRM:
|
fnRt = 12'd0;
|
fnRt = 12'd0;
|
`FSYNC: fnRt = 12'd0;
|
`FSYNC: fnRt = 12'd0;
|
default: fnRt = {fp_rgs,1'b0,isn[`INSTRUCTION_RC]};
|
default: fnRt = {fp1_rgs,1'b0,isn[`INSTRUCTION_RC]};
|
endcase
|
endcase
|
`BRK: fnRt = 12'd0;
|
`BRK: fnRt = 12'd0;
|
`REX: fnRt = 12'd0;
|
`REX: fnRt = 12'd0;
|
`CHK: fnRt = 12'd0;
|
`CHK: fnRt = 12'd0;
|
`EXEC: fnRt = 12'd0;
|
`EXEC: fnRt = 12'd0;
|
| Line 2479... |
Line 2694... |
|
|
function IsFlowCtrl;
|
function IsFlowCtrl;
|
input [47:0] isn;
|
input [47:0] isn;
|
casez(isn[`INSTRUCTION_OP])
|
casez(isn[`INSTRUCTION_OP])
|
`BRK: IsFlowCtrl = TRUE;
|
`BRK: IsFlowCtrl = TRUE;
|
`RR: case(isn[`INSTRUCTION_S2])
|
`R2: case(isn[`INSTRUCTION_S2])
|
`RTI: IsFlowCtrl = TRUE;
|
`RTI: IsFlowCtrl = TRUE;
|
default: IsFlowCtrl = FALSE;
|
default: IsFlowCtrl = FALSE;
|
endcase
|
endcase
|
`Bcc: IsFlowCtrl = TRUE;
|
`Bcc: IsFlowCtrl = TRUE;
|
`BBc: IsFlowCtrl = TRUE;
|
`BBc: IsFlowCtrl = TRUE;
|
| Line 2537... |
Line 2752... |
function IsFSync;
|
function IsFSync;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsFSync = (isn[`INSTRUCTION_OP]==`FLOAT && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`FSYNC);
|
IsFSync = (isn[`INSTRUCTION_OP]==`FLOAT && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`FSYNC);
|
endfunction
|
endfunction
|
|
|
function IsMemdb;
|
|
input [47:0] isn;
|
|
IsMemdb = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`MEMDB);
|
|
endfunction
|
|
|
|
function IsMemsb;
|
function IsMemsb;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsMemsb = (isn[`INSTRUCTION_OP]==`RR && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`MEMSB);
|
IsMemsb = (isn[`INSTRUCTION_OP]==`RR && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`MEMSB);
|
endfunction
|
endfunction
|
|
|
| Line 2735... |
Line 2945... |
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [7:0] fnSelect;
|
function [7:0] fnSelect;
|
input [47:0] ins;
|
input [47:0] ins;
|
input [31:0] adr;
|
input [`ABITS] adr;
|
begin
|
begin
|
case(ins[`INSTRUCTION_OP])
|
case(ins[`INSTRUCTION_OP])
|
`MEMNDX:
|
`MEMNDX:
|
if (ins[`INSTRUCTION_L2]==2'b00)
|
if (ins[`INSTRUCTION_L2]==2'b00)
|
case(ins[`INSTRUCTION_S2])
|
case(ins[`INSTRUCTION_S2])
|
| Line 2905... |
Line 3115... |
endcase
|
endcase
|
endfunction
|
endfunction
|
*/
|
*/
|
function [63:0] fnDati;
|
function [63:0] fnDati;
|
input [47:0] ins;
|
input [47:0] ins;
|
input [31:0] adr;
|
input [`ABITS] adr;
|
input [63:0] dat;
|
input [63:0] dat;
|
case(ins[`INSTRUCTION_OP])
|
case(ins[`INSTRUCTION_OP])
|
`MEMNDX:
|
`MEMNDX:
|
if (ins[`INSTRUCTION_L2]==2'b00)
|
if (ins[`INSTRUCTION_L2]==2'b00)
|
case(ins[`INSTRUCTION_S2])
|
case(ins[`INSTRUCTION_S2])
|
| Line 3139... |
Line 3349... |
endcase
|
endcase
|
else
|
else
|
fnDato = dat;
|
fnDato = dat;
|
`SB: fnDato = {8{dat[7:0]}};
|
`SB: fnDato = {8{dat[7:0]}};
|
`Sx:
|
`Sx:
|
case(isn[20:18])
|
casez(isn[20:18])
|
3'b100: fnDato = dat;
|
3'b100: fnDato = dat;
|
3'b?10: fnDato = {2{dat[31:0]}};
|
3'b?10: fnDato = {2{dat[31:0]}};
|
3'b??1: fnDato = {4{dat[15:0]}};
|
3'b??1: fnDato = {4{dat[15:0]}};
|
default: fnDato = dat;
|
default: fnDato = dat;
|
endcase
|
endcase
|
| Line 3234... |
Line 3444... |
FT64_fetchbuf #(AMSB,RSTPC) ufb1
|
FT64_fetchbuf #(AMSB,RSTPC) ufb1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.clk4x(clk4x),
|
.clk4x(clk4x),
|
.clk(clk),
|
.clk(clk),
|
|
.fcu_clk(fcu_clk),
|
.cs_i(adr_o[31:16]==16'hFFFF),
|
.cs_i(adr_o[31:16]==16'hFFFF),
|
.cyc_i(cyc_o),
|
.cyc_i(cyc_o),
|
.stb_i(stb_o),
|
.stb_i(stb_o),
|
.ack_o(dc_ack),
|
.ack_o(dc_ack),
|
.we_i(we_o),
|
.we_i(we_o),
|
| Line 3294... |
Line 3505... |
.btgtC(btgtC),
|
.btgtC(btgtC),
|
.btgtD(btgtD),
|
.btgtD(btgtD),
|
.nop_fetchbuf(nop_fetchbuf),
|
.nop_fetchbuf(nop_fetchbuf),
|
.take_branch0(take_branch0),
|
.take_branch0(take_branch0),
|
.take_branch1(take_branch1),
|
.take_branch1(take_branch1),
|
.stompedRets(stompedOnRets)
|
.stompedRets(stompedOnRets),
|
|
.panic(fb_panic)
|
);
|
);
|
|
|
|
|
|
|
//initial begin: stop_at
|
//initial begin: stop_at
|
| Line 3714... |
Line 3926... |
generate begin : issue_logic
|
generate begin : issue_logic
|
for (g = 0; g < QENTRIES; g = g + 1)
|
for (g = 0; g < QENTRIES; g = g + 1)
|
begin
|
begin
|
assign args_valid[g] =
|
assign args_valid[g] =
|
(iqentry_a1_v[g]
|
(iqentry_a1_v[g]
|
|
`ifdef FU_BYPASS
|
|| (iqentry_a1_s[g] == alu0_sourceid && alu0_dataready)
|
|| (iqentry_a1_s[g] == alu0_sourceid && alu0_dataready)
|
|| (iqentry_a1_s[g] == alu1_sourceid && alu1_dataready))
|
|| ((iqentry_a1_s[g] == alu1_sourceid && alu1_dataready) && (`NUM_ALU > 1))
|
|
|| ((iqentry_a1_s[g] == fpu1_sourceid && fpu1_dataready) && (`NUM_FPU > 0))
|
|
`endif
|
|
)
|
&& (iqentry_a2_v[g]
|
&& (iqentry_a2_v[g]
|
|| (iqentry_mem[g] & ~iqentry_agen[g] & ~iqentry_memndx[g]) // a2 needs to be valid for indexed instruction
|
|| (iqentry_mem[g] & ~iqentry_agen[g] & ~iqentry_memndx[g]) // a2 needs to be valid for indexed instruction
|
|
`ifdef FU_BYPASS
|
|| (iqentry_a2_s[g] == alu0_sourceid && alu0_dataready)
|
|| (iqentry_a2_s[g] == alu0_sourceid && alu0_dataready)
|
|| (iqentry_a2_s[g] == alu1_sourceid && alu1_dataready))
|
|| ((iqentry_a2_s[g] == alu1_sourceid && alu1_dataready) && (`NUM_ALU > 1))
|
|
|| ((iqentry_a2_s[g] == fpu1_sourceid && fpu1_dataready) && (`NUM_FPU > 0))
|
|
`endif
|
|
)
|
&& (iqentry_a3_v[g]
|
&& (iqentry_a3_v[g]
|
// || (iqentry_mem[g] & ~iqentry_agen[g])
|
// || (iqentry_mem[g] & ~iqentry_agen[g])
|
|
`ifdef FU_BYPASS
|
|| (iqentry_a3_s[g] == alu0_sourceid && alu0_dataready)
|
|| (iqentry_a3_s[g] == alu0_sourceid && alu0_dataready)
|
|| (iqentry_a3_s[g] == alu1_sourceid && alu1_dataready))
|
|| ((iqentry_a3_s[g] == alu1_sourceid && alu1_dataready) && (`NUM_ALU > 1))
|
|
`endif
|
|
)
|
;
|
;
|
|
|
assign could_issue[g] = iqentry_v[g] && !iqentry_done[g] && !iqentry_out[g]
|
assign could_issue[g] = iqentry_v[g] && !iqentry_done[g] && !iqentry_out[g]
|
&& args_valid[g]
|
&& args_valid[g]
|
&& iqentry_iv[g]
|
&& iqentry_iv[g]
|
| Line 3759... |
Line 3982... |
assign heads[6] = head6;
|
assign heads[6] = head6;
|
assign heads[7] = head7;
|
assign heads[7] = head7;
|
|
|
always @*
|
always @*
|
begin
|
begin
|
iqentry_id1issue = 8'h00;
|
iqentry_id1issue = {QENTRIES{1'b0}};
|
iqentry_id2issue = 8'h00;
|
|
|
|
// aluissue is a task
|
|
if (id1_available) begin
|
if (id1_available) begin
|
for (n = 0; n < QENTRIES; n = n + 1)
|
for (n = 0; n < QENTRIES; n = n + 1)
|
if (could_issueid[heads[n]] && iqentry_id1issue==8'h00)
|
if (could_issueid[heads[n]] && iqentry_id1issue=={QENTRIES{1'b0}})
|
iqentry_id1issue[heads[n]] = `TRUE;
|
iqentry_id1issue[heads[n]] = `TRUE;
|
end
|
end
|
|
end
|
|
generate begin : gIDUIssue
|
|
if (`NUM_IDU > 1) begin
|
|
always @*
|
|
begin
|
|
iqentry_id2issue = {QENTRIES{1'b0}};
|
if (id2_available) begin
|
if (id2_available) begin
|
for (n = 0; n < QENTRIES; n = n + 1)
|
for (n = 0; n < QENTRIES; n = n + 1)
|
if (could_issueid[heads[n]] && !iqentry_id1issue[heads[n]] && iqentry_id2issue==8'h00)
|
if (could_issueid[heads[n]] && !iqentry_id1issue[heads[n]] && iqentry_id2issue=={QENTRIES{1'b0}})
|
iqentry_id2issue[heads[n]] = `TRUE;
|
iqentry_id2issue[heads[n]] = `TRUE;
|
end
|
end
|
end
|
end
|
|
end
|
|
if (`NUM_IDU > 2) begin
|
|
always @*
|
|
begin
|
|
iqentry_id3issue = {QENTRIES{1'b0}};
|
|
if (id3_available) begin
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
|
if (could_issueid[heads[n]]
|
|
&& !iqentry_id1issue[heads[n]]
|
|
&& !iqentry_id2issue[heads[n]]
|
|
&& iqentry_id3issue=={QENTRIES{1'b0}})
|
|
iqentry_id3issue[heads[n]] = `TRUE;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
endgenerate
|
|
|
always @*
|
always @*
|
begin
|
begin
|
iqentry_alu0_issue = 8'h00;
|
iqentry_alu0_issue = {QENTRIES{1'b0}};
|
iqentry_alu1_issue = 8'h00;
|
iqentry_alu1_issue = {QENTRIES{1'b0}};
|
|
|
// aluissue is a task
|
|
// aluissue is a task
|
|
if (alu0_available & alu0_idle) begin
|
if (alu0_available & alu0_idle) begin
|
if (could_issue[head0] && iqentry_alu[head0]) begin
|
if (could_issue[head0] && iqentry_alu[head0]) begin
|
iqentry_alu0_issue[head0] = `TRUE;
|
iqentry_alu0_issue[head0] = `TRUE;
|
end
|
end
|
else if (could_issue[head1] && iqentry_alu[head1])
|
else if (could_issue[head1] && iqentry_alu[head1])
|
| Line 3906... |
Line 4146... |
iqentry_alu0_issue[head7] = `TRUE;
|
iqentry_alu0_issue[head7] = `TRUE;
|
end
|
end
|
`endif
|
`endif
|
end
|
end
|
|
|
if (alu1_available & alu1_idle) begin
|
if (alu1_available && alu1_idle && `NUM_ALU > 1) begin
|
if ((could_issue & ~iqentry_alu0_issue & ~iqentry_alu0) != 8'h00) begin
|
if ((could_issue & ~iqentry_alu0_issue & ~iqentry_alu0) != 8'h00) begin
|
if (could_issue[head0] && iqentry_alu[head0]
|
if (could_issue[head0] && iqentry_alu[head0]
|
&& !iqentry_alu0[head0] // alu0only
|
&& !iqentry_alu0[head0] // alu0only
|
&& !iqentry_alu0_issue[head0]) begin
|
&& !iqentry_alu0_issue[head0]) begin
|
iqentry_alu1_issue[head0] = `TRUE;
|
iqentry_alu1_issue[head0] = `TRUE;
|
| Line 4045... |
Line 4285... |
end
|
end
|
end
|
end
|
|
|
always @*
|
always @*
|
begin
|
begin
|
iqentry_fpu_issue = 8'h00;
|
iqentry_fpu1_issue = {QENTRIES{1'b0}};
|
// fpuissue(fpu_idle,2'b00);
|
// fpu1issue(fpu1_idle,2'b00);
|
if (fpu_idle) begin
|
if (fpu1_idle && `NUM_FPU > 0) begin
|
if (could_issue[head0] && iqentry_fpu[head0]) begin
|
if (could_issue[head0] && iqentry_fpu[head0]) begin
|
iqentry_fpu_issue[head0] = `TRUE;
|
iqentry_fpu1_issue[head0] = `TRUE;
|
iqentry_fpu_islot[head0] = 2'b00;
|
|
end
|
end
|
else if (could_issue[head1] && iqentry_fpu[head1])
|
else if (could_issue[head1] && iqentry_fpu[head1])
|
begin
|
begin
|
iqentry_fpu_issue[head1] = `TRUE;
|
iqentry_fpu1_issue[head1] = `TRUE;
|
iqentry_fpu_islot[head1] = 2'b00;
|
|
end
|
end
|
else if (could_issue[head2] && iqentry_fpu[head2]
|
else if (could_issue[head2] && iqentry_fpu[head2]
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
) begin
|
) begin
|
iqentry_fpu_issue[head2] = `TRUE;
|
iqentry_fpu1_issue[head2] = `TRUE;
|
iqentry_fpu_islot[head2] = 2'b00;
|
|
end
|
end
|
else if (could_issue[head3] && iqentry_fpu[head3]
|
else if (could_issue[head3] && iqentry_fpu[head3]
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
((!iqentry_v[head0])
|
((!iqentry_v[head0])
|
&& (!iqentry_v[head1]))
|
&& (!iqentry_v[head1]))
|
)
|
)
|
) begin
|
) begin
|
iqentry_fpu_issue[head3] = `TRUE;
|
iqentry_fpu1_issue[head3] = `TRUE;
|
iqentry_fpu_islot[head3] = 2'b00;
|
|
end
|
end
|
else if (could_issue[head4] && iqentry_fpu[head4]
|
else if (could_issue[head4] && iqentry_fpu[head4]
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
((!iqentry_v[head0])
|
((!iqentry_v[head0])
|
| Line 4085... |
Line 4321... |
((!iqentry_v[head0])
|
((!iqentry_v[head0])
|
&& (!iqentry_v[head1])
|
&& (!iqentry_v[head1])
|
&& (!iqentry_v[head2]))
|
&& (!iqentry_v[head2]))
|
)
|
)
|
) begin
|
) begin
|
iqentry_fpu_issue[head4] = `TRUE;
|
iqentry_fpu1_issue[head4] = `TRUE;
|
iqentry_fpu_islot[head4] = 2'b00;
|
|
end
|
end
|
else if (could_issue[head5] && iqentry_fpu[head5]
|
else if (could_issue[head5] && iqentry_fpu[head5]
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
((!iqentry_v[head0])
|
((!iqentry_v[head0])
|
| Line 4106... |
Line 4341... |
&& (!iqentry_v[head1])
|
&& (!iqentry_v[head1])
|
&& (!iqentry_v[head2])
|
&& (!iqentry_v[head2])
|
&& (!iqentry_v[head3]))
|
&& (!iqentry_v[head3]))
|
)
|
)
|
) begin
|
) begin
|
iqentry_fpu_issue[head5] = `TRUE;
|
iqentry_fpu1_issue[head5] = `TRUE;
|
iqentry_fpu_islot[head5] = 2'b00;
|
|
end
|
end
|
`ifdef FULL_ISSUE_LOGIC
|
`ifdef FULL_ISSUE_LOGIC
|
else if (could_issue[head6] && iqentry_fpu[head6]
|
else if (could_issue[head6] && iqentry_fpu[head6]
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
| Line 4135... |
Line 4369... |
&& (!iqentry_v[head2])
|
&& (!iqentry_v[head2])
|
&& (!iqentry_v[head3])
|
&& (!iqentry_v[head3])
|
&& (!iqentry_v[head4]))
|
&& (!iqentry_v[head4]))
|
)
|
)
|
) begin
|
) begin
|
iqentry_fpu_issue[head6] = `TRUE;
|
iqentry_fpu1_issue[head6] = `TRUE;
|
iqentry_fpu_islot[head6] = 2'b00;
|
|
end
|
end
|
else if (could_issue[head7] && iqentry_fpu[head7]
|
else if (could_issue[head7] && iqentry_fpu[head7]
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
((!iqentry_v[head0])
|
((!iqentry_v[head0])
|
| Line 4172... |
Line 4405... |
&& (!iqentry_v[head4])
|
&& (!iqentry_v[head4])
|
&& (!iqentry_v[head5]))
|
&& (!iqentry_v[head5]))
|
)
|
)
|
)
|
)
|
begin
|
begin
|
iqentry_fpu_issue[head7] = `TRUE;
|
iqentry_fpu1_issue[head7] = `TRUE;
|
iqentry_fpu_islot[head7] = 2'b00;
|
|
end
|
end
|
`endif
|
`endif
|
end
|
end
|
end
|
end
|
|
|
|
always @*
|
|
begin
|
|
iqentry_fpu2_issue = {QENTRIES{1'b0}};
|
|
// fpu2issue(fpu2_idle,2'b00);
|
|
if (fpu2_idle && `NUM_FPU > 1) begin
|
|
if (could_issue[head0] && iqentry_fpu[head0] && !iqentry_fpu1_issue[head0]) begin
|
|
iqentry_fpu2_issue[head0] = `TRUE;
|
|
end
|
|
else if (could_issue[head1] && iqentry_fpu[head1] && !iqentry_fpu1_issue[head1])
|
|
begin
|
|
iqentry_fpu2_issue[head1] = `TRUE;
|
|
end
|
|
else if (could_issue[head2] && iqentry_fpu[head2] && !iqentry_fpu1_issue[head2]
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
|
) begin
|
|
iqentry_fpu2_issue[head2] = `TRUE;
|
|
end
|
|
else if (could_issue[head3] && iqentry_fpu[head3] && !iqentry_fpu1_issue[head3]
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
) begin
|
|
iqentry_fpu2_issue[head3] = `TRUE;
|
|
end
|
|
else if (could_issue[head4] && iqentry_fpu[head4] && !iqentry_fpu1_issue[head4]
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_v[head3] && (iqentry_sync[head3] || iqentry_fsync[head3])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2]))
|
|
)
|
|
) begin
|
|
iqentry_fpu2_issue[head4] = `TRUE;
|
|
end
|
|
else if (could_issue[head5] && iqentry_fpu[head5] && !iqentry_fpu1_issue[head5]
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_v[head3] && (iqentry_sync[head3] || iqentry_fsync[head3])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2]))
|
|
)
|
|
&& (!(iqentry_v[head4] && (iqentry_sync[head4] || iqentry_fsync[head4])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3]))
|
|
)
|
|
) begin
|
|
iqentry_fpu2_issue[head5] = `TRUE;
|
|
end
|
|
`ifdef FULL_ISSUE_LOGIC
|
|
else if (could_issue[head6] && iqentry_fpu[head6] && !iqentry_fpu1_issue[head6]
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_v[head3] && (iqentry_sync[head3] || iqentry_fsync[head3])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2]))
|
|
)
|
|
&& (!(iqentry_v[head4] && (iqentry_sync[head4] || iqentry_fsync[head4])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3]))
|
|
)
|
|
&& (!(iqentry_v[head5] && (iqentry_sync[head5] || iqentry_fsync[head5])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4]))
|
|
)
|
|
) begin
|
|
iqentry_fpu2_issue[head6] = `TRUE;
|
|
end
|
|
else if (could_issue[head7] && iqentry_fpu[head7] && !iqentry_fpu1_issue[head7]
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_v[head3] && (iqentry_sync[head3] || iqentry_fsync[head3])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2]))
|
|
)
|
|
&& (!(iqentry_v[head4] && (iqentry_sync[head4] || iqentry_fsync[head4])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3]))
|
|
)
|
|
&& (!(iqentry_v[head5] && (iqentry_sync[head5] || iqentry_fsync[head5])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4]))
|
|
)
|
|
&& (!(iqentry_v[head6] && (iqentry_sync[head6] || iqentry_fsync[head6])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4])
|
|
&& (!iqentry_v[head5]))
|
|
)
|
|
)
|
|
begin
|
|
iqentry_fpu2_issue[head7] = `TRUE;
|
|
end
|
|
`endif
|
|
end
|
|
end
|
|
|
wire [QENTRIES-1:0] nextqd;
|
wire [QENTRIES-1:0] nextqd;
|
// Next queue id
|
// Next queue id
|
|
|
reg [`QBITS] nid0;
|
reg [`QBITS] nid0;
|
| Line 4371... |
Line 4730... |
|
|
// Don't issue to the fcu until the following instruction is enqueued.
|
// Don't issue to the fcu until the following instruction is enqueued.
|
// However, if the queue is full then issue anyway. A branch miss will likely occur.
|
// However, if the queue is full then issue anyway. A branch miss will likely occur.
|
always @*//(could_issue or head0 or head1 or head2 or head3 or head4 or head5 or head6 or head7)
|
always @*//(could_issue or head0 or head1 or head2 or head3 or head4 or head5 or head6 or head7)
|
begin
|
begin
|
iqentry_fcu_issue = 8'h00;
|
iqentry_fcu_issue = {QENTRIES{1'b0}};
|
if (fcu_done) begin
|
if (fcu_done) begin
|
if (could_issue[head0] && iqentry_fc[head0] && nextqd[head0]) begin
|
if (could_issue[head0] && iqentry_fc[head0] && nextqd[head0]) begin
|
iqentry_fcu_issue[head0] = `TRUE;
|
iqentry_fcu_issue[head0] = `TRUE;
|
end
|
end
|
else if (could_issue[head1] && iqentry_fc[head1] && nextqd[head1])
|
else if (could_issue[head1] && iqentry_fc[head1] && nextqd[head1])
|
| Line 4509... |
Line 4868... |
memissue[ head0 ] = iqentry_memready[ head0 ]; // first in line ... go as soon as ready
|
memissue[ head0 ] = iqentry_memready[ head0 ]; // first in line ... go as soon as ready
|
if (memissue[head0])
|
if (memissue[head0])
|
issue_count = issue_count + 1;
|
issue_count = issue_count + 1;
|
|
|
memissue[ head1 ] = ~iqentry_stomp[head1] && iqentry_memready[ head1 ] // addr and data are valid
|
memissue[ head1 ] = ~iqentry_stomp[head1] && iqentry_memready[ head1 ] // addr and data are valid
|
|
&& issue_count < `NUM_MEM
|
// ... and no preceding instruction is ready to go
|
// ... and no preceding instruction is ready to go
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head0]
|
// ... and there is no address-overlap with any preceding instruction
|
// ... and there is no address-overlap with any preceding instruction
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
|| (iqentry_a1_v[head0] && iqentry_a1[head1] != iqentry_a1[head0]))
|
|| (iqentry_a1_v[head0] && iqentry_a1[head1][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
// ... if a release, any prior memory ops must be done before this one
|
// ... if a release, any prior memory ops must be done before this one
|
&& (iqentry_rl[head1] ? iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0] : 1'b1)
|
&& (iqentry_rl[head1] ? iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0] : 1'b1)
|
// ... if a preivous op has the aquire bit set
|
// ... if a preivous op has the aquire bit set
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
// ... and, if it is a SW, there is no chance of it being undone
|
// ... and, if it is a SW, there is no chance of it being undone
|
| Line 4526... |
Line 4886... |
if (memissue[head1])
|
if (memissue[head1])
|
issue_count = issue_count + 1;
|
issue_count = issue_count + 1;
|
|
|
memissue[ head2 ] = ~iqentry_stomp[head2] && iqentry_memready[ head2 ] // addr and data are valid
|
memissue[ head2 ] = ~iqentry_stomp[head2] && iqentry_memready[ head2 ] // addr and data are valid
|
// ... and no preceding instruction is ready to go
|
// ... and no preceding instruction is ready to go
|
|
&& issue_count < `NUM_MEM
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head1]
|
// ... and there is no address-overlap with any preceding instruction
|
// ... and there is no address-overlap with any preceding instruction
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
|| (iqentry_a1_v[head0] && iqentry_a1[head2] != iqentry_a1[head0]))
|
|| (iqentry_a1_v[head0] && iqentry_a1[head2][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
|| (iqentry_a1_v[head1] && iqentry_a1[head2] != iqentry_a1[head1]))
|
|| (iqentry_a1_v[head1] && iqentry_a1[head2][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
// ... if a release, any prior memory ops must be done before this one
|
// ... if a release, any prior memory ops must be done before this one
|
&& (iqentry_rl[head2] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_rl[head2] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
: 1'b1)
|
: 1'b1)
|
// ... if a preivous op has the aquire bit set
|
// ... if a preivous op has the aquire bit set
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
&& !(iqentry_aq[head1] && iqentry_v[head1])
|
&& !(iqentry_aq[head1] && iqentry_v[head1])
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
&& (!(iqentry_v[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_iv[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_v[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_iv[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
// ... and, if it is a SW, there is no chance of it being undone
|
// ... and, if it is a SW, there is no chance of it being undone
|
&& (iqentry_load[head2] ||
|
&& (iqentry_load[head2] ||
|
!(iqentry_fc[head0]||iqentry_canex[head0])
|
!(iqentry_fc[head0]||iqentry_canex[head0])
|
&& !(iqentry_fc[head1]||iqentry_canex[head1]));
|
&& !(iqentry_fc[head1]||iqentry_canex[head1]));
|
if (memissue[head2])
|
if (memissue[head2])
|
issue_count = issue_count + 1;
|
issue_count = issue_count + 1;
|
|
|
memissue[ head3 ] = ~iqentry_stomp[head3] && iqentry_memready[ head3 ] // addr and data are valid
|
memissue[ head3 ] = ~iqentry_stomp[head3] && iqentry_memready[ head3 ] // addr and data are valid
|
// ... and no preceding instruction is ready to go
|
// ... and no preceding instruction is ready to go
|
&& issue_count < 3
|
&& issue_count < `NUM_MEM
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head2]
|
//&& ~iqentry_memready[head2]
|
// ... and there is no address-overlap with any preceding instruction
|
// ... and there is no address-overlap with any preceding instruction
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
|| (iqentry_a1_v[head0] && iqentry_a1[head3] != iqentry_a1[head0]))
|
|| (iqentry_a1_v[head0] && iqentry_a1[head3][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
|| (iqentry_a1_v[head1] && iqentry_a1[head3] != iqentry_a1[head1]))
|
|| (iqentry_a1_v[head1] && iqentry_a1[head3][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
|| (iqentry_a1_v[head2] && iqentry_a1[head3] != iqentry_a1[head2]))
|
|| (iqentry_a1_v[head2] && iqentry_a1[head3][AMSB:3] != iqentry_a1[head2][AMSB:3]))
|
// ... if a release, any prior memory ops must be done before this one
|
// ... if a release, any prior memory ops must be done before this one
|
&& (iqentry_rl[head3] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_rl[head3] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
: 1'b1)
|
: 1'b1)
|
// ... if a preivous op has the aquire bit set
|
// ... if a preivous op has the aquire bit set
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
&& !(iqentry_aq[head1] && iqentry_v[head1])
|
&& !(iqentry_aq[head1] && iqentry_v[head1])
|
&& !(iqentry_aq[head2] && iqentry_v[head2])
|
&& !(iqentry_aq[head2] && iqentry_v[head2])
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
&& (!(iqentry_v[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_iv[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_v[head2] && iqentry_memsb[head2]) ||
|
&& (!(iqentry_iv[head2] && iqentry_memsb[head2]) ||
|
((iqentry_done[head0] || !iqentry_v[head0])
|
((iqentry_done[head0] || !iqentry_v[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1]))
|
&& (iqentry_done[head1] || !iqentry_v[head1]))
|
)
|
)
|
&& (!(iqentry_v[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_iv[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_v[head2] && iqentry_memdb[head2]) ||
|
&& (!(iqentry_iv[head2] && iqentry_memdb[head2]) ||
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]))
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]))
|
)
|
)
|
// ... and, if it is a SW, there is no chance of it being undone
|
// ... and, if it is a SW, there is no chance of it being undone
|
&& (iqentry_load[head3] ||
|
&& (iqentry_load[head3] ||
|
| Line 4593... |
Line 4954... |
if (memissue[head3])
|
if (memissue[head3])
|
issue_count = issue_count + 1;
|
issue_count = issue_count + 1;
|
|
|
memissue[ head4 ] = ~iqentry_stomp[head4] && iqentry_memready[ head4 ] // addr and data are valid
|
memissue[ head4 ] = ~iqentry_stomp[head4] && iqentry_memready[ head4 ] // addr and data are valid
|
// ... and no preceding instruction is ready to go
|
// ... and no preceding instruction is ready to go
|
&& issue_count < 3
|
&& issue_count < `NUM_MEM
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head2]
|
//&& ~iqentry_memready[head2]
|
//&& ~iqentry_memready[head3]
|
//&& ~iqentry_memready[head3]
|
// ... and there is no address-overlap with any preceding instruction
|
// ... and there is no address-overlap with any preceding instruction
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
|| (iqentry_a1_v[head0] && iqentry_a1[head4] != iqentry_a1[head0]))
|
|| (iqentry_a1_v[head0] && iqentry_a1[head4][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
|| (iqentry_a1_v[head1] && iqentry_a1[head4] != iqentry_a1[head1]))
|
|| (iqentry_a1_v[head1] && iqentry_a1[head4][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
|| (iqentry_a1_v[head2] && iqentry_a1[head4] != iqentry_a1[head2]))
|
|| (iqentry_a1_v[head2] && iqentry_a1[head4][AMSB:3] != iqentry_a1[head2][AMSB:3]))
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|
|| (iqentry_a1_v[head3] && iqentry_a1[head4] != iqentry_a1[head3]))
|
|| (iqentry_a1_v[head3] && iqentry_a1[head4][AMSB:3] != iqentry_a1[head3][AMSB:3]))
|
// ... if a release, any prior memory ops must be done before this one
|
// ... if a release, any prior memory ops must be done before this one
|
&& (iqentry_rl[head4] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_rl[head4] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
| Line 4619... |
Line 4980... |
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
&& !(iqentry_aq[head1] && iqentry_v[head1])
|
&& !(iqentry_aq[head1] && iqentry_v[head1])
|
&& !(iqentry_aq[head2] && iqentry_v[head2])
|
&& !(iqentry_aq[head2] && iqentry_v[head2])
|
&& !(iqentry_aq[head3] && iqentry_v[head3])
|
&& !(iqentry_aq[head3] && iqentry_v[head3])
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
&& (!(iqentry_v[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_iv[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_v[head2] && iqentry_memsb[head2]) ||
|
&& (!(iqentry_iv[head2] && iqentry_memsb[head2]) ||
|
((iqentry_done[head0] || !iqentry_v[head0])
|
((iqentry_done[head0] || !iqentry_v[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1]))
|
&& (iqentry_done[head1] || !iqentry_v[head1]))
|
)
|
)
|
&& (!(iqentry_v[head3] && iqentry_memsb[head3]) ||
|
&& (!(iqentry_iv[head3] && iqentry_memsb[head3]) ||
|
((iqentry_done[head0] || !iqentry_v[head0])
|
((iqentry_done[head0] || !iqentry_v[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2]))
|
&& (iqentry_done[head2] || !iqentry_v[head2]))
|
)
|
)
|
&& (!(iqentry_v[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_v[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_v[head2] && iqentry_memdb[head2]) ||
|
&& (!(iqentry_iv[head2] && iqentry_memdb[head2]) ||
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]))
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]))
|
)
|
)
|
&& (!(iqentry_v[head3] && iqentry_memdb[head3]) ||
|
&& (!(iqentry_iv[head3] && iqentry_memdb[head3]) ||
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]))
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]))
|
)
|
)
|
// ... and, if it is a SW, there is no chance of it being undone
|
// ... and, if it is a SW, there is no chance of it being undone
|
| Line 4650... |
Line 5011... |
if (memissue[head4])
|
if (memissue[head4])
|
issue_count = issue_count + 1;
|
issue_count = issue_count + 1;
|
|
|
memissue[ head5 ] = ~iqentry_stomp[head5] && iqentry_memready[ head5 ] // addr and data are valid
|
memissue[ head5 ] = ~iqentry_stomp[head5] && iqentry_memready[ head5 ] // addr and data are valid
|
// ... and no preceding instruction is ready to go
|
// ... and no preceding instruction is ready to go
|
&& issue_count < 3
|
&& issue_count < `NUM_MEM
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head2]
|
//&& ~iqentry_memready[head2]
|
//&& ~iqentry_memready[head3]
|
//&& ~iqentry_memready[head3]
|
//&& ~iqentry_memready[head4]
|
//&& ~iqentry_memready[head4]
|
// ... and there is no address-overlap with any preceding instruction
|
// ... and there is no address-overlap with any preceding instruction
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
|| (iqentry_a1_v[head0] && iqentry_a1[head5] != iqentry_a1[head0]))
|
|| (iqentry_a1_v[head0] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
|| (iqentry_a1_v[head1] && iqentry_a1[head5] != iqentry_a1[head1]))
|
|| (iqentry_a1_v[head1] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
|| (iqentry_a1_v[head2] && iqentry_a1[head5] != iqentry_a1[head2]))
|
|| (iqentry_a1_v[head2] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head2][AMSB:3]))
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|
|| (iqentry_a1_v[head3] && iqentry_a1[head5] != iqentry_a1[head3]))
|
|| (iqentry_a1_v[head3] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head3][AMSB:3]))
|
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4])
|
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4])
|
|| (iqentry_a1_v[head4] && iqentry_a1[head5] != iqentry_a1[head4]))
|
|| (iqentry_a1_v[head4] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head4][AMSB:3]))
|
// ... if a release, any prior memory ops must be done before this one
|
// ... if a release, any prior memory ops must be done before this one
|
&& (iqentry_rl[head5] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_rl[head5] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
| Line 4681... |
Line 5042... |
&& !(iqentry_aq[head1] && iqentry_v[head1])
|
&& !(iqentry_aq[head1] && iqentry_v[head1])
|
&& !(iqentry_aq[head2] && iqentry_v[head2])
|
&& !(iqentry_aq[head2] && iqentry_v[head2])
|
&& !(iqentry_aq[head3] && iqentry_v[head3])
|
&& !(iqentry_aq[head3] && iqentry_v[head3])
|
&& !(iqentry_aq[head4] && iqentry_v[head4])
|
&& !(iqentry_aq[head4] && iqentry_v[head4])
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
&& (!(iqentry_v[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_iv[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_v[head2] && iqentry_memsb[head2]) ||
|
&& (!(iqentry_iv[head2] && iqentry_memsb[head2]) ||
|
((iqentry_done[head0] || !iqentry_v[head0])
|
((iqentry_done[head0] || !iqentry_v[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1]))
|
&& (iqentry_done[head1] || !iqentry_v[head1]))
|
)
|
)
|
&& (!(iqentry_v[head3] && iqentry_memsb[head3]) ||
|
&& (!(iqentry_iv[head3] && iqentry_memsb[head3]) ||
|
((iqentry_done[head0] || !iqentry_v[head0])
|
((iqentry_done[head0] || !iqentry_v[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2]))
|
&& (iqentry_done[head2] || !iqentry_v[head2]))
|
)
|
)
|
&& (!(iqentry_v[head4] && iqentry_memsb[head4]) ||
|
&& (!(iqentry_iv[head4] && iqentry_memsb[head4]) ||
|
((iqentry_done[head0] || !iqentry_v[head0])
|
((iqentry_done[head0] || !iqentry_v[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
&& (iqentry_done[head3] || !iqentry_v[head3]))
|
&& (iqentry_done[head3] || !iqentry_v[head3]))
|
)
|
)
|
&& (!(iqentry_v[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_iv[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_v[head2] && iqentry_memdb[head2]) ||
|
&& (!(iqentry_iv[head2] && iqentry_memdb[head2]) ||
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]))
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]))
|
)
|
)
|
&& (!(iqentry_v[head3] && iqentry_memdb[head3]) ||
|
&& (!(iqentry_iv[head3] && iqentry_memdb[head3]) ||
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]))
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]))
|
)
|
)
|
&& (!(iqentry_v[head4] && iqentry_memdb[head4]) ||
|
&& (!(iqentry_iv[head4] && iqentry_memdb[head4]) ||
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]))
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]))
|
)
|
)
|
| Line 4726... |
Line 5087... |
issue_count = issue_count + 1;
|
issue_count = issue_count + 1;
|
|
|
`ifdef FULL_ISSUE_LOGIC
|
`ifdef FULL_ISSUE_LOGIC
|
memissue[ head6 ] = ~iqentry_stomp[head6] && iqentry_memready[ head6 ] // addr and data are valid
|
memissue[ head6 ] = ~iqentry_stomp[head6] && iqentry_memready[ head6 ] // addr and data are valid
|
// ... and no preceding instruction is ready to go
|
// ... and no preceding instruction is ready to go
|
&& issue_count < 3
|
&& issue_count < `NUM_MEM
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head2]
|
//&& ~iqentry_memready[head2]
|
//&& ~iqentry_memready[head3]
|
//&& ~iqentry_memready[head3]
|
//&& ~iqentry_memready[head4]
|
//&& ~iqentry_memready[head4]
|
//&& ~iqentry_memready[head5]
|
//&& ~iqentry_memready[head5]
|
// ... and there is no address-overlap with any preceding instruction
|
// ... and there is no address-overlap with any preceding instruction
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
|| (iqentry_a1_v[head0] && iqentry_a1[head6] != iqentry_a1[head0]))
|
|| (iqentry_a1_v[head0] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
|| (iqentry_a1_v[head1] && iqentry_a1[head6] != iqentry_a1[head1]))
|
|| (iqentry_a1_v[head1] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
|| (iqentry_a1_v[head2] && iqentry_a1[head6] != iqentry_a1[head2]))
|
|| (iqentry_a1_v[head2] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head2][AMSB:3]))
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|
|| (iqentry_a1_v[head3] && iqentry_a1[head6] != iqentry_a1[head3]))
|
|| (iqentry_a1_v[head3] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head3][AMSB:3]))
|
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4])
|
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4])
|
|| (iqentry_a1_v[head4] && iqentry_a1[head6] != iqentry_a1[head4]))
|
|| (iqentry_a1_v[head4] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head4][AMSB:3]))
|
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5])
|
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5])
|
|| (iqentry_a1_v[head5] && iqentry_a1[head6] != iqentry_a1[head5]))
|
|| (iqentry_a1_v[head5] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head5][AMSB:3]))
|
&& (iqentry_rl[head6] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_rl[head6] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
&& (iqentry_done[head4] || !iqentry_v[head4] || !iqentry_mem[head4])
|
&& (iqentry_done[head4] || !iqentry_v[head4] || !iqentry_mem[head4])
|
| Line 4761... |
Line 5122... |
&& !(iqentry_aq[head2] && iqentry_v[head2])
|
&& !(iqentry_aq[head2] && iqentry_v[head2])
|
&& !(iqentry_aq[head3] && iqentry_v[head3])
|
&& !(iqentry_aq[head3] && iqentry_v[head3])
|
&& !(iqentry_aq[head4] && iqentry_v[head4])
|
&& !(iqentry_aq[head4] && iqentry_v[head4])
|
&& !(iqentry_aq[head5] && iqentry_v[head5])
|
&& !(iqentry_aq[head5] && iqentry_v[head5])
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
&& (!(iqentry_v[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_iv[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_v[head2] && iqentry_memsb[head2]) ||
|
&& (!(iqentry_iv[head2] && iqentry_memsb[head2]) ||
|
((iqentry_done[head0] || !iqentry_v[head0])
|
((iqentry_done[head0] || !iqentry_v[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1]))
|
&& (iqentry_done[head1] || !iqentry_v[head1]))
|
)
|
)
|
&& (!(iqentry_v[head3] && iqentry_memsb[head3]) ||
|
&& (!(iqentry_iv[head3] && iqentry_memsb[head3]) ||
|
((iqentry_done[head0] || !iqentry_v[head0])
|
((iqentry_done[head0] || !iqentry_v[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2]))
|
&& (iqentry_done[head2] || !iqentry_v[head2]))
|
)
|
)
|
&& (!(iqentry_v[head4] && iqentry_memsb[head4]) ||
|
&& (!(iqentry_iv[head4] && iqentry_memsb[head4]) ||
|
((iqentry_done[head0] || !iqentry_v[head0])
|
((iqentry_done[head0] || !iqentry_v[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
&& (iqentry_done[head3] || !iqentry_v[head3]))
|
&& (iqentry_done[head3] || !iqentry_v[head3]))
|
)
|
)
|
&& (!(iqentry_v[head5] && iqentry_memsb[head5]) ||
|
&& (!(iqentry_iv[head5] && iqentry_memsb[head5]) ||
|
((iqentry_done[head0] || !iqentry_v[head0])
|
((iqentry_done[head0] || !iqentry_v[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
&& (iqentry_done[head3] || !iqentry_v[head3])
|
&& (iqentry_done[head3] || !iqentry_v[head3])
|
&& (iqentry_done[head4] || !iqentry_v[head4]))
|
&& (iqentry_done[head4] || !iqentry_v[head4]))
|
)
|
)
|
&& (!(iqentry_v[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_iv[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_v[head2] && iqentry_memdb[head2]) ||
|
&& (!(iqentry_iv[head2] && iqentry_memdb[head2]) ||
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]))
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]))
|
)
|
)
|
&& (!(iqentry_v[head3] && iqentry_memdb[head3]) ||
|
&& (!(iqentry_iv[head3] && iqentry_memdb[head3]) ||
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]))
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]))
|
)
|
)
|
&& (!(iqentry_v[head4] && iqentry_memdb[head4]) ||
|
&& (!(iqentry_iv[head4] && iqentry_memdb[head4]) ||
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]))
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]))
|
)
|
)
|
&& (!(iqentry_v[head5] && iqentry_memdb[head5]) ||
|
&& (!(iqentry_iv[head5] && iqentry_memdb[head5]) ||
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])
|
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4]))
|
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4]))
|
| Line 4820... |
Line 5181... |
if (memissue[head6])
|
if (memissue[head6])
|
issue_count = issue_count + 1;
|
issue_count = issue_count + 1;
|
|
|
memissue[ head7 ] = ~iqentry_stomp[head7] && iqentry_memready[ head7 ] // addr and data are valid
|
memissue[ head7 ] = ~iqentry_stomp[head7] && iqentry_memready[ head7 ] // addr and data are valid
|
// ... and no preceding instruction is ready to go
|
// ... and no preceding instruction is ready to go
|
&& issue_count < 3
|
&& issue_count < `NUM_MEM
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head2]
|
//&& ~iqentry_memready[head2]
|
//&& ~iqentry_memready[head3]
|
//&& ~iqentry_memready[head3]
|
//&& ~iqentry_memready[head4]
|
//&& ~iqentry_memready[head4]
|
//&& ~iqentry_memready[head5]
|
//&& ~iqentry_memready[head5]
|
//&& ~iqentry_memready[head6]
|
//&& ~iqentry_memready[head6]
|
// ... and there is no address-overlap with any preceding instruction
|
// ... and there is no address-overlap with any preceding instruction
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
|| (iqentry_a1_v[head0] && iqentry_a1[head7] != iqentry_a1[head0]))
|
|| (iqentry_a1_v[head0] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
|| (iqentry_a1_v[head1] && iqentry_a1[head7] != iqentry_a1[head1]))
|
|| (iqentry_a1_v[head1] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
|| (iqentry_a1_v[head2] && iqentry_a1[head7] != iqentry_a1[head2]))
|
|| (iqentry_a1_v[head2] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head2][AMSB:3]))
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|
|| (iqentry_a1_v[head3] && iqentry_a1[head7] != iqentry_a1[head3]))
|
|| (iqentry_a1_v[head3] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head3][AMSB:3]))
|
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4])
|
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4])
|
|| (iqentry_a1_v[head4] && iqentry_a1[head7] != iqentry_a1[head4]))
|
|| (iqentry_a1_v[head4] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head4][AMSB:3]))
|
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5])
|
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5])
|
|| (iqentry_a1_v[head5] && iqentry_a1[head7] != iqentry_a1[head5]))
|
|| (iqentry_a1_v[head5] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head5][AMSB:3]))
|
&& (!iqentry_mem[head6] || (iqentry_agen[head6] & iqentry_out[head6])
|
&& (!iqentry_mem[head6] || (iqentry_agen[head6] & iqentry_out[head6])
|
|| (iqentry_a1_v[head6] && iqentry_a1[head7] != iqentry_a1[head6]))
|
|| (iqentry_a1_v[head6] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head6][AMSB:3]))
|
&& (iqentry_rl[head7] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_rl[head7] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
&& (iqentry_done[head4] || !iqentry_v[head4] || !iqentry_mem[head4])
|
&& (iqentry_done[head4] || !iqentry_v[head4] || !iqentry_mem[head4])
|
| Line 4860... |
Line 5221... |
&& !(iqentry_aq[head3] && iqentry_v[head3])
|
&& !(iqentry_aq[head3] && iqentry_v[head3])
|
&& !(iqentry_aq[head4] && iqentry_v[head4])
|
&& !(iqentry_aq[head4] && iqentry_v[head4])
|
&& !(iqentry_aq[head5] && iqentry_v[head5])
|
&& !(iqentry_aq[head5] && iqentry_v[head5])
|
&& !(iqentry_aq[head6] && iqentry_v[head6])
|
&& !(iqentry_aq[head6] && iqentry_v[head6])
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
&& (!(iqentry_v[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_iv[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_v[head2] && iqentry_memsb[head2]) ||
|
&& (!(iqentry_iv[head2] && iqentry_memsb[head2]) ||
|
((iqentry_done[head0] || !iqentry_v[head0])
|
((iqentry_done[head0] || !iqentry_v[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1]))
|
&& (iqentry_done[head1] || !iqentry_v[head1]))
|
)
|
)
|
&& (!(iqentry_v[head3] && iqentry_memsb[head3]) ||
|
&& (!(iqentry_iv[head3] && iqentry_memsb[head3]) ||
|
((iqentry_done[head0] || !iqentry_v[head0])
|
((iqentry_done[head0] || !iqentry_v[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2]))
|
&& (iqentry_done[head2] || !iqentry_v[head2]))
|
)
|
)
|
&& (!(iqentry_v[head4] && iqentry_memsb[head4]) ||
|
&& (!(iqentry_iv[head4] && iqentry_memsb[head4]) ||
|
((iqentry_done[head0] || !iqentry_v[head0])
|
((iqentry_done[head0] || !iqentry_v[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
&& (iqentry_done[head3] || !iqentry_v[head3]))
|
&& (iqentry_done[head3] || !iqentry_v[head3]))
|
)
|
)
|
&& (!(iqentry_v[head5] && iqentry_memsb[head5]) ||
|
&& (!(iqentry_iv[head5] && iqentry_memsb[head5]) ||
|
((iqentry_done[head0] || !iqentry_v[head0])
|
((iqentry_done[head0] || !iqentry_v[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
&& (iqentry_done[head3] || !iqentry_v[head3])
|
&& (iqentry_done[head3] || !iqentry_v[head3])
|
&& (iqentry_done[head4] || !iqentry_v[head4]))
|
&& (iqentry_done[head4] || !iqentry_v[head4]))
|
)
|
)
|
&& (!(iqentry_v[head6] && iqentry_memsb[head6]) ||
|
&& (!(iqentry_iv[head6] && iqentry_memsb[head6]) ||
|
((iqentry_done[head0] || !iqentry_v[head0])
|
((iqentry_done[head0] || !iqentry_v[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
&& (iqentry_done[head3] || !iqentry_v[head3])
|
&& (iqentry_done[head3] || !iqentry_v[head3])
|
&& (iqentry_done[head4] || !iqentry_v[head4])
|
&& (iqentry_done[head4] || !iqentry_v[head4])
|
&& (iqentry_done[head5] || !iqentry_v[head5]))
|
&& (iqentry_done[head5] || !iqentry_v[head5]))
|
)
|
)
|
&& (!(iqentry_v[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_iv[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
&& (!(iqentry_v[head2] && iqentry_memdb[head2]) ||
|
&& (!(iqentry_iv[head2] && iqentry_memdb[head2]) ||
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]))
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]))
|
)
|
)
|
&& (!(iqentry_v[head3] && iqentry_memdb[head3]) ||
|
&& (!(iqentry_iv[head3] && iqentry_memdb[head3]) ||
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]))
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]))
|
)
|
)
|
&& (!(iqentry_v[head4] && iqentry_memdb[head4]) ||
|
&& (!(iqentry_iv[head4] && iqentry_memdb[head4]) ||
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]))
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]))
|
)
|
)
|
&& (!(iqentry_v[head5] && iqentry_memdb[head5]) ||
|
&& (!(iqentry_iv[head5] && iqentry_memdb[head5]) ||
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])
|
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4]))
|
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4]))
|
)
|
)
|
&& (!(iqentry_v[head6] && iqentry_memdb[head6]) ||
|
&& (!(iqentry_iv[head6] && iqentry_memdb[head6]) ||
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])
|
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4])
|
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4])
|
| Line 4934... |
Line 5295... |
&& !(iqentry_fc[head5]||iqentry_canex[head5])
|
&& !(iqentry_fc[head5]||iqentry_canex[head5])
|
&& !(iqentry_fc[head6]||iqentry_canex[head6]));
|
&& !(iqentry_fc[head6]||iqentry_canex[head6]));
|
`endif
|
`endif
|
end
|
end
|
|
|
|
reg [2:0] wbptr;
|
|
always @*
|
|
begin
|
|
// Crashes sim
|
|
// wbptr <= `WB_DEPTH-1;
|
|
// if (wb_v==8'h0)
|
|
// wbptr <= 3'd0;
|
|
// else
|
|
// begin
|
|
// for (n = `WB_DEPTH-2; n >= 0; n = n - 1)
|
|
// if (wb_v[n] && wbptr==`WB_DEPTH-1)
|
|
// wbptr <= n + 1;
|
|
// end
|
|
if (wb_v[6])
|
|
wbptr <= 3'd7;
|
|
else if (wb_v[5])
|
|
wbptr <= 3'd6;
|
|
else if (wb_v[4])
|
|
wbptr <= 3'd5;
|
|
else if (wb_v[3])
|
|
wbptr <= 3'd4;
|
|
else if (wb_v[2])
|
|
wbptr <= 3'd3;
|
|
else if (wb_v[1])
|
|
wbptr <= 3'd2;
|
|
else if (wb_v[0])
|
|
wbptr <= 3'd1;
|
|
else
|
|
wbptr <= 3'd0;
|
|
end
|
|
|
// Stomp logic for branch miss.
|
// Stomp logic for branch miss.
|
|
|
FT64_stomp #(QENTRIES) ustmp1
|
FT64_stomp #(QENTRIES) ustmp1
|
(
|
(
|
.branchmiss(branchmiss),
|
.branchmiss(branchmiss),
|
| Line 4967... |
Line 5359... |
stompedOnRets = stompedOnRets + 4'd1;
|
stompedOnRets = stompedOnRets + 4'd1;
|
if (iqentry_stomp[7] && IsRet(iqentry_instr[7]))
|
if (iqentry_stomp[7] && IsRet(iqentry_instr[7]))
|
stompedOnRets = stompedOnRets + 4'd1;
|
stompedOnRets = stompedOnRets + 4'd1;
|
end
|
end
|
|
|
reg id1_vi, id2_vi;
|
reg id1_vi, id2_vi, id3_vi;
|
wire [4:0] id1_ido, id2_ido;
|
wire [4:0] id1_ido, id2_ido, id3_ido;
|
wire id1_vo, id2_vo;
|
wire id1_vo, id2_vo, id3_vo;
|
wire id1_clk, id2_clk;
|
wire id1_clk, id2_clk, id3_clk;
|
|
|
|
// Always at least one decoder
|
BUFGCE uclkb2
|
BUFGCE uclkb2
|
(
|
(
|
.I(clk_i),
|
.I(clk_i),
|
.CE(id1_available),
|
.CE(id1_available),
|
.O(id1_clk)
|
.O(id1_clk)
|
| Line 4995... |
Line 5388... |
.bus(id1_bus),
|
.bus(id1_bus),
|
.id_o(id1_ido),
|
.id_o(id1_ido),
|
.idv_o(id1_vo)
|
.idv_o(id1_vo)
|
);
|
);
|
|
|
|
generate begin : gIDUInst
|
|
if (`NUM_IDU > 1) begin
|
BUFGCE uclkb3
|
BUFGCE uclkb3
|
(
|
(
|
.I(clk_i),
|
.I(clk_i),
|
.CE(id2_available),
|
.CE(id2_available),
|
.O(id2_clk)
|
.O(id2_clk)
|
| Line 5017... |
Line 5412... |
.Rt(id2_Rt),
|
.Rt(id2_Rt),
|
.bus(id2_bus),
|
.bus(id2_bus),
|
.id_o(id2_ido),
|
.id_o(id2_ido),
|
.idv_o(id2_vo)
|
.idv_o(id2_vo)
|
);
|
);
|
|
end
|
|
if (`NUM_IDU > 2) begin
|
|
BUFGCE uclkb4
|
|
(
|
|
.I(clk_i),
|
|
.CE(id3_available),
|
|
.O(id3_clk)
|
|
);
|
|
|
|
FT64_idecoder uid2
|
|
(
|
|
.clk(id3_clk),
|
|
.idv_i(id3_vi),
|
|
.id_i(id3_id),
|
|
.instr(id3_instr),
|
|
.ven(id3_ven),
|
|
.vl(id3_vl),
|
|
.thrd(id3_thrd),
|
|
.predict_taken(id3_pt),
|
|
.Rt(id3_Rt),
|
|
.bus(id3_bus),
|
|
.id_o(id3_ido),
|
|
.idv_o(id3_vo)
|
|
);
|
|
end
|
|
end
|
|
endgenerate
|
|
|
//
|
//
|
// EXECUTE
|
// EXECUTE
|
//
|
//
|
reg [63:0] csr_r;
|
reg [63:0] csr_r;
|
| Line 5051... |
Line 5473... |
.exc(alu0_exc),
|
.exc(alu0_exc),
|
.thrd(alu0_thrd),
|
.thrd(alu0_thrd),
|
.mem(alu0_mem),
|
.mem(alu0_mem),
|
.shift48(alu0_shft48)
|
.shift48(alu0_shft48)
|
);
|
);
|
|
generate begin : gAluInst
|
|
if (`NUM_ALU > 1) begin
|
FT64_alu #(.BIG(1'b0),.SUP_VECTOR(SUP_VECTOR)) ualu1 (
|
FT64_alu #(.BIG(1'b0),.SUP_VECTOR(SUP_VECTOR)) ualu1 (
|
.rst(rst),
|
.rst(rst),
|
.clk(clk),
|
.clk(clk),
|
.ld(alu1_ld),
|
.ld(alu1_ld),
|
.abort(1'b0),
|
.abort(1'b0),
|
| Line 5078... |
Line 5502... |
.exc(alu1_exc),
|
.exc(alu1_exc),
|
.thrd(1'b0),
|
.thrd(1'b0),
|
.mem(alu1_mem),
|
.mem(alu1_mem),
|
.shift48(alu1_shft48)
|
.shift48(alu1_shft48)
|
);
|
);
|
|
end
|
|
end
|
|
endgenerate
|
|
|
|
generate begin : gFPUInst
|
|
if (`NUM_FPU > 0) begin
|
|
wire fpu1_clk;
|
|
BUFGCE ufpc1
|
|
(
|
|
.I(clk_i),
|
|
.CE(fpu1_available),
|
|
.O(fpu1_clk)
|
|
);
|
fpUnit ufp1
|
fpUnit ufp1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.clk(clk),
|
.clk(fpu1_clk),
|
|
.clk4x(clk4x),
|
|
.ce(1'b1),
|
|
.ir(fpu1_instr),
|
|
.ld(fpu1_ld),
|
|
.a(fpu1_argA),
|
|
.b(fpu1_argB),
|
|
.imm(fpu1_argI),
|
|
.o(fpu1_bus),
|
|
.csr_i(),
|
|
.status(fpu1_status),
|
|
.exception(),
|
|
.done(fpu1_done)
|
|
);
|
|
end
|
|
if (`NUM_FPU > 1) begin
|
|
wire fpu2_clk;
|
|
BUFGCE ufpc2
|
|
(
|
|
.I(clk_i),
|
|
.CE(fpu2_available),
|
|
.O(fpu2_clk)
|
|
);
|
|
fpUnit ufp1
|
|
(
|
|
.rst(rst),
|
|
.clk(fpu2_clk),
|
.clk4x(clk4x),
|
.clk4x(clk4x),
|
.ce(1'b1),
|
.ce(1'b1),
|
.ir(fpu_instr),
|
.ir(fpu2_instr),
|
.ld(fpu_ld),
|
.ld(fpu2_ld),
|
.a(fpu_argA),
|
.a(fpu2_argA),
|
.b(fpu_argB),
|
.b(fpu2_argB),
|
.imm(fpu_argI),
|
.imm(fpu2_argI),
|
.o(fpu_bus),
|
.o(fpu2_bus),
|
.csr_i(),
|
.csr_i(),
|
.status(fpu_status),
|
.status(fpu2_status),
|
.exception(),
|
.exception(),
|
.done(fpu_done)
|
.done(fpu2_done)
|
);
|
);
|
assign fpu_exc = |fpu_status[15:0] ? `FLT_FLT : `FLT_NONE;
|
end
|
|
end
|
|
endgenerate
|
|
|
|
assign fpu_exc = fpu1_available ? (|fpu1_status[15:0] ? `FLT_FLT : `FLT_NONE) : `FLT_UNIMP;
|
|
|
assign alu0_v = alu0_dataready,
|
assign alu0_v = alu0_dataready,
|
alu1_v = alu1_dataready;
|
alu1_v = alu1_dataready;
|
assign alu0_id = alu0_sourceid,
|
assign alu0_id = alu0_sourceid,
|
alu1_id = alu1_sourceid;
|
alu1_id = alu1_sourceid;
|
assign fpu_v = fpu_dataready;
|
assign fpu1_v = fpu1_dataready;
|
assign fpu_id = fpu_sourceid;
|
assign fpu1_id = fpu1_sourceid;
|
|
assign fpu2_v = fpu2_dataready;
|
|
assign fpu2_id = fpu2_sourceid;
|
|
|
`ifdef SUPPORT_SMT
|
`ifdef SUPPORT_SMT
|
wire [1:0] olm = ol[fcu_thrd];
|
wire [1:0] olm = ol[fcu_thrd];
|
`else
|
`else
|
wire [1:0] olm = ol;
|
wire [1:0] olm = ol;
|
| Line 5316... |
Line 5785... |
commit0_v <= ({iqentry_v[head0], iqentry_cmt[head0]} == 2'b11 && ~|panic);
|
commit0_v <= ({iqentry_v[head0], iqentry_cmt[head0]} == 2'b11 && ~|panic);
|
commit0_id <= {iqentry_mem[head0], head0}; // if a memory op, it has a DRAM-bus id
|
commit0_id <= {iqentry_mem[head0], head0}; // if a memory op, it has a DRAM-bus id
|
commit0_tgt <= iqentry_tgt[head0];
|
commit0_tgt <= iqentry_tgt[head0];
|
commit0_we <= iqentry_we[head0];
|
commit0_we <= iqentry_we[head0];
|
commit0_bus <= iqentry_res[head0];
|
commit0_bus <= iqentry_res[head0];
|
|
if (`NUM_CMT > 1) begin
|
commit1_v <= ({iqentry_v[head0], iqentry_cmt[head0]} != 2'b10
|
commit1_v <= ({iqentry_v[head0], iqentry_cmt[head0]} != 2'b10
|
&& {iqentry_v[head1], iqentry_cmt[head1]} == 2'b11
|
&& {iqentry_v[head1], iqentry_cmt[head1]} == 2'b11
|
&& ~|panic);
|
&& ~|panic);
|
commit1_id <= {iqentry_mem[head1], head1};
|
commit1_id <= {iqentry_mem[head1], head1};
|
commit1_tgt <= iqentry_tgt[head1];
|
commit1_tgt <= iqentry_tgt[head1];
|
commit1_we <= iqentry_we[head1];
|
commit1_we <= iqentry_we[head1];
|
commit1_bus <= iqentry_res[head1];
|
commit1_bus <= iqentry_res[head1];
|
end
|
end
|
|
else begin
|
|
commit1_tgt <= 12'h000;
|
|
commit1_we <= 8'h00;
|
|
end
|
|
end
|
|
|
assign int_commit = (commit0_v && IsIrq(iqentry_instr[head0])) ||
|
assign int_commit = (commit0_v && IsIrq(iqentry_instr[head0])) ||
|
(commit0_v && commit1_v && IsIrq(iqentry_instr[head1]));
|
(commit0_v && commit1_v && IsIrq(iqentry_instr[head1]) && `NUM_CMT > 1);
|
|
|
// Detect if a given register will become valid during the current cycle.
|
// Detect if a given register will become valid during the current cycle.
|
// We want a signal that is active during the current clock cycle for the read
|
// We want a signal that is active during the current clock cycle for the read
|
// through register file, which trims a cycle off register access for every
|
// through register file, which trims a cycle off register access for every
|
// instruction. But two different kinds of assignment statements can't be
|
// instruction. But two different kinds of assignment statements can't be
|
| Line 5354... |
Line 5829... |
end
|
end
|
end
|
end
|
if (commit0_v && n=={commit0_tgt[7:0]})
|
if (commit0_v && n=={commit0_tgt[7:0]})
|
regIsValid[n] = regIsValid[n] | (rf_source[ {commit0_tgt[7:0]} ] == commit0_id
|
regIsValid[n] = regIsValid[n] | (rf_source[ {commit0_tgt[7:0]} ] == commit0_id
|
|| (branchmiss && branchmiss_thrd == iqentry_thrd[commit0_id[`QBITS]] && iqentry_source[ commit0_id[`QBITS] ]));
|
|| (branchmiss && branchmiss_thrd == iqentry_thrd[commit0_id[`QBITS]] && iqentry_source[ commit0_id[`QBITS] ]));
|
if (commit1_v && n=={commit1_tgt[7:0]})
|
if (commit1_v && n=={commit1_tgt[7:0]} && `NUM_CMT > 1)
|
regIsValid[n] = regIsValid[n] | (rf_source[ {commit1_tgt[7:0]} ] == commit1_id
|
regIsValid[n] = regIsValid[n] | (rf_source[ {commit1_tgt[7:0]} ] == commit1_id
|
|| (branchmiss && branchmiss_thrd == iqentry_thrd[commit0_id[`QBITS]] && iqentry_source[ commit1_id[`QBITS] ]));
|
|| (branchmiss && branchmiss_thrd == iqentry_thrd[commit0_id[`QBITS]] && iqentry_source[ commit1_id[`QBITS] ]));
|
end
|
end
|
regIsValid[0] = `VAL;
|
regIsValid[0] = `VAL;
|
end
|
end
|
| Line 5556... |
Line 6031... |
// Like to move some of this to clocking under different always blocks in order
|
// Like to move some of this to clocking under different always blocks in order
|
// to help out the toolset's synthesis, but it ain't gonna be easy.
|
// to help out the toolset's synthesis, but it ain't gonna be easy.
|
// Simulation doesn't like it if things are under separate always blocks.
|
// Simulation doesn't like it if things are under separate always blocks.
|
// Synthesis doesn't like it if things are under the same always block.
|
// Synthesis doesn't like it if things are under the same always block.
|
|
|
always @(posedge clk)
|
//always @(posedge clk)
|
begin
|
//begin
|
branchmiss <= excmiss|fcu_branchmiss;
|
// branchmiss <= excmiss|fcu_branchmiss;
|
misspc <= excmiss ? excmisspc : fcu_misspc;
|
// misspc <= excmiss ? excmisspc : fcu_misspc;
|
missid <= excmiss ? (|iqentry_exc[head0] ? head0 : head1) : fcu_sourceid;
|
// missid <= excmiss ? (|iqentry_exc[head0] ? head0 : head1) : fcu_sourceid;
|
branchmiss_thrd <= excmiss ? excthrd : fcu_thrd;
|
// branchmiss_thrd <= excmiss ? excthrd : fcu_thrd;
|
end
|
//end
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (rst) begin
|
if (rst) begin
|
`ifdef SUPPORT_SMT
|
`ifdef SUPPORT_SMT
|
mstatus[0] <= 64'h0007; // select register set #0 for thread 0
|
mstatus[0] <= 64'h0007; // select register set #0 for thread 0
|
| Line 5591... |
Line 6066... |
iqentry_alu0[n] <= FALSE;
|
iqentry_alu0[n] <= FALSE;
|
iqentry_alu[n] <= FALSE;
|
iqentry_alu[n] <= FALSE;
|
iqentry_alu0_issue[n] <= FALSE;
|
iqentry_alu0_issue[n] <= FALSE;
|
iqentry_alu1_issue[n] <= FALSE;
|
iqentry_alu1_issue[n] <= FALSE;
|
iqentry_fpu[n] <= FALSE;
|
iqentry_fpu[n] <= FALSE;
|
iqentry_fpu_islot[n] <= 2'b00;
|
iqentry_fpu1_issue[n] <= FALSE;
|
iqentry_fpu_issue[n] <= FALSE;
|
iqentry_fpu2_issue[n] <= FALSE;
|
iqentry_fsync[n] <= FALSE;
|
iqentry_fsync[n] <= FALSE;
|
iqentry_fc[n] <= FALSE;
|
iqentry_fc[n] <= FALSE;
|
iqentry_fcu_issue[n] <= FALSE;
|
iqentry_fcu_issue[n] <= FALSE;
|
iqentry_jmp[n] <= FALSE;
|
iqentry_jmp[n] <= FALSE;
|
iqentry_ldcmp[n] <= FALSE;
|
iqentry_ldcmp[n] <= FALSE;
|
| Line 5616... |
Line 6091... |
iqentry_preload[n] <= FALSE;
|
iqentry_preload[n] <= FALSE;
|
iqentry_mem[n] <= FALSE;
|
iqentry_mem[n] <= FALSE;
|
iqentry_memndx[n] <= FALSE;
|
iqentry_memndx[n] <= FALSE;
|
iqentry_memissue[n] <= FALSE;
|
iqentry_memissue[n] <= FALSE;
|
iqentry_mem_islot[n] <= 3'd0;
|
iqentry_mem_islot[n] <= 3'd0;
|
|
iqentry_memdb[n] <= FALSE;
|
|
iqentry_memsb[n] <= FALSE;
|
iqentry_tgt[n] <= 6'd0;
|
iqentry_tgt[n] <= 6'd0;
|
iqentry_imm[n] <= 1'b0;
|
iqentry_imm[n] <= 1'b0;
|
iqentry_a0[n] <= 64'd0;
|
iqentry_a0[n] <= 64'd0;
|
iqentry_a1[n] <= 64'd0;
|
iqentry_a1[n] <= 64'd0;
|
iqentry_a2[n] <= 64'd0;
|
iqentry_a2[n] <= 64'd0;
|
| Line 5630... |
Line 6107... |
iqentry_a1_s[n] <= 5'd0;
|
iqentry_a1_s[n] <= 5'd0;
|
iqentry_a2_s[n] <= 5'd0;
|
iqentry_a2_s[n] <= 5'd0;
|
iqentry_a3_s[n] <= 5'd0;
|
iqentry_a3_s[n] <= 5'd0;
|
iqentry_canex[n] <= FALSE;
|
iqentry_canex[n] <= FALSE;
|
end
|
end
|
|
bwhich <= 2'b00;
|
dram0 <= `DRAMSLOT_AVAIL;
|
dram0 <= `DRAMSLOT_AVAIL;
|
dram1 <= `DRAMSLOT_AVAIL;
|
dram1 <= `DRAMSLOT_AVAIL;
|
dram2 <= `DRAMSLOT_AVAIL;
|
dram2 <= `DRAMSLOT_AVAIL;
|
dram0_instr <= `NOP_INSN;
|
dram0_instr <= `NOP_INSN;
|
dram1_instr <= `NOP_INSN;
|
dram1_instr <= `NOP_INSN;
|
| Line 5652... |
Line 6130... |
head4 <= 4;
|
head4 <= 4;
|
head5 <= 5;
|
head5 <= 5;
|
head6 <= 6;
|
head6 <= 6;
|
head7 <= 7;
|
head7 <= 7;
|
panic = `PANIC_NONE;
|
panic = `PANIC_NONE;
|
id1_available <= `ID1_AVAIL;
|
|
id2_available <= `ID2_AVAIL;
|
|
alu0_available <= `ALU0_AVAIL;
|
|
alu0_dataready <= 0;
|
alu0_dataready <= 0;
|
alu1_available <= `ALU1_AVAIL;
|
|
alu1_dataready <= 0;
|
alu1_dataready <= 0;
|
alu0_sourceid <= 5'd0;
|
alu0_sourceid <= 5'd0;
|
alu1_sourceid <= 5'd0;
|
alu1_sourceid <= 5'd0;
|
`ifdef SIM
|
`ifdef SIM
|
alu0_pc <= RSTPC;
|
alu0_pc <= RSTPC;
|
| Line 5686... |
Line 6160... |
alu1_shft48 <= 1'b0;
|
alu1_shft48 <= 1'b0;
|
alu1_thrd <= 1'b0;
|
alu1_thrd <= 1'b0;
|
alu1_tgt <= 6'h00;
|
alu1_tgt <= 6'h00;
|
alu1_ven <= 6'd0;
|
alu1_ven <= 6'd0;
|
`endif
|
`endif
|
fpu1_available <= `FPU1_AVAIL;
|
|
fcu_dataready <= 0;
|
fcu_dataready <= 0;
|
fcu_instr <= `NOP_INSN;
|
fcu_instr <= `NOP_INSN;
|
fcu_retadr_v <= 0;
|
fcu_retadr_v <= 0;
|
dramA_v <= 0;
|
dramA_v <= 0;
|
dramB_v <= 0;
|
dramB_v <= 0;
|
| Line 5718... |
Line 6191... |
pcr <= 32'd0;
|
pcr <= 32'd0;
|
pcr2 <= 64'd0;
|
pcr2 <= 64'd0;
|
for (n = 0; n < PREGS; n = n + 1)
|
for (n = 0; n < PREGS; n = n + 1)
|
rf_v[n] <= `VAL;
|
rf_v[n] <= `VAL;
|
tgtq <= FALSE;
|
tgtq <= FALSE;
|
fp_rm <= 3'd0; // round nearest even - default rounding mode
|
fp1_rm <= 3'd0; // round nearest even - default rounding mode
|
|
fp2_rm <= 3'd0;
|
waitctr <= 64'd0;
|
waitctr <= 64'd0;
|
for (n = 0; n < 16; n = n + 1)
|
for (n = 0; n < 16; n = n + 1)
|
badaddr[n] <= 64'd0;
|
badaddr[n] <= 64'd0;
|
sbl <= 32'h0;
|
sbl <= 32'h0;
|
sbu <= 32'hFFFFFFFF;
|
sbu <= 32'hFFFFFFFF;
|
| Line 5738... |
Line 6212... |
seq_num <= 5'd0;
|
seq_num <= 5'd0;
|
seq_num1 <= 5'd0;
|
seq_num1 <= 5'd0;
|
fcu_done <= `TRUE;
|
fcu_done <= `TRUE;
|
sema <= 64'h0;
|
sema <= 64'h0;
|
tvec[0] <= RSTPC;
|
tvec[0] <= RSTPC;
|
|
pmr <= 64'hFFFFFFFFFFFFFFFF;
|
|
pmr[0] <= `ID1_AVAIL;
|
|
pmr[1] <= `ID2_AVAIL;
|
|
pmr[2] <= `ID3_AVAIL;
|
|
pmr[8] <= `ALU0_AVAIL;
|
|
pmr[9] <= `ALU1_AVAIL;
|
|
pmr[16] <= `FPU1_AVAIL;
|
|
pmr[17] <= `FPU2_AVAIL;
|
|
pmr[24] <= `MEM1_AVAIL;
|
|
pmr[25] <= `MEM2_AVAIL;
|
|
pmr[26] <= `MEM3_AVAIL;
|
|
pmr[32] <= `FCU_AVAIL;
|
|
for (n = 0; n < `WB_DEPTH; n = n + 1) begin
|
|
wb_v[n] <= 1'b0;
|
|
wb_rmw[n] <= 1'b0;
|
|
wb_id[n] <= {QENTRIES{1'b0}};
|
|
end
|
|
wb_en <= `TRUE;
|
|
wbo_id <= {QENTRIES{1'b0}};
|
|
`ifdef SIM
|
|
wb_merges <= 32'd0;
|
|
`endif
|
end
|
end
|
else begin
|
else begin
|
|
if (|fb_panic)
|
|
panic <= fb_panic;
|
|
begin
|
|
branchmiss <= excmiss|fcu_branchmiss;
|
|
misspc <= excmiss ? excmisspc : fcu_misspc;
|
|
missid <= excmiss ? (|iqentry_exc[head0] ? head0 : head1) : fcu_sourceid;
|
|
branchmiss_thrd <= excmiss ? excthrd : fcu_thrd;
|
|
end
|
// The following signals only pulse
|
// The following signals only pulse
|
|
|
// Instruction decode output should only pulse once for a queue entry. We
|
// Instruction decode output should only pulse once for a queue entry. We
|
// want the decode to be invalidated after a clock cycle so that it isn't
|
// want the decode to be invalidated after a clock cycle so that it isn't
|
// inadvertently used to update the queue at a later point.
|
// inadvertently used to update the queue at a later point.
|
id1_vi <= `INV;
|
id1_vi <= `INV;
|
|
if (`NUM_IDU > 1)
|
id2_vi <= `INV;
|
id2_vi <= `INV;
|
|
if (`NUM_IDU > 2)
|
|
id3_vi <= `INV;
|
|
if (iqentry_v[nid] && iqentry_sn[nid] > iqentry_sn[fcu_id[`QBITS]])
|
|
fcu_dataready <= `INV;
|
ld_time <= {ld_time[4:0],1'b0};
|
ld_time <= {ld_time[4:0],1'b0};
|
wc_times <= wc_time;
|
wc_times <= wc_time;
|
rf_vra0 <= regIsValid[Ra0s];
|
rf_vra0 <= regIsValid[Ra0s];
|
rf_vra1 <= regIsValid[Ra1s];
|
rf_vra1 <= regIsValid[Ra1s];
|
if (vqe0 >= vl) begin
|
if (vqe0 >= vl) begin
|
| Line 5773... |
Line 6282... |
excmiss <= FALSE;
|
excmiss <= FALSE;
|
invic <= FALSE;
|
invic <= FALSE;
|
tick <= tick + 64'd1;
|
tick <= tick + 64'd1;
|
alu0_ld <= FALSE;
|
alu0_ld <= FALSE;
|
alu1_ld <= FALSE;
|
alu1_ld <= FALSE;
|
fpu_ld <= FALSE;
|
fpu1_ld <= FALSE;
|
|
fpu2_ld <= FALSE;
|
fcu_ld <= FALSE;
|
fcu_ld <= FALSE;
|
fcu_retadr_v <= FALSE;
|
fcu_retadr_v <= FALSE;
|
dramA_v <= FALSE;
|
dramA_v <= FALSE;
|
dramB_v <= FALSE;
|
dramB_v <= FALSE;
|
dramC_v <= FALSE;
|
dramC_v <= FALSE;
|
| Line 5823... |
Line 6333... |
if (commit0_tgt[5:0] != 6'd0) $display("r%d <- %h v[%d]<-%d", commit0_tgt, commit0_bus, regIsValid[commit0_tgt[5:0]],
|
if (commit0_tgt[5:0] != 6'd0) $display("r%d <- %h v[%d]<-%d", commit0_tgt, commit0_bus, regIsValid[commit0_tgt[5:0]],
|
rf_source[ {commit0_tgt[7:0]} ] == commit0_id || (branchmiss && iqentry_source[ commit0_id[`QBITS] ]));
|
rf_source[ {commit0_tgt[7:0]} ] == commit0_id || (branchmiss && iqentry_source[ commit0_id[`QBITS] ]));
|
if (commit0_tgt[5:0]==6'd30 && commit0_bus==64'd0)
|
if (commit0_tgt[5:0]==6'd30 && commit0_bus==64'd0)
|
$display("FP <= 0");
|
$display("FP <= 0");
|
end
|
end
|
if (commit1_v) begin
|
if (commit1_v && `NUM_CMT > 1) begin
|
if (!rf_v[ {commit1_tgt[7:0]} ]) begin
|
if (!rf_v[ {commit1_tgt[7:0]} ]) begin
|
if ({commit1_tgt[7:0]}=={commit0_tgt[7:0]})
|
if ({commit1_tgt[7:0]}=={commit0_tgt[7:0]})
|
rf_v[ {commit1_tgt[7:0]} ] <= regIsValid[{commit0_tgt[7:0]}] | regIsValid[{commit1_tgt[7:0]}];
|
rf_v[ {commit1_tgt[7:0]} ] <= regIsValid[{commit0_tgt[7:0]}] | regIsValid[{commit1_tgt[7:0]}];
|
/*
|
/*
|
(rf_source[ commit0_tgt[4:0] ] == commit0_id || (branchmiss && iqentry_source[ commit0_id[`QBITS] ])) ||
|
(rf_source[ commit0_tgt[4:0] ] == commit0_id || (branchmiss && iqentry_source[ commit0_id[`QBITS] ])) ||
|
| Line 6427... |
Line 6937... |
iqentry_out [ alu0_id[`QBITS] ] <= `INV;
|
iqentry_out [ alu0_id[`QBITS] ] <= `INV;
|
iqentry_agen[ alu0_id[`QBITS] ] <= `VAL;//!iqentry_fc[alu0_id[`QBITS]]; // RET
|
iqentry_agen[ alu0_id[`QBITS] ] <= `VAL;//!iqentry_fc[alu0_id[`QBITS]]; // RET
|
alu0_dataready <= FALSE;
|
alu0_dataready <= FALSE;
|
end
|
end
|
|
|
if (alu1_v) begin
|
if (alu1_v && `NUM_ALU > 1) begin
|
iqentry_tgt [ alu1_id[`QBITS] ] <= alu1_tgt;
|
iqentry_tgt [ alu1_id[`QBITS] ] <= alu1_tgt;
|
iqentry_res [ alu1_id[`QBITS] ] <= alu1_bus;
|
iqentry_res [ alu1_id[`QBITS] ] <= alu1_bus;
|
iqentry_exc [ alu1_id[`QBITS] ] <= alu1_exc;
|
iqentry_exc [ alu1_id[`QBITS] ] <= alu1_exc;
|
iqentry_done[ alu1_id[`QBITS] ] <= !iqentry_mem[ alu1_id[`QBITS] ] && alu1_done;
|
iqentry_done[ alu1_id[`QBITS] ] <= !iqentry_mem[ alu1_id[`QBITS] ] && alu1_done;
|
iqentry_cmt[ alu1_id[`QBITS] ] <= !iqentry_mem[ alu1_id[`QBITS] ] && alu1_done;
|
iqentry_cmt[ alu1_id[`QBITS] ] <= !iqentry_mem[ alu1_id[`QBITS] ] && alu1_done;
|
iqentry_out [ alu1_id[`QBITS] ] <= `INV;
|
iqentry_out [ alu1_id[`QBITS] ] <= `INV;
|
iqentry_agen[ alu1_id[`QBITS] ] <= `VAL;//!iqentry_fc[alu0_id[`QBITS]]; // RET
|
iqentry_agen[ alu1_id[`QBITS] ] <= `VAL;//!iqentry_fc[alu0_id[`QBITS]]; // RET
|
alu1_dataready <= FALSE;
|
alu1_dataready <= FALSE;
|
end
|
end
|
|
|
if (fpu_v) begin
|
if (fpu1_v) begin
|
iqentry_res [ fpu_id[`QBITS] ] <= fpu_bus;
|
iqentry_res [ fpu1_id[`QBITS] ] <= fpu1_bus;
|
iqentry_a0 [ fpu_id[`QBITS] ] <= fpu_status;
|
iqentry_a0 [ fpu1_id[`QBITS] ] <= fpu1_status;
|
iqentry_exc [ fpu_id[`QBITS] ] <= fpu_exc;
|
iqentry_exc [ fpu1_id[`QBITS] ] <= fpu1_exc;
|
iqentry_done[ fpu_id[`QBITS] ] <= fpu_done;
|
iqentry_done[ fpu1_id[`QBITS] ] <= fpu1_done;
|
iqentry_cmt[ fpu_id[`QBITS] ] <= fpu_done;
|
iqentry_cmt[ fpu1_id[`QBITS] ] <= fpu1_done;
|
iqentry_out [ fpu_id[`QBITS] ] <= `INV;
|
iqentry_out [ fpu1_id[`QBITS] ] <= `INV;
|
|
//iqentry_agen[ fpu_id[`QBITS] ] <= `VAL; // RET
|
|
fpu1_dataready <= FALSE;
|
|
end
|
|
|
|
if (fpu2_v && `NUM_FPU > 1) begin
|
|
iqentry_res [ fpu2_id[`QBITS] ] <= fpu2_bus;
|
|
iqentry_a0 [ fpu2_id[`QBITS] ] <= fpu2_status;
|
|
iqentry_exc [ fpu2_id[`QBITS] ] <= fpu2_exc;
|
|
iqentry_done[ fpu2_id[`QBITS] ] <= fpu2_done;
|
|
iqentry_cmt[ fpu2_id[`QBITS] ] <= fpu2_done;
|
|
iqentry_out [ fpu2_id[`QBITS] ] <= `INV;
|
//iqentry_agen[ fpu_id[`QBITS] ] <= `VAL; // RET
|
//iqentry_agen[ fpu_id[`QBITS] ] <= `VAL; // RET
|
fpu_dataready <= FALSE;
|
fpu2_dataready <= FALSE;
|
end
|
end
|
|
|
if (fcu_wr) begin
|
if (fcu_wr & ~fcu_done) begin
|
if (fcu_ld)
|
if (fcu_ld)
|
waitctr <= fcu_argA;
|
waitctr <= fcu_argA;
|
iqentry_res [ fcu_id[`QBITS] ] <= fcu_bus;
|
iqentry_res [ fcu_id[`QBITS] ] <= fcu_bus;
|
iqentry_exc [ fcu_id[`QBITS] ] <= fcu_exc;
|
iqentry_exc [ fcu_id[`QBITS] ] <= fcu_exc;
|
if (IsWait(fcu_instr)) begin
|
if (IsWait(fcu_instr)) begin
|
| Line 6493... |
Line 7014... |
fcu_clearbm <= `TRUE;
|
fcu_clearbm <= `TRUE;
|
//fcu_instr[`INSTRUCTION_OP] <= `NOP;
|
//fcu_instr[`INSTRUCTION_OP] <= `NOP;
|
//iqentry_instr[fcu_id][`INSTRUCTION_OP] <= `NOP;
|
//iqentry_instr[fcu_id][`INSTRUCTION_OP] <= `NOP;
|
end
|
end
|
// if (dram_v && iqentry_v[ dram_id[`QBITS] ] && iqentry_mem[ dram_id[`QBITS] ] ) begin // if data for stomped instruction, ignore
|
// if (dram_v && iqentry_v[ dram_id[`QBITS] ] && iqentry_mem[ dram_id[`QBITS] ] ) begin // if data for stomped instruction, ignore
|
if (dramA_v && iqentry_v[ dramA_id[`QBITS] ] && iqentry_load[ dramA_id[`QBITS] ]) begin // if data for stomped instruction, ignore
|
if (mem1_available && dramA_v && iqentry_v[ dramA_id[`QBITS] ] && iqentry_load[ dramA_id[`QBITS] ]) begin // if data for stomped instruction, ignore
|
iqentry_res [ dramA_id[`QBITS] ] <= dramA_bus;
|
iqentry_res [ dramA_id[`QBITS] ] <= dramA_bus;
|
iqentry_exc [ dramA_id[`QBITS] ] <= dramA_exc;
|
iqentry_exc [ dramA_id[`QBITS] ] <= dramA_exc;
|
iqentry_done[ dramA_id[`QBITS] ] <= `VAL;
|
iqentry_done[ dramA_id[`QBITS] ] <= `VAL;
|
iqentry_out [ dramA_id[`QBITS] ] <= `INV;
|
iqentry_out [ dramA_id[`QBITS] ] <= `INV;
|
iqentry_cmt[ dramA_id[`QBITS] ] <= `VAL;
|
iqentry_cmt[ dramA_id[`QBITS] ] <= `VAL;
|
iqentry_aq [ dramA_id[`QBITS] ] <= `INV;
|
iqentry_aq [ dramA_id[`QBITS] ] <= `INV;
|
// if (iqentry_lptr[dram0_id[`QBITS]])
|
// if (iqentry_lptr[dram0_id[`QBITS]])
|
// wbrcd[pcr[5:0]] <= 1'b1;
|
// wbrcd[pcr[5:0]] <= 1'b1;
|
end
|
end
|
if (dramB_v && iqentry_v[ dramB_id[`QBITS] ] && iqentry_load[ dramB_id[`QBITS] ]) begin // if data for stomped instruction, ignore
|
if (mem2_available && `NUM_MEM > 1 && dramB_v && iqentry_v[ dramB_id[`QBITS] ] && iqentry_load[ dramB_id[`QBITS] ]) begin // if data for stomped instruction, ignore
|
iqentry_res [ dramB_id[`QBITS] ] <= dramB_bus;
|
iqentry_res [ dramB_id[`QBITS] ] <= dramB_bus;
|
iqentry_exc [ dramB_id[`QBITS] ] <= dramB_exc;
|
iqentry_exc [ dramB_id[`QBITS] ] <= dramB_exc;
|
iqentry_done[ dramB_id[`QBITS] ] <= `VAL;
|
iqentry_done[ dramB_id[`QBITS] ] <= `VAL;
|
iqentry_out [ dramB_id[`QBITS] ] <= `INV;
|
iqentry_out [ dramB_id[`QBITS] ] <= `INV;
|
iqentry_cmt[ dramB_id[`QBITS] ] <= `VAL;
|
iqentry_cmt[ dramB_id[`QBITS] ] <= `VAL;
|
iqentry_aq [ dramB_id[`QBITS] ] <= `INV;
|
iqentry_aq [ dramB_id[`QBITS] ] <= `INV;
|
// if (iqentry_lptr[dram1_id[`QBITS]])
|
// if (iqentry_lptr[dram1_id[`QBITS]])
|
// wbrcd[pcr[5:0]] <= 1'b1;
|
// wbrcd[pcr[5:0]] <= 1'b1;
|
end
|
end
|
if (dramC_v && iqentry_v[ dramC_id[`QBITS] ] && iqentry_load[ dramC_id[`QBITS] ]) begin // if data for stomped instruction, ignore
|
if (mem3_available && `NUM_MEM > 2 && dramC_v && iqentry_v[ dramC_id[`QBITS] ] && iqentry_load[ dramC_id[`QBITS] ]) begin // if data for stomped instruction, ignore
|
iqentry_res [ dramC_id[`QBITS] ] <= dramC_bus;
|
iqentry_res [ dramC_id[`QBITS] ] <= dramC_bus;
|
iqentry_exc [ dramC_id[`QBITS] ] <= dramC_exc;
|
iqentry_exc [ dramC_id[`QBITS] ] <= dramC_exc;
|
iqentry_done[ dramC_id[`QBITS] ] <= `VAL;
|
iqentry_done[ dramC_id[`QBITS] ] <= `VAL;
|
iqentry_out [ dramC_id[`QBITS] ] <= `INV;
|
iqentry_out [ dramC_id[`QBITS] ] <= `INV;
|
iqentry_cmt[ dramC_id[`QBITS] ] <= `VAL;
|
iqentry_cmt[ dramC_id[`QBITS] ] <= `VAL;
|
| Line 6527... |
Line 7048... |
end
|
end
|
|
|
//
|
//
|
// set the IQ entry == DONE as soon as the SW is let loose to the memory system
|
// set the IQ entry == DONE as soon as the SW is let loose to the memory system
|
//
|
//
|
if (dram0 == `DRAMSLOT_BUSY && IsStore(dram0_instr)) begin
|
if (mem1_available && dram0 == `DRAMSLOT_BUSY && IsStore(dram0_instr)) begin
|
if ((alu0_v && (dram0_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram0_id[`QBITS] == alu1_id[`QBITS]))) panic <= `PANIC_MEMORYRACE;
|
if ((alu0_v && (dram0_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram0_id[`QBITS] == alu1_id[`QBITS]))) panic <= `PANIC_MEMORYRACE;
|
iqentry_done[ dram0_id[`QBITS] ] <= `VAL;
|
iqentry_done[ dram0_id[`QBITS] ] <= `VAL;
|
iqentry_out[ dram0_id[`QBITS] ] <= `INV;
|
iqentry_out[ dram0_id[`QBITS] ] <= `INV;
|
end
|
end
|
if (dram1 == `DRAMSLOT_BUSY && IsStore(dram1_instr)) begin
|
if (mem2_available && `NUM_MEM > 1 && dram1 == `DRAMSLOT_BUSY && IsStore(dram1_instr)) begin
|
if ((alu0_v && (dram1_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram1_id[`QBITS] == alu1_id[`QBITS]))) panic <= `PANIC_MEMORYRACE;
|
if ((alu0_v && (dram1_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram1_id[`QBITS] == alu1_id[`QBITS]))) panic <= `PANIC_MEMORYRACE;
|
iqentry_done[ dram1_id[`QBITS] ] <= `VAL;
|
iqentry_done[ dram1_id[`QBITS] ] <= `VAL;
|
iqentry_out[ dram1_id[`QBITS] ] <= `INV;
|
iqentry_out[ dram1_id[`QBITS] ] <= `INV;
|
end
|
end
|
if (dram2 == `DRAMSLOT_BUSY && IsStore(dram2_instr)) begin
|
if (mem3_available && `NUM_MEM > 2 && dram2 == `DRAMSLOT_BUSY && IsStore(dram2_instr)) begin
|
if ((alu0_v && (dram2_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram2_id[`QBITS] == alu1_id[`QBITS]))) panic <= `PANIC_MEMORYRACE;
|
if ((alu0_v && (dram2_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram2_id[`QBITS] == alu1_id[`QBITS]))) panic <= `PANIC_MEMORYRACE;
|
iqentry_done[ dram2_id[`QBITS] ] <= `VAL;
|
iqentry_done[ dram2_id[`QBITS] ] <= `VAL;
|
iqentry_out[ dram2_id[`QBITS] ] <= `INV;
|
iqentry_out[ dram2_id[`QBITS] ] <= `INV;
|
end
|
end
|
|
|
| Line 6556... |
Line 7077... |
// - commit1_bus
|
// - commit1_bus
|
//
|
//
|
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
for (n = 0; n < QENTRIES; n = n + 1)
|
begin
|
begin
|
setargs(n,{1'b0,fpu_id},fpu_v,fpu_bus);
|
if (`NUM_FPU > 0)
|
|
setargs(n,{1'b0,fpu1_id},fpu1_v,fpu1_bus);
|
|
if (`NUM_FPU > 1)
|
|
setargs(n,{1'b0,fpu2_id},fpu2_v,fpu2_bus);
|
|
|
setargs(n,{1'b0,alu0_id},alu0_v,alu0_bus);
|
setargs(n,{1'b0,alu0_id},alu0_v,alu0_bus);
|
|
if (`NUM_ALU > 1)
|
setargs(n,{1'b0,alu1_id},alu1_v,alu1_bus);
|
setargs(n,{1'b0,alu1_id},alu1_v,alu1_bus);
|
|
|
setargs(n,{1'b0,fcu_id},fcu_wr,fcu_bus);
|
setargs(n,{1'b0,fcu_id},fcu_wr,fcu_bus);
|
|
|
setargs(n,{1'b0,dramA_id},dramA_v,dramA_bus);
|
setargs(n,{1'b0,dramA_id},dramA_v,dramA_bus);
|
|
if (`NUM_MEM > 1)
|
setargs(n,{1'b0,dramB_id},dramB_v,dramB_bus);
|
setargs(n,{1'b0,dramB_id},dramB_v,dramB_bus);
|
|
if (`NUM_MEM > 2)
|
setargs(n,{1'b0,dramC_id},dramC_v,dramC_bus);
|
setargs(n,{1'b0,dramC_id},dramC_v,dramC_bus);
|
|
|
setargs(n,commit0_id,commit0_v,commit0_bus);
|
setargs(n,commit0_id,commit0_v,commit0_bus);
|
|
if (`NUM_CMT > 1)
|
setargs(n,commit1_id,commit1_v,commit1_bus);
|
setargs(n,commit1_id,commit1_v,commit1_bus);
|
|
|
setinsn(n[`QBITS],id1_ido,id1_available&id1_vo,id1_bus);
|
setinsn(n[`QBITS],id1_ido,id1_available&id1_vo,id1_bus);
|
|
if (`NUM_IDU > 1)
|
setinsn(n[`QBITS],id2_ido,id2_available&id2_vo,id2_bus);
|
setinsn(n[`QBITS],id2_ido,id2_available&id2_vo,id2_bus);
|
|
if (`NUM_IDU > 2)
|
|
setinsn(n[`QBITS],id3_ido,id3_available&id3_vo,id3_bus);
|
end
|
end
|
|
|
//
|
//
|
// ISSUE
|
// ISSUE
|
//
|
//
|
| Line 6585... |
Line 7120... |
if (iqentry_id1issue[n] && !iqentry_iv[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
if (iqentry_id1issue[n] && !iqentry_iv[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
id1_vi <= `VAL;
|
id1_vi <= `VAL;
|
id1_id <= n[4:0];
|
id1_id <= n[4:0];
|
id1_instr <= iqentry_rtop[n] ? (
|
id1_instr <= iqentry_rtop[n] ? (
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
|
`ifdef FU_BYPASS
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a3_s[n] == alu1_id) ? alu1_bus
|
: (iqentry_a3_s[n] == alu1_id) ? alu1_bus
|
|
`endif
|
: `NOP_INSN)
|
: `NOP_INSN)
|
: iqentry_instr[n];
|
: iqentry_instr[n];
|
id1_ven <= iqentry_ven[n];
|
id1_ven <= iqentry_ven[n];
|
id1_vl <= iqentry_vl[n];
|
id1_vl <= iqentry_vl[n];
|
id1_thrd <= iqentry_thrd[n];
|
id1_thrd <= iqentry_thrd[n];
|
id1_Rt <= iqentry_tgt[n][4:0];
|
id1_Rt <= iqentry_tgt[n][4:0];
|
id1_pt <= iqentry_pt[n];
|
id1_pt <= iqentry_pt[n];
|
end
|
end
|
end
|
end
|
|
if (`NUM_IDU > 1) begin
|
for (n = 0; n < QENTRIES; n = n + 1)
|
for (n = 0; n < QENTRIES; n = n + 1)
|
if (id2_available) begin
|
if (id2_available) begin
|
if (iqentry_id2issue[n] && !iqentry_iv[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
if (iqentry_id2issue[n] && !iqentry_iv[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
id2_vi <= `VAL;
|
id2_vi <= `VAL;
|
id2_id <= n[4:0];
|
id2_id <= n[4:0];
|
id2_instr <= iqentry_rtop[n] ? (
|
id2_instr <= iqentry_rtop[n] ? (
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
|
`ifdef FU_BYPASS
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a3_s[n] == alu1_id) ? alu1_bus
|
: (iqentry_a3_s[n] == alu1_id) ? alu1_bus
|
|
`endif
|
: `NOP_INSN)
|
: `NOP_INSN)
|
: iqentry_instr[n];
|
: iqentry_instr[n];
|
id2_ven <= iqentry_ven[n];
|
id2_ven <= iqentry_ven[n];
|
id2_vl <= iqentry_vl[n];
|
id2_vl <= iqentry_vl[n];
|
id2_thrd <= iqentry_thrd[n];
|
id2_thrd <= iqentry_thrd[n];
|
id2_Rt <= iqentry_tgt[n][4:0];
|
id2_Rt <= iqentry_tgt[n][4:0];
|
id2_pt <= iqentry_pt[n];
|
id2_pt <= iqentry_pt[n];
|
end
|
end
|
end
|
end
|
|
end
|
|
if (`NUM_IDU > 2) begin
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
|
if (id3_available) begin
|
|
if (iqentry_id3issue[n] && !iqentry_iv[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
|
id3_vi <= `VAL;
|
|
id3_id <= n[4:0];
|
|
id3_instr <= iqentry_rtop[n] ? (
|
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
|
`ifdef FU_BYPASS
|
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus
|
|
: (iqentry_a3_s[n] == alu1_id) ? alu1_bus
|
|
`endif
|
|
: `NOP_INSN)
|
|
: iqentry_instr[n];
|
|
id3_ven <= iqentry_ven[n];
|
|
id3_vl <= iqentry_vl[n];
|
|
id3_thrd <= iqentry_thrd[n];
|
|
id3_Rt <= iqentry_tgt[n][4:0];
|
|
id3_pt <= iqentry_pt[n];
|
|
end
|
|
end
|
|
end
|
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
for (n = 0; n < QENTRIES; n = n + 1)
|
if (iqentry_alu0_issue[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
if (iqentry_alu0_issue[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
if (alu0_available & alu0_done) begin
|
if (alu0_available & alu0_done) begin
|
alu0_sourceid <= n[3:0];
|
alu0_sourceid <= n[3:0];
|
alu0_instr <= iqentry_rtop[n] ? (
|
alu0_instr <= iqentry_rtop[n] ? (
|
|
`ifdef FU_BYPASS
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus : alu1_bus)
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus
|
|
: (iqentry_a3_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
|
: alu1_bus)
|
|
`else
|
|
iqentry_a3[n])
|
|
`endif
|
: iqentry_instr[n];
|
: iqentry_instr[n];
|
alu0_bt <= iqentry_bt[n];
|
alu0_bt <= iqentry_bt[n];
|
alu0_mem <= iqentry_mem[n];
|
alu0_mem <= iqentry_mem[n];
|
alu0_shft48 <= iqentry_shft48[n];
|
alu0_shft48 <= iqentry_shft48[n];
|
alu0_pc <= iqentry_pc[n];
|
alu0_pc <= iqentry_pc[n];
|
alu0_argA <= iqentry_a1_v[n] ? iqentry_a1[n]
|
alu0_argA <=
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
`ifdef FU_BYPASS
|
|
iqentry_a1_v[n] ? iqentry_a1[n]
|
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
|
: (iqentry_a1_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
|
: alu1_bus;
|
|
`else
|
|
iqentry_a1[n];
|
|
`endif
|
alu0_argB <= iqentry_imm[n]
|
alu0_argB <= iqentry_imm[n]
|
? iqentry_a0[n]
|
? iqentry_a0[n]
|
|
`ifdef FU_BYPASS
|
: (iqentry_a2_v[n] ? iqentry_a2[n]
|
: (iqentry_a2_v[n] ? iqentry_a2[n]
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus : alu1_bus);
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus
|
alu0_argC <= iqentry_a3_v[n] ? iqentry_a3[n]
|
: (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
|
: alu1_bus);
|
|
`else
|
|
: iqentry_a2[n];
|
|
`endif
|
|
alu0_argC <=
|
|
`ifdef FU_BYPASS
|
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
|
`else
|
|
iqentry_a3[n];
|
|
`endif
|
alu0_argI <= iqentry_a0[n];
|
alu0_argI <= iqentry_a0[n];
|
alu0_tgt <= IsVeins(iqentry_instr[n]) ?
|
alu0_tgt <= IsVeins(iqentry_instr[n]) ?
|
{6'h0,1'b1,iqentry_tgt[n][4:0]} | ((iqentry_a2_v[n] ? iqentry_a2[n][5:0]
|
{6'h0,1'b1,iqentry_tgt[n][4:0]} | ((
|
|
iqentry_a2_v[n] ? iqentry_a2[n][5:0]
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus[5:0]
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus[5:0]
|
: (iqentry_a2_s[n] == alu1_id) ? alu1_bus[5:0]
|
: (iqentry_a2_s[n] == alu1_id) ? alu1_bus[5:0]
|
: {4{16'h0000}})) << 6 :
|
: {4{16'h0000}})) << 6 :
|
iqentry_tgt[n];
|
iqentry_tgt[n];
|
alu0_ven <= iqentry_ven[n];
|
alu0_ven <= iqentry_ven[n];
|
| Line 6654... |
Line 7242... |
iqentry_a1_v[n] <= `INV;
|
iqentry_a1_v[n] <= `INV;
|
iqentry_a1_s[n] <= n[3:0];
|
iqentry_a1_s[n] <= n[3:0];
|
end
|
end
|
end
|
end
|
end
|
end
|
|
if (`NUM_ALU > 1) begin
|
for (n = 0; n < QENTRIES; n = n + 1)
|
for (n = 0; n < QENTRIES; n = n + 1)
|
if (iqentry_alu1_issue[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
if (iqentry_alu1_issue[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
if (alu1_available && alu1_done) begin
|
if (alu1_available && alu1_done) begin
|
if (iqentry_alu0[n])
|
if (iqentry_alu0[n])
|
panic <= `PANIC_ALU0ONLY;
|
panic <= `PANIC_ALU0ONLY;
|
| Line 6666... |
Line 7254... |
alu1_instr <= iqentry_instr[n];
|
alu1_instr <= iqentry_instr[n];
|
alu1_bt <= iqentry_bt[n];
|
alu1_bt <= iqentry_bt[n];
|
alu1_mem <= iqentry_mem[n];
|
alu1_mem <= iqentry_mem[n];
|
alu1_shft48 <= iqentry_shft48[n];
|
alu1_shft48 <= iqentry_shft48[n];
|
alu1_pc <= iqentry_pc[n];
|
alu1_pc <= iqentry_pc[n];
|
alu1_argA <= iqentry_a1_v[n] ? iqentry_a1[n]
|
alu1_argA <=
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
`ifdef FU_BYPASS
|
|
iqentry_a1_v[n] ? iqentry_a1[n]
|
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
|
: (iqentry_a1_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
|
: alu1_bus;
|
|
`else
|
|
iqentry_a1[n];
|
|
`endif
|
alu1_argB <= iqentry_imm[n]
|
alu1_argB <= iqentry_imm[n]
|
? iqentry_a0[n]
|
? iqentry_a0[n]
|
|
`ifdef FU_BYPASS
|
: (iqentry_a2_v[n] ? iqentry_a2[n]
|
: (iqentry_a2_v[n] ? iqentry_a2[n]
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus : alu1_bus);
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus
|
alu1_argC <= iqentry_a3_v[n] ? iqentry_a3[n]
|
: (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
|
: alu1_bus);
|
|
`else
|
|
: iqentry_a2[n];
|
|
`endif
|
|
alu1_argC <=
|
|
`ifdef FU_BYPASS
|
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
|
`else
|
|
iqentry_a3[n];
|
|
`endif
|
alu1_argI <= iqentry_a0[n];
|
alu1_argI <= iqentry_a0[n];
|
alu1_tgt <= IsVeins(iqentry_instr[n]) ?
|
alu1_tgt <= IsVeins(iqentry_instr[n]) ?
|
{6'h0,1'b1,iqentry_tgt[n][4:0]} | ((iqentry_a2_v[n] ? iqentry_a2[n][5:0]
|
{6'h0,1'b1,iqentry_tgt[n][4:0]} | ((iqentry_a2_v[n] ? iqentry_a2[n][5:0]
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus[5:0]
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus[5:0]
|
: (iqentry_a2_s[n] == alu1_id) ? alu1_bus[5:0]
|
: (iqentry_a2_s[n] == alu1_id) ? alu1_bus[5:0]
|
| Line 6692... |
Line 7298... |
iqentry_a1_v[n] <= `INV;
|
iqentry_a1_v[n] <= `INV;
|
iqentry_a1_s[n] <= n[3:0];
|
iqentry_a1_s[n] <= n[3:0];
|
end
|
end
|
end
|
end
|
end
|
end
|
|
end
|
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
for (n = 0; n < QENTRIES; n = n + 1)
|
if (iqentry_fpu_issue[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
if (iqentry_fpu1_issue[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
if (fpu1_available & fpu_done) begin
|
if (fpu1_available & fpu1_done) begin
|
fpu_sourceid <= n[3:0];
|
fpu1_sourceid <= n[3:0];
|
fpu_instr <= iqentry_instr[n];
|
fpu1_instr <= iqentry_instr[n];
|
fpu_pc <= iqentry_pc[n];
|
fpu1_pc <= iqentry_pc[n];
|
fpu_argA <= iqentry_a1_v[n] ? iqentry_a1[n]
|
fpu1_argA <=
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
`ifdef FU_BYPASS
|
fpu_argB <= (iqentry_a2_v[n] ? iqentry_a2[n]
|
iqentry_a1_v[n] ? iqentry_a1[n]
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus : alu1_bus);
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
fpu_argC <= iqentry_a3_v[n] ? iqentry_a3[n]
|
: (iqentry_a1_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
|
: alu1_bus;
|
|
`else
|
|
iqentry_a1[n];
|
|
`endif
|
|
fpu1_argB <=
|
|
`ifdef FU_BYPASS
|
|
(iqentry_a2_v[n] ? iqentry_a2[n]
|
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus
|
|
: (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
|
: alu1_bus);
|
|
`else
|
|
iqentry_a2[n];
|
|
`endif
|
|
fpu1_argC <=
|
|
`ifdef FU_BYPASS
|
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
|
`else
|
|
iqentry_a3[n];
|
|
`endif
|
|
fpu1_argI <= iqentry_a0[n];
|
|
fpu1_dataready <= `VAL;
|
|
fpu1_ld <= TRUE;
|
|
iqentry_out[n] <= `VAL;
|
|
end
|
|
end
|
|
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
|
if (`NUM_FPU > 1 && iqentry_fpu2_issue[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
|
if (fpu2_available & fpu2_done) begin
|
|
fpu2_sourceid <= n[3:0];
|
|
fpu2_instr <= iqentry_instr[n];
|
|
fpu2_pc <= iqentry_pc[n];
|
|
fpu2_argA <=
|
|
`ifdef FU_BYPASS
|
|
iqentry_a1_v[n] ? iqentry_a1[n]
|
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
|
: (iqentry_a1_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
|
: alu1_bus;
|
|
`else
|
|
iqentry_a1[n];
|
|
`endif
|
|
fpu2_argB <=
|
|
`ifdef FU_BYPASS
|
|
(iqentry_a2_v[n] ? iqentry_a2[n]
|
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus
|
|
: (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
|
: alu1_bus);
|
|
`else
|
|
iqentry_a2[n];
|
|
`endif
|
|
fpu2_argC <=
|
|
`ifdef FU_BYPASS
|
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
fpu_argI <= iqentry_a0[n];
|
`else
|
fpu_dataready <= `VAL;
|
iqentry_a3[n];
|
fpu_ld <= TRUE;
|
`endif
|
|
fpu2_argI <= iqentry_a0[n];
|
|
fpu2_dataready <= `VAL;
|
|
fpu2_ld <= TRUE;
|
iqentry_out[n] <= `VAL;
|
iqentry_out[n] <= `VAL;
|
end
|
end
|
end
|
end
|
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
for (n = 0; n < QENTRIES; n = n + 1)
|
| Line 6725... |
Line 7389... |
fcu_brdisp <= {{52{iqentry_instr[n][31]}},iqentry_instr[n][31:21],1'b0};
|
fcu_brdisp <= {{52{iqentry_instr[n][31]}},iqentry_instr[n][31:21],1'b0};
|
fcu_call <= IsCall(iqentry_instr[n])|IsJAL(iqentry_instr[n]);
|
fcu_call <= IsCall(iqentry_instr[n])|IsJAL(iqentry_instr[n]);
|
fcu_bt <= iqentry_bt[n];
|
fcu_bt <= iqentry_bt[n];
|
fcu_pc <= iqentry_pc[n];
|
fcu_pc <= iqentry_pc[n];
|
fcu_argA <= iqentry_a1_v[n] ? iqentry_a1[n]
|
fcu_argA <= iqentry_a1_v[n] ? iqentry_a1[n]
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
|
: (iqentry_a1_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
|
: alu1_bus;
|
`ifdef SUPPORT_SMT
|
`ifdef SUPPORT_SMT
|
fcu_argB <= IsRTI(iqentry_instr[n]) ? epc0[iqentry_thrd[n]]
|
fcu_argB <= IsRTI(iqentry_instr[n]) ? epc0[iqentry_thrd[n]]
|
`else
|
`else
|
fcu_argB <= IsRTI(iqentry_instr[n]) ? epc0
|
fcu_argB <= IsRTI(iqentry_instr[n]) ? epc0
|
`endif
|
`endif
|
: (iqentry_a2_v[n] ? iqentry_a2[n]
|
: (iqentry_a2_v[n] ? iqentry_a2[n]
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus : alu1_bus);
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus
|
|
: (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
|
: alu1_bus);
|
waitctr <= iqentry_imm[n]
|
waitctr <= iqentry_imm[n]
|
? iqentry_a0[n]
|
? iqentry_a0[n]
|
: (iqentry_a2_v[n] ? iqentry_a2[n]
|
: (iqentry_a2_v[n] ? iqentry_a2[n]
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus : alu1_bus);
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus : alu1_bus);
|
fcu_argC <= iqentry_a3_v[n] ? iqentry_a3[n]
|
fcu_argC <= iqentry_a3_v[n] ? iqentry_a3[n]
|
| Line 6773... |
Line 7441... |
// if (dram1 != `DRAMSLOT_AVAIL) dram1 <= dram1 + 2'd1;
|
// if (dram1 != `DRAMSLOT_AVAIL) dram1 <= dram1 + 2'd1;
|
// if (dram2 != `DRAMSLOT_AVAIL) dram2 <= dram2 + 2'd1;
|
// if (dram2 != `DRAMSLOT_AVAIL) dram2 <= dram2 + 2'd1;
|
|
|
//
|
//
|
// grab requests that have finished and put them on the dram_bus
|
// grab requests that have finished and put them on the dram_bus
|
if (dram0 == `DRAMREQ_READY) begin
|
if (mem1_available && dram0 == `DRAMREQ_READY) begin
|
dram0 <= `DRAMSLOT_AVAIL;
|
dram0 <= `DRAMSLOT_AVAIL;
|
dramA_v <= dram0_load;
|
dramA_v <= dram0_load;
|
dramA_id <= dram0_id;
|
dramA_id <= dram0_id;
|
dramA_exc <= dram0_exc;
|
dramA_exc <= dram0_exc;
|
dramA_bus <= fnDati(dram0_instr,dram0_addr,rdat0);
|
dramA_bus <= fnDati(dram0_instr,dram0_addr,rdat0);
|
if (IsStore(dram0_instr)) $display("m[%h] <- %h", dram0_addr, dram0_data);
|
if (IsStore(dram0_instr)) $display("m[%h] <- %h", dram0_addr, dram0_data);
|
end
|
end
|
// else
|
// else
|
// dramA_v <= `INV;
|
// dramA_v <= `INV;
|
if (dram1 == `DRAMREQ_READY) begin
|
if (mem2_available && dram1 == `DRAMREQ_READY && `NUM_MEM > 1) begin
|
dram1 <= `DRAMSLOT_AVAIL;
|
dram1 <= `DRAMSLOT_AVAIL;
|
dramB_v <= dram1_load;
|
dramB_v <= dram1_load;
|
dramB_id <= dram1_id;
|
dramB_id <= dram1_id;
|
dramB_exc <= dram1_exc;
|
dramB_exc <= dram1_exc;
|
dramB_bus <= fnDati(dram1_instr,dram1_addr,rdat1);
|
dramB_bus <= fnDati(dram1_instr,dram1_addr,rdat1);
|
if (IsStore(dram1_instr)) $display("m[%h] <- %h", dram1_addr, dram1_data);
|
if (IsStore(dram1_instr)) $display("m[%h] <- %h", dram1_addr, dram1_data);
|
end
|
end
|
// else
|
// else
|
// dramB_v <= `INV;
|
// dramB_v <= `INV;
|
if (dram2 == `DRAMREQ_READY) begin
|
if (mem3_available && dram2 == `DRAMREQ_READY && `NUM_MEM > 2) begin
|
dram2 <= `DRAMSLOT_AVAIL;
|
dram2 <= `DRAMSLOT_AVAIL;
|
dramC_v <= dram2_load;
|
dramC_v <= dram2_load;
|
dramC_id <= dram2_id;
|
dramC_id <= dram2_id;
|
dramC_exc <= dram2_exc;
|
dramC_exc <= dram2_exc;
|
dramC_bus <= fnDati(dram2_instr,dram2_addr,rdat2);
|
dramC_bus <= fnDati(dram2_instr,dram2_addr,rdat2);
|
| Line 6829... |
Line 7497... |
if (dram2_id[`QBITS] == n[`QBITS]) dram2 <= `DRAMSLOT_AVAIL;
|
if (dram2_id[`QBITS] == n[`QBITS]) dram2 <= `DRAMSLOT_AVAIL;
|
end
|
end
|
|
|
last_issue = 8;
|
last_issue = 8;
|
for (n = 0; n < QENTRIES; n = n + 1)
|
for (n = 0; n < QENTRIES; n = n + 1)
|
if (~iqentry_stomp[n] && iqentry_memissue[n] && iqentry_agen[n] && ~iqentry_out[n]) begin
|
if (~iqentry_stomp[n] && iqentry_memissue[n] && iqentry_agen[n] && ~iqentry_out[n] && ~iqentry_done[n]) begin
|
if (dram0 == `DRAMSLOT_AVAIL) begin
|
if (mem1_available && dram0 == `DRAMSLOT_AVAIL) begin
|
dramA_v <= `INV;
|
dramA_v <= `INV;
|
dram0 <= `DRAMSLOT_BUSY;
|
dram0 <= `DRAMSLOT_BUSY;
|
dram0_id <= { 1'b1, n[`QBITS] };
|
dram0_id <= { 1'b1, n[`QBITS] };
|
dram0_instr <= iqentry_instr[n];
|
dram0_instr <= iqentry_instr[n];
|
dram0_rmw <= iqentry_rmw[n];
|
dram0_rmw <= iqentry_rmw[n];
|
| Line 6843... |
Line 7511... |
dram0_data <= iqentry_memndx[n] ? iqentry_a3[n] : iqentry_a2[n];
|
dram0_data <= iqentry_memndx[n] ? iqentry_a3[n] : iqentry_a2[n];
|
dram0_addr <= iqentry_a1[n];
|
dram0_addr <= iqentry_a1[n];
|
// if (ol[iqentry_thrd[n]]==`OL_USER)
|
// if (ol[iqentry_thrd[n]]==`OL_USER)
|
// dram0_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
|
// dram0_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
|
// else
|
// else
|
dram0_seg <= 64'd0;
|
|
dram0_unc <= iqentry_a1[n][31:20]==12'hFFD || !dce || IsVolatileLoad(iqentry_instr[n]);
|
dram0_unc <= iqentry_a1[n][31:20]==12'hFFD || !dce || IsVolatileLoad(iqentry_instr[n]);
|
dram0_memsize <= MemSize(iqentry_instr[n]);
|
dram0_memsize <= MemSize(iqentry_instr[n]);
|
dram0_load <= iqentry_load[n];
|
dram0_load <= iqentry_load[n];
|
dram0_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
|
dram0_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
|
// Once the memory op is issued reset the a1_v flag.
|
// Once the memory op is issued reset the a1_v flag.
|
| Line 6858... |
Line 7525... |
end
|
end
|
end
|
end
|
if (last_issue < 8)
|
if (last_issue < 8)
|
iqentry_out[last_issue] <= `VAL;
|
iqentry_out[last_issue] <= `VAL;
|
for (n = 0; n < QENTRIES; n = n + 1)
|
for (n = 0; n < QENTRIES; n = n + 1)
|
if (~iqentry_stomp[n] && iqentry_memissue[n] && iqentry_agen[n] && ~iqentry_out[n]) begin
|
if (~iqentry_stomp[n] && iqentry_memissue[n] && iqentry_agen[n] && ~iqentry_out[n] && ~iqentry_done[n]) begin
|
if (n < last_issue) begin
|
if (mem2_available && n < last_issue && `NUM_MEM > 1) begin
|
if (dram1 == `DRAMSLOT_AVAIL) begin
|
if (dram1 == `DRAMSLOT_AVAIL) begin
|
dramB_v <= `INV;
|
dramB_v <= `INV;
|
dram1 <= `DRAMSLOT_BUSY;
|
dram1 <= `DRAMSLOT_BUSY;
|
dram1_id <= { 1'b1, n[`QBITS] };
|
dram1_id <= { 1'b1, n[`QBITS] };
|
dram1_instr <= iqentry_instr[n];
|
dram1_instr <= iqentry_instr[n];
|
| Line 6873... |
Line 7540... |
dram1_data <= iqentry_memndx[n] ? iqentry_a3[n] : iqentry_a2[n];
|
dram1_data <= iqentry_memndx[n] ? iqentry_a3[n] : iqentry_a2[n];
|
dram1_addr <= iqentry_a1[n];
|
dram1_addr <= iqentry_a1[n];
|
// if (ol[iqentry_thrd[n]]==`OL_USER)
|
// if (ol[iqentry_thrd[n]]==`OL_USER)
|
// dram1_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
|
// dram1_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
|
// else
|
// else
|
dram1_seg <= 64'd0;
|
|
dram1_unc <= iqentry_a1[n][31:20]==12'hFFD || !dce || IsVolatileLoad(iqentry_instr[n]);
|
dram1_unc <= iqentry_a1[n][31:20]==12'hFFD || !dce || IsVolatileLoad(iqentry_instr[n]);
|
dram1_memsize <= MemSize(iqentry_instr[n]);
|
dram1_memsize <= MemSize(iqentry_instr[n]);
|
dram1_load <= iqentry_load[n];
|
dram1_load <= iqentry_load[n];
|
dram1_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
|
dram1_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
|
iqentry_a1_v[n] <= `INV;
|
iqentry_a1_v[n] <= `INV;
|
| Line 6886... |
Line 7552... |
end
|
end
|
end
|
end
|
if (last_issue < 8)
|
if (last_issue < 8)
|
iqentry_out[last_issue] <= `VAL;
|
iqentry_out[last_issue] <= `VAL;
|
for (n = 0; n < QENTRIES; n = n + 1)
|
for (n = 0; n < QENTRIES; n = n + 1)
|
if (~iqentry_stomp[n] && iqentry_memissue[n] && iqentry_agen[n] && ~iqentry_out[n]) begin
|
if (~iqentry_stomp[n] && iqentry_memissue[n] && iqentry_agen[n] && ~iqentry_out[n] && ~iqentry_done[n]) begin
|
if (n < last_issue) begin
|
if (mem3_available && n < last_issue && `NUM_MEM > 2) begin
|
if (dram2 == `DRAMSLOT_AVAIL) begin
|
if (dram2 == `DRAMSLOT_AVAIL) begin
|
dramC_v <= `INV;
|
dramC_v <= `INV;
|
dram2 <= `DRAMSLOT_BUSY;
|
dram2 <= `DRAMSLOT_BUSY;
|
dram2_id <= { 1'b1, n[`QBITS] };
|
dram2_id <= { 1'b1, n[`QBITS] };
|
dram2_instr <= iqentry_instr[n];
|
dram2_instr <= iqentry_instr[n];
|
| Line 6901... |
Line 7567... |
dram2_data <= iqentry_memndx[n] ? iqentry_a3[n] : iqentry_a2[n];
|
dram2_data <= iqentry_memndx[n] ? iqentry_a3[n] : iqentry_a2[n];
|
dram2_addr <= iqentry_a1[n];
|
dram2_addr <= iqentry_a1[n];
|
// if (ol[iqentry_thrd[n]]==`OL_USER)
|
// if (ol[iqentry_thrd[n]]==`OL_USER)
|
// dram2_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
|
// dram2_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
|
// else
|
// else
|
dram2_seg <= 64'd0;
|
|
dram2_unc <= iqentry_a1[n][31:20]==12'hFFD || !dce || IsVolatileLoad(iqentry_instr[n]);
|
dram2_unc <= iqentry_a1[n][31:20]==12'hFFD || !dce || IsVolatileLoad(iqentry_instr[n]);
|
dram2_memsize <= MemSize(iqentry_instr[n]);
|
dram2_memsize <= MemSize(iqentry_instr[n]);
|
dram2_load <= iqentry_load[n];
|
dram2_load <= iqentry_load[n];
|
dram2_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
|
dram2_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
|
iqentry_a1_v[n] <= `INV;
|
iqentry_a1_v[n] <= `INV;
|
| Line 6933... |
Line 7598... |
// look at head0 and head1 and let 'em write to the register file if they are ready
|
// look at head0 and head1 and let 'em write to the register file if they are ready
|
//
|
//
|
// always @(posedge clk) begin: commit_phase
|
// always @(posedge clk) begin: commit_phase
|
|
|
oddball_commit(commit0_v, head0);
|
oddball_commit(commit0_v, head0);
|
|
if (`NUM_CMT > 1)
|
oddball_commit(commit1_v, head1);
|
oddball_commit(commit1_v, head1);
|
|
|
// Fetch and queue are limited to two instructions per cycle, so we might as
|
// Fetch and queue are limited to two instructions per cycle, so we might as
|
// well limit retiring to two instructions max to conserve logic.
|
// well limit retiring to two instructions max to conserve logic.
|
//
|
//
|
if (~|panic)
|
if (~|panic)
|
casez ({ iqentry_v[head0],
|
casez ({ iqentry_v[head0],
|
iqentry_cmt[head0],
|
iqentry_cmt[head0],
|
iqentry_v[head1],
|
iqentry_v[head1],
|
iqentry_cmt[head1]})
|
iqentry_cmt[head1],
|
|
iqentry_v[head2],
|
|
iqentry_cmt[head2]})
|
|
|
// retire 3
|
// retire 3
|
4'b0?_0?:
|
6'b0?_0?_0?:
|
if (head0 != tail0 && head1 != tail0) begin
|
if (head0 != tail0 && head1 != tail0 && head2 != tail0) begin
|
|
head_inc(3);
|
|
end
|
|
else if (head0 != tail0 && head1 != tail0) begin
|
head_inc(2);
|
head_inc(2);
|
end
|
end
|
else if (head0 != tail0) begin
|
else if (head0 != tail0) begin
|
head_inc(1);
|
head_inc(1);
|
end
|
end
|
|
6'b0?_0?_10: ;
|
|
6'b0?_0?_11:
|
|
if (`NUM_CMT > 2 || iqentry_tgt[head2][4:0]==5'd0) begin
|
|
iqentry_v[head2] <= `INV;
|
|
head_inc(3);
|
|
end
|
|
else begin
|
|
head_inc(2);
|
|
end
|
|
|
// retire 1 (wait for regfile for head1)
|
// retire 1 (wait for regfile for head1)
|
4'b0?_10:
|
6'b0?_10_??:
|
head_inc(1);
|
head_inc(1);
|
|
|
// retire 2
|
// retire 2
|
4'b0?_11:
|
6'b0?_11_0?,
|
begin
|
6'b0?_11_10:
|
|
if (`NUM_CMT > 1 || iqentry_tgt[head1]==12'd0) begin
|
iqentry_v[head1] <= `INV;
|
iqentry_v[head1] <= `INV;
|
iqentry_iv[head1] <= `INV;
|
|
iqentry_alu[head1] <= `INV;
|
|
head_inc(2);
|
head_inc(2);
|
end
|
end
|
|
else begin
|
// retire 0 (stuck on head0)
|
head_inc(1);
|
4'b10_??: ;
|
end
|
|
6'b0?_11_11:
|
// retire 1 or 2
|
if (`NUM_CMT > 2 || (`NUM_CMT > 1 && iqentry_tgt[head2] == 12'd0)) begin
|
4'b11_0?:
|
iqentry_v[head1] <= `INV;
|
|
iqentry_v[head2] <= `INV;
|
|
head_inc(3);
|
|
end
|
|
else if (`NUM_CMT > 1 || iqentry_tgt[head1]==12'd0) begin
|
|
iqentry_v[head1] <= `INV;
|
|
head_inc(2);
|
|
end
|
|
else
|
|
head_inc(1);
|
|
6'b10_??_??: ;
|
|
6'b11_0?_0?:
|
|
if (head1 != tail0 && head2 != tail0) begin
|
|
iqentry_v[head0] <= `INV;
|
|
head_inc(3);
|
|
end
|
|
else if (head1 != tail0) begin
|
|
iqentry_v[head0] <= `INV;
|
|
head_inc(2);
|
|
end
|
|
else begin
|
|
iqentry_v[head0] <= `INV;
|
|
head_inc(1);
|
|
end
|
|
6'b11_0?_10:
|
if (head1 != tail0) begin
|
if (head1 != tail0) begin
|
iqentry_v[head0] <= `INV;
|
iqentry_v[head0] <= `INV;
|
iqentry_iv[head0] <= `INV;
|
|
iqentry_alu[head0] <= `INV;
|
|
head_inc(2);
|
head_inc(2);
|
end
|
end
|
else begin
|
else begin
|
iqentry_v[head0] <= `INV;
|
iqentry_v[head0] <= `INV;
|
iqentry_iv[head0] <= `INV;
|
|
iqentry_alu[head0] <= `INV;
|
|
head_inc(1);
|
head_inc(1);
|
end
|
end
|
|
6'b11_0?_11:
|
// retire 1 (wait for regfile for head1)
|
if (head1 != tail0) begin
|
4'b11_10:
|
if (`NUM_CMT > 2 || iqentry_tgt[head2]==12'd0) begin
|
begin
|
iqentry_v[head0] <= `INV;
|
|
iqentry_v[head2] <= `INV;
|
|
head_inc(3);
|
|
end
|
|
else begin
|
|
iqentry_v[head0] <= `INV;
|
|
head_inc(2);
|
|
end
|
|
end
|
|
else begin
|
iqentry_v[head0] <= `INV;
|
iqentry_v[head0] <= `INV;
|
iqentry_iv[head0] <= `INV;
|
|
iqentry_alu[head0] <= `INV;
|
|
head_inc(1);
|
head_inc(1);
|
end
|
end
|
|
6'b11_10_??:
|
// retire 2
|
|
4'b11_11:
|
|
begin
|
begin
|
iqentry_v[head0] <= `INV; // may conflict with STOMP, but since both are setting to 0, it is okay
|
iqentry_v[head0] <= `INV;
|
iqentry_v[head1] <= `INV; // may conflict with STOMP, but since both are setting to 0, it is okay
|
head_inc(1);
|
iqentry_iv[head0] <= `INV;
|
end
|
iqentry_iv[head1] <= `INV;
|
6'b11_11_0?:
|
iqentry_alu[head0] <= `INV;
|
if (`NUM_CMT > 1 && head2 != tail0) begin
|
iqentry_alu[head1] <= `INV;
|
iqentry_v[head0] <= `INV;
|
|
iqentry_v[head1] <= `INV;
|
|
head_inc(3);
|
|
end
|
|
else if (iqentry_tgt[head1]== 12'd0 && head2 != tail0) begin
|
|
iqentry_v[head0] <= `INV;
|
|
iqentry_v[head1] <= `INV;
|
|
head_inc(3);
|
|
end
|
|
else if (`NUM_CMT > 1 || iqentry_tgt[head1]==12'd0) begin
|
|
iqentry_v[head0] <= `INV;
|
|
iqentry_v[head1] <= `INV;
|
|
head_inc(2);
|
|
end
|
|
else begin
|
|
iqentry_v[head0] <= `INV;
|
|
head_inc(1);
|
|
end
|
|
6'b11_11_10:
|
|
if (`NUM_CMT > 1 || iqentry_tgt[head1]==12'd0) begin
|
|
iqentry_v[head0] <= `INV;
|
|
iqentry_v[head1] <= `INV;
|
|
head_inc(2);
|
|
end
|
|
else begin
|
|
iqentry_v[head0] <= `INV;
|
|
head_inc(1);
|
|
end
|
|
6'b11_11_11:
|
|
if (`NUM_CMT > 2 || (`NUM_CMT > 1 && iqentry_tgt[head2]==12'd0)) begin
|
|
iqentry_v[head0] <= `INV;
|
|
iqentry_v[head1] <= `INV;
|
|
iqentry_v[head2] <= `INV;
|
|
head_inc(3);
|
|
end
|
|
else if (`NUM_CMT > 1 || iqentry_tgt[head1]==12'd0) begin
|
|
iqentry_v[head0] <= `INV;
|
|
iqentry_v[head1] <= `INV;
|
head_inc(2);
|
head_inc(2);
|
end
|
end
|
|
else begin
|
|
iqentry_v[head0] <= `INV;
|
|
head_inc(1);
|
|
end
|
endcase
|
endcase
|
|
|
|
|
rf_source[0] <= 0;
|
rf_source[0] <= 0;
|
L1_wr0 <= FALSE;
|
L1_wr0 <= FALSE;
|
| Line 7030... |
Line 7775... |
if (bstate != B7 && bstate != B9) begin
|
if (bstate != B7 && bstate != B9) begin
|
if (!ihit0) begin
|
if (!ihit0) begin
|
L1_adr <= {pcr[5:0],pc0[31:3],3'h0};
|
L1_adr <= {pcr[5:0],pc0[31:3],3'h0};
|
L2_adr <= {pcr[5:0],pc0[31:3],3'h0};
|
L2_adr <= {pcr[5:0],pc0[31:3],3'h0};
|
L1_invline <= TRUE;
|
L1_invline <= TRUE;
|
icwhich <= 1'b0;
|
icwhich <= 2'b00;
|
iccnt <= 3'b00;
|
iccnt <= 3'b00;
|
icstate <= IC2;
|
icstate <= IC2;
|
end
|
end
|
else if (!ihit1) begin
|
else if (!ihit1 && `WAYS > 1) begin
|
`ifdef SUPPORT_SMT
|
`ifdef SUPPORT_SMT
|
L1_adr <= {pcr[5:0],pc1[31:3],3'h0};
|
L1_adr <= {pcr[5:0],pc1[31:3],3'h0};
|
L2_adr <= {pcr[5:0],pc1[31:3],3'h0};
|
L2_adr <= {pcr[5:0],pc1[31:3],3'h0};
|
`else
|
`else
|
L1_adr <= {pcr[5:0],pc0plus6[31:3],3'h0};
|
L1_adr <= {pcr[5:0],pc0plus6[31:3],3'h0};
|
L2_adr <= {pcr[5:0],pc0plus6[31:3],3'h0};
|
L2_adr <= {pcr[5:0],pc0plus6[31:3],3'h0};
|
`endif
|
`endif
|
L1_invline <= TRUE;
|
L1_invline <= TRUE;
|
icwhich <= 1'b1;
|
icwhich <= 2'b01;
|
|
iccnt <= 3'b00;
|
|
icstate <= IC2;
|
|
end
|
|
else if (!ihit2 && `WAYS > 2) begin
|
|
`ifdef SUPPORT_SMT
|
|
L1_adr <= {pcr[5:0],pc2[31:3],3'h0};
|
|
L2_adr <= {pcr[5:0],pc2[31:3],3'h0};
|
|
`else
|
|
L1_adr <= {pcr[5:0],pc0plus12[31:3],3'h0};
|
|
L2_adr <= {pcr[5:0],pc0plus12[31:3],3'h0};
|
|
`endif
|
|
L1_invline <= TRUE;
|
|
icwhich <= 2'b10;
|
iccnt <= 3'b00;
|
iccnt <= 3'b00;
|
icstate <= IC2;
|
icstate <= IC2;
|
end
|
end
|
end
|
end
|
IC2: icstate <= IC3;
|
IC2: icstate <= IC3;
|
| Line 7058... |
Line 7816... |
// already active when this state was entered in which case waiting
|
// already active when this state was entered in which case waiting
|
// will do no good.
|
// will do no good.
|
// The IC machine will stall in this state until the BIU has loaded the
|
// The IC machine will stall in this state until the BIU has loaded the
|
// L2 cache.
|
// L2 cache.
|
IC4:
|
IC4:
|
if (ihit2 && picstate==IC3a) begin
|
if (ihitL2 && picstate==IC3a) begin
|
L1_en <= 10'h3FF;
|
L1_en <= 9'h1FF;
|
L1_wr1 <= TRUE;
|
|
L1_wr0 <= TRUE;
|
L1_wr0 <= TRUE;
|
|
L1_wr1 <= TRUE && `WAYS > 1;
|
|
L1_wr2 <= TRUE && `WAYS > 2;
|
L1_adr <= L2_adr;
|
L1_adr <= L2_adr;
|
L2_rdat <= L2_dato;
|
L2_rdat <= L2_dato;
|
icstate <= IC5;
|
icstate <= IC5;
|
end
|
end
|
else if (bstate!=B9)
|
else if (bstate!=B9)
|
;
|
;
|
else begin
|
else begin
|
L1_en <= 10'h3FF;
|
L1_en <= 9'h1FF;
|
L1_wr1 <= TRUE;
|
|
L1_wr0 <= TRUE;
|
L1_wr0 <= TRUE;
|
|
L1_wr1 <= TRUE && `WAYS > 1;
|
|
L1_wr2 <= TRUE && `WAYS > 2;
|
L1_adr <= L2_adr;
|
L1_adr <= L2_adr;
|
L2_rdat <= L2_dato;
|
L2_rdat <= L2_dato;
|
icstate <= IC5;
|
icstate <= IC5;
|
end
|
end
|
IC5:
|
IC5:
|
begin
|
begin
|
L1_en <= 10'h000;
|
L1_en <= 9'h000;
|
L1_wr0 <= FALSE;
|
L1_wr0 <= FALSE;
|
L1_wr1 <= FALSE;
|
L1_wr1 <= FALSE;
|
|
L1_wr2 <= FALSE;
|
icstate <= IC6;
|
icstate <= IC6;
|
end
|
end
|
IC6: icstate <= IC7;
|
IC6: icstate <= IC7;
|
IC7: icstate <= IC8;
|
IC7: icstate <= IC8;
|
IC8: begin
|
IC8: begin
|
| Line 7092... |
Line 7853... |
icnxt <= TRUE;
|
icnxt <= TRUE;
|
end
|
end
|
default: icstate <= IDLE;
|
default: icstate <= IDLE;
|
endcase
|
endcase
|
|
|
if (dram0_load)
|
if (mem1_available && dram0_load)
|
case(dram0)
|
case(dram0)
|
`DRAMSLOT_AVAIL: ;
|
`DRAMSLOT_AVAIL: ;
|
`DRAMSLOT_BUSY: dram0 <= dram0 + !dram0_unc;
|
`DRAMSLOT_BUSY: dram0 <= dram0 + !dram0_unc;
|
3'd2: dram0 <= dram0 + 3'd1;
|
3'd2: dram0 <= dram0 + 3'd1;
|
3'd3: dram0 <= dram0 + 3'd1;
|
3'd3: dram0 <= dram0 + 3'd1;
|
| Line 7104... |
Line 7865... |
`DRAMSLOT_REQBUS: ;
|
`DRAMSLOT_REQBUS: ;
|
`DRAMSLOT_HASBUS: ;
|
`DRAMSLOT_HASBUS: ;
|
`DRAMREQ_READY: ;
|
`DRAMREQ_READY: ;
|
endcase
|
endcase
|
|
|
if (dram1_load)
|
if (mem2_available && dram1_load && `NUM_MEM > 1)
|
case(dram1)
|
case(dram1)
|
`DRAMSLOT_AVAIL: ;
|
`DRAMSLOT_AVAIL: ;
|
`DRAMSLOT_BUSY: dram1 <= dram1 + !dram1_unc;
|
`DRAMSLOT_BUSY: dram1 <= dram1 + !dram1_unc;
|
3'd2: dram1 <= dram1 + 3'd1;
|
3'd2: dram1 <= dram1 + 3'd1;
|
3'd3: dram1 <= dram1 + 3'd1;
|
3'd3: dram1 <= dram1 + 3'd1;
|
| Line 7116... |
Line 7877... |
`DRAMSLOT_REQBUS: ;
|
`DRAMSLOT_REQBUS: ;
|
`DRAMSLOT_HASBUS: ;
|
`DRAMSLOT_HASBUS: ;
|
`DRAMREQ_READY: ;
|
`DRAMREQ_READY: ;
|
endcase
|
endcase
|
|
|
if (dram2_load)
|
if (mem3_available && dram2_load && `NUM_MEM > 2)
|
case(dram2)
|
case(dram2)
|
`DRAMSLOT_AVAIL: ;
|
`DRAMSLOT_AVAIL: ;
|
`DRAMSLOT_BUSY: dram2 <= dram2 + !dram2_unc;
|
`DRAMSLOT_BUSY: dram2 <= dram2 + !dram2_unc;
|
3'd2: dram2 <= dram2 + 3'd1;
|
3'd2: dram2 <= dram2 + 3'd1;
|
3'd3: dram2 <= dram2 + 3'd1;
|
3'd3: dram2 <= dram2 + 3'd1;
|
| Line 7146... |
Line 7907... |
isSpt <= FALSE;
|
isSpt <= FALSE;
|
isRMW <= FALSE;
|
isRMW <= FALSE;
|
rdvq <= 1'b0;
|
rdvq <= 1'b0;
|
errq <= 1'b0;
|
errq <= 1'b0;
|
exvq <= 1'b0;
|
exvq <= 1'b0;
|
bwhich <= 2'b11;
|
bwhich <= 2'b00;
|
preload <= FALSE;
|
preload <= FALSE;
|
if (dram0==`DRAMSLOT_BUSY && dram0_rmw) begin
|
`ifdef HAS_WB
|
|
if (wb_v[0] & wb_en) begin
|
|
cyc_o <= `HIGH;
|
|
stb_o <= `HIGH;
|
|
we_o <= `HIGH;
|
|
sel_o <= wb_sel[0];
|
|
adr_o <= wb_addr[0];
|
|
dat_o <= wb_data[0];
|
|
ol_o <= wb_ol[0];
|
|
wbo_id <= wb_id[0];
|
|
bstate <= wb_rmw[0] ? B12 : B1;
|
|
end
|
|
begin
|
|
for (j = 1; j < `WB_DEPTH; j = j + 1) begin
|
|
wb_v[j-1] <= wb_v[j];
|
|
wb_id[j-1] <= wb_id[j];
|
|
wb_rmw[j-1] <= wb_rmw[j];
|
|
wb_sel[j-1] <= wb_sel[j];
|
|
wb_addr[j-1] <= wb_addr[j];
|
|
wb_data[j-1] <= wb_data[j];
|
|
wb_ol[j-1] <= wb_ol[j];
|
|
end
|
|
wb_v[`WB_DEPTH-1] <= `INV;
|
|
wb_rmw[`WB_DEPTH-1] <= `FALSE;
|
|
end
|
|
|
|
// if (|wb_v)
|
|
// ;
|
|
// else
|
|
`endif
|
|
if (~|wb_v && mem1_available && dram0==`DRAMSLOT_BUSY && dram0_rmw) begin
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
if (dbg_smatch0|dbg_lmatch0) begin
|
if (dbg_smatch0|dbg_lmatch0) begin
|
dramA_v <= `TRUE;
|
dramA_v <= `TRUE;
|
dramA_id <= dram0_id;
|
dramA_id <= dram0_id;
|
dramA_exc <= `FLT_DBG;
|
dramA_exc <= `FLT_DBG;
|
| Line 7160... |
Line 7951... |
dram0 <= `DRAMSLOT_AVAIL;
|
dram0 <= `DRAMSLOT_AVAIL;
|
end
|
end
|
else
|
else
|
`endif
|
`endif
|
begin
|
begin
|
dram0 <= `DRAMSLOT_HASBUS;
|
|
isRMW <= dram0_rmw;
|
isRMW <= dram0_rmw;
|
isCAS <= IsCAS(dram0_instr);
|
isCAS <= IsCAS(dram0_instr);
|
isAMO <= IsAMO(dram0_instr);
|
isAMO <= IsAMO(dram0_instr);
|
isInc <= IsInc(dram0_instr);
|
isInc <= IsInc(dram0_instr);
|
casid <= dram0_id;
|
casid <= dram0_id;
|
bwhich <= 2'b00;
|
bwhich <= 2'b00;
|
|
dram0 <= `DRAMSLOT_HASBUS;
|
cyc_o <= `HIGH;
|
cyc_o <= `HIGH;
|
stb_o <= `HIGH;
|
stb_o <= `HIGH;
|
sel_o <= fnSelect(dram0_instr,dram0_addr);
|
sel_o <= fnSelect(dram0_instr,dram0_addr);
|
adr_o <= dram0_addr;
|
adr_o <= dram0_addr;
|
dat_o <= fnDato(dram0_instr,dram0_data);
|
dat_o <= fnDato(dram0_instr,dram0_data);
|
ol_o <= dram0_ol;
|
ol_o <= dram0_ol;
|
bstate <= B12;
|
bstate <= B12;
|
end
|
end
|
end
|
end
|
else if (dram1==`DRAMSLOT_BUSY && dram1_rmw) begin
|
else if (~|wb_v && mem2_available && dram1==`DRAMSLOT_BUSY && dram1_rmw && `NUM_MEM > 1) begin
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
if (dbg_smatch1|dbg_lmatch1) begin
|
if (dbg_smatch1|dbg_lmatch1) begin
|
dramB_v <= `TRUE;
|
dramB_v <= `TRUE;
|
dramB_id <= dram1_id;
|
dramB_id <= dram1_id;
|
dramB_exc <= `FLT_DBG;
|
dramB_exc <= `FLT_DBG;
|
| Line 7188... |
Line 7979... |
dram1 <= `DRAMSLOT_AVAIL;
|
dram1 <= `DRAMSLOT_AVAIL;
|
end
|
end
|
else
|
else
|
`endif
|
`endif
|
begin
|
begin
|
dram1 <= `DRAMSLOT_HASBUS;
|
|
isRMW <= dram1_rmw;
|
isRMW <= dram1_rmw;
|
isCAS <= IsCAS(dram1_instr);
|
isCAS <= IsCAS(dram1_instr);
|
isAMO <= IsAMO(dram1_instr);
|
isAMO <= IsAMO(dram1_instr);
|
isInc <= IsInc(dram1_instr);
|
isInc <= IsInc(dram1_instr);
|
casid <= dram1_id;
|
casid <= dram1_id;
|
bwhich <= 2'b01;
|
bwhich <= 2'b01;
|
|
dram1 <= `DRAMSLOT_HASBUS;
|
cyc_o <= `HIGH;
|
cyc_o <= `HIGH;
|
stb_o <= `HIGH;
|
stb_o <= `HIGH;
|
sel_o <= fnSelect(dram1_instr,dram1_addr);
|
sel_o <= fnSelect(dram1_instr,dram1_addr);
|
adr_o <= dram1_addr;
|
adr_o <= dram1_addr;
|
dat_o <= fnDato(dram1_instr,dram1_data);
|
dat_o <= fnDato(dram1_instr,dram1_data);
|
ol_o <= dram1_ol;
|
ol_o <= dram1_ol;
|
bstate <= B12;
|
bstate <= B12;
|
end
|
end
|
end
|
end
|
else if (dram2==`DRAMSLOT_BUSY && dram2_rmw) begin
|
else if (~|wb_v && mem3_available && dram2==`DRAMSLOT_BUSY && dram2_rmw && `NUM_MEM > 2) begin
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
if (dbg_smatch2|dbg_lmatch2) begin
|
if (dbg_smatch2|dbg_lmatch2) begin
|
dramC_v <= `TRUE;
|
dramC_v <= `TRUE;
|
dramC_id <= dram2_id;
|
dramC_id <= dram2_id;
|
dramC_exc <= `FLT_DBG;
|
dramC_exc <= `FLT_DBG;
|
| Line 7216... |
Line 8007... |
dram2 <= `DRAMSLOT_AVAIL;
|
dram2 <= `DRAMSLOT_AVAIL;
|
end
|
end
|
else
|
else
|
`endif
|
`endif
|
begin
|
begin
|
dram2 <= `DRAMSLOT_HASBUS;
|
|
isRMW <= dram2_rmw;
|
isRMW <= dram2_rmw;
|
isCAS <= IsCAS(dram2_instr);
|
isCAS <= IsCAS(dram2_instr);
|
isAMO <= IsAMO(dram2_instr);
|
isAMO <= IsAMO(dram2_instr);
|
isInc <= IsInc(dram2_instr);
|
isInc <= IsInc(dram2_instr);
|
casid <= dram2_id;
|
casid <= dram2_id;
|
bwhich <= 2'b10;
|
bwhich <= 2'b10;
|
|
dram2 <= `DRAMSLOT_HASBUS;
|
cyc_o <= `HIGH;
|
cyc_o <= `HIGH;
|
stb_o <= `HIGH;
|
stb_o <= `HIGH;
|
sel_o <= fnSelect(dram2_instr,dram2_addr);
|
sel_o <= fnSelect(dram2_instr,dram2_addr);
|
adr_o <= dram2_addr;
|
adr_o <= dram2_addr;
|
dat_o <= fnDato(dram2_instr,dram2_data);
|
dat_o <= fnDato(dram2_instr,dram2_data);
|
ol_o <= dram2_ol;
|
ol_o <= dram2_ol;
|
bstate <= B12;
|
bstate <= B12;
|
end
|
end
|
end
|
end
|
else if (dram0==`DRAMSLOT_BUSY && IsStore(dram0_instr)) begin
|
else if (mem1_available && dram0==`DRAMSLOT_BUSY && IsStore(dram0_instr)) begin
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
if (dbg_smatch0) begin
|
if (dbg_smatch0) begin
|
dramA_v <= `TRUE;
|
dramA_v <= `TRUE;
|
dramA_id <= dram0_id;
|
dramA_id <= dram0_id;
|
dramA_exc <= `FLT_DBG;
|
dramA_exc <= `FLT_DBG;
|
| Line 7244... |
Line 8035... |
dram0 <= `DRAMSLOT_AVAIL;
|
dram0 <= `DRAMSLOT_AVAIL;
|
end
|
end
|
else
|
else
|
`endif
|
`endif
|
begin
|
begin
|
|
bwhich <= 2'b00;
|
|
`ifndef HAS_WB
|
dram0 <= `DRAMSLOT_HASBUS;
|
dram0 <= `DRAMSLOT_HASBUS;
|
dram0_instr[`INSTRUCTION_OP] <= `NOP;
|
dram0_instr[`INSTRUCTION_OP] <= `NOP;
|
bwhich <= 2'b00;
|
|
cyc_o <= `HIGH;
|
cyc_o <= `HIGH;
|
stb_o <= `HIGH;
|
stb_o <= `HIGH;
|
we_o <= `HIGH;
|
|
sel_o <= fnSelect(dram0_instr,dram0_addr);
|
sel_o <= fnSelect(dram0_instr,dram0_addr);
|
adr_o <= dram0_addr;
|
adr_o <= dram0_addr;
|
dat_o <= fnDato(dram0_instr,dram0_data);
|
dat_o <= fnDato(dram0_instr,dram0_data);
|
cr_o <= IsSWC(dram0_instr);
|
|
ol_o <= dram0_ol;
|
ol_o <= dram0_ol;
|
bstate <= B1;
|
bstate <= B1;
|
|
`else
|
|
if (wbptr<`WB_DEPTH-1) begin
|
|
dram0 <= `DRAMREQ_READY;
|
|
dram0_instr[`INSTRUCTION_OP] <= `NOP;
|
|
wb_update(
|
|
dram0_id,
|
|
`FALSE,
|
|
fnSelect(dram0_instr,dram0_addr),
|
|
dram0_ol,
|
|
dram0_addr,
|
|
fnDato(dram0_instr,dram0_data)
|
|
);
|
|
iqentry_done[ dram0_id[`QBITS] ] <= `VAL;
|
|
iqentry_out[ dram0_id[`QBITS] ] <= `INV;
|
|
end
|
|
`endif
|
|
// cr_o <= IsSWC(dram0_instr);
|
end
|
end
|
end
|
end
|
else if (dram1==`DRAMSLOT_BUSY && IsStore(dram1_instr)) begin
|
else if (mem2_available && dram1==`DRAMSLOT_BUSY && IsStore(dram1_instr) && `NUM_MEM > 1) begin
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
if (dbg_smatch1) begin
|
if (dbg_smatch1) begin
|
dramB_v <= `TRUE;
|
dramB_v <= `TRUE;
|
dramB_id <= dram1_id;
|
dramB_id <= dram1_id;
|
dramB_exc <= `FLT_DBG;
|
dramB_exc <= `FLT_DBG;
|
| Line 7270... |
Line 8077... |
dram1 <= `DRAMSLOT_AVAIL;
|
dram1 <= `DRAMSLOT_AVAIL;
|
end
|
end
|
else
|
else
|
`endif
|
`endif
|
begin
|
begin
|
|
bwhich <= 2'b01;
|
|
`ifndef HAS_WB
|
dram1 <= `DRAMSLOT_HASBUS;
|
dram1 <= `DRAMSLOT_HASBUS;
|
dram1_instr[`INSTRUCTION_OP] <= `NOP;
|
dram1_instr[`INSTRUCTION_OP] <= `NOP;
|
bwhich <= 2'b01;
|
|
cyc_o <= `HIGH;
|
cyc_o <= `HIGH;
|
stb_o <= `HIGH;
|
stb_o <= `HIGH;
|
we_o <= `HIGH;
|
|
sel_o <= fnSelect(dram1_instr,dram1_addr);
|
sel_o <= fnSelect(dram1_instr,dram1_addr);
|
adr_o <= dram1_addr;
|
adr_o <= dram1_addr;
|
dat_o <= fnDato(dram1_instr,dram1_data);
|
dat_o <= fnDato(dram1_instr,dram1_data);
|
cr_o <= IsSWC(dram1_instr);
|
|
ol_o <= dram1_ol;
|
ol_o <= dram1_ol;
|
bstate <= B1;
|
bstate <= B1;
|
|
`else
|
|
if (wbptr<`WB_DEPTH-1) begin
|
|
dram1 <= `DRAMREQ_READY;
|
|
dram1_instr[`INSTRUCTION_OP] <= `NOP;
|
|
wb_update(
|
|
dram1_id,
|
|
`FALSE,
|
|
fnSelect(dram1_instr,dram1_addr),
|
|
dram1_ol,
|
|
dram1_addr,
|
|
fnDato(dram1_instr,dram1_data)
|
|
);
|
|
iqentry_done[ dram1_id[`QBITS] ] <= `VAL;
|
|
iqentry_out[ dram1_id[`QBITS] ] <= `INV;
|
|
end
|
|
`endif
|
|
// cr_o <= IsSWC(dram0_instr);
|
end
|
end
|
end
|
end
|
else if (dram2==`DRAMSLOT_BUSY && IsStore(dram2_instr)) begin
|
else if (mem3_available && dram2==`DRAMSLOT_BUSY && IsStore(dram2_instr) && `NUM_MEM > 2) begin
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
if (dbg_smatch2) begin
|
if (dbg_smatch2) begin
|
dramC_v <= `TRUE;
|
dramC_v <= `TRUE;
|
dramC_id <= dram2_id;
|
dramC_id <= dram2_id;
|
dramC_exc <= `FLT_DBG;
|
dramC_exc <= `FLT_DBG;
|
| Line 7296... |
Line 8119... |
dram2 <= `DRAMSLOT_AVAIL;
|
dram2 <= `DRAMSLOT_AVAIL;
|
end
|
end
|
else
|
else
|
`endif
|
`endif
|
begin
|
begin
|
|
bwhich <= 2'b10;
|
|
`ifndef HAS_WB
|
dram2 <= `DRAMSLOT_HASBUS;
|
dram2 <= `DRAMSLOT_HASBUS;
|
dram2_instr[`INSTRUCTION_OP] <= `NOP;
|
dram2_instr[`INSTRUCTION_OP] <= `NOP;
|
bwhich <= 2'b10;
|
|
cyc_o <= `HIGH;
|
cyc_o <= `HIGH;
|
stb_o <= `HIGH;
|
stb_o <= `HIGH;
|
we_o <= `HIGH;
|
|
sel_o <= fnSelect(dram2_instr,dram2_addr);
|
sel_o <= fnSelect(dram2_instr,dram2_addr);
|
adr_o <= dram2_addr;
|
adr_o <= dram2_addr;
|
dat_o <= fnDato(dram2_instr,dram2_data);
|
dat_o <= fnDato(dram2_instr,dram2_data);
|
cr_o <= IsSWC(dram2_instr);
|
|
ol_o <= dram2_ol;
|
ol_o <= dram2_ol;
|
bstate <= B1;
|
bstate <= B1;
|
|
`else
|
|
if (wbptr<`WB_DEPTH-1) begin
|
|
dram2 <= `DRAMREQ_READY;
|
|
dram2_instr[`INSTRUCTION_OP] <= `NOP;
|
|
wb_update(
|
|
dram2_id,
|
|
`FALSE,
|
|
fnSelect(dram2_instr,dram2_addr),
|
|
dram2_ol,
|
|
dram2_addr,
|
|
fnDato(dram2_instr,dram2_data)
|
|
);
|
|
iqentry_done[ dram2_id[`QBITS] ] <= `VAL;
|
|
iqentry_out[ dram2_id[`QBITS] ] <= `INV;
|
|
end
|
|
`endif
|
|
// cr_o <= IsSWC(dram0_instr);
|
end
|
end
|
end
|
end
|
// Check for read misses on the data cache
|
// Check for read misses on the data cache
|
else if (!dram0_unc && dram0==`DRAMSLOT_REQBUS && dram0_load) begin
|
else if (mem1_available && !dram0_unc && dram0==`DRAMSLOT_REQBUS && dram0_load) begin
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
if (dbg_lmatch0) begin
|
if (dbg_lmatch0) begin
|
dramA_v <= `TRUE;
|
dramA_v <= `TRUE;
|
dramA_id <= dram0_id;
|
dramA_id <= dram0_id;
|
dramA_exc <= `FLT_DBG;
|
dramA_exc <= `FLT_DBG;
|
| Line 7329... |
Line 8168... |
bwhich <= 2'b00;
|
bwhich <= 2'b00;
|
preload <= dram0_preload;
|
preload <= dram0_preload;
|
bstate <= B2;
|
bstate <= B2;
|
end
|
end
|
end
|
end
|
else if (!dram1_unc && dram1==`DRAMSLOT_REQBUS && dram1_load) begin
|
else if (~|wb_v && mem2_available && !dram1_unc && dram1==`DRAMSLOT_REQBUS && dram1_load && `NUM_MEM > 1) begin
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
if (dbg_lmatch1) begin
|
if (dbg_lmatch1) begin
|
dramB_v <= `TRUE;
|
dramB_v <= `TRUE;
|
dramB_id <= dram1_id;
|
dramB_id <= dram1_id;
|
dramB_exc <= `FLT_DBG;
|
dramB_exc <= `FLT_DBG;
|
| Line 7347... |
Line 8186... |
bwhich <= 2'b01;
|
bwhich <= 2'b01;
|
preload <= dram1_preload;
|
preload <= dram1_preload;
|
bstate <= B2;
|
bstate <= B2;
|
end
|
end
|
end
|
end
|
else if (!dram2_unc && dram2==`DRAMSLOT_REQBUS && dram2_load) begin
|
else if (~|wb_v && mem3_available && !dram2_unc && dram2==`DRAMSLOT_REQBUS && dram2_load && `NUM_MEM > 2) begin
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
if (dbg_lmatch2) begin
|
if (dbg_lmatch2) begin
|
dramC_v <= `TRUE;
|
dramC_v <= `TRUE;
|
dramC_id <= dram2_id;
|
dramC_id <= dram2_id;
|
dramC_exc <= `FLT_DBG;
|
dramC_exc <= `FLT_DBG;
|
| Line 7365... |
Line 8204... |
preload <= dram2_preload;
|
preload <= dram2_preload;
|
bwhich <= 2'b10;
|
bwhich <= 2'b10;
|
bstate <= B2;
|
bstate <= B2;
|
end
|
end
|
end
|
end
|
else if (dram0_unc && dram0==`DRAMSLOT_BUSY && dram0_load) begin
|
else if (~|wb_v && mem1_available && dram0_unc && dram0==`DRAMSLOT_BUSY && dram0_load) begin
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
if (dbg_lmatch0) begin
|
if (dbg_lmatch0) begin
|
dramA_v <= `TRUE;
|
dramA_v <= `TRUE;
|
dramA_id <= dram0_id;
|
dramA_id <= dram0_id;
|
dramA_exc <= `FLT_DBG;
|
dramA_exc <= `FLT_DBG;
|
| Line 7387... |
Line 8226... |
sr_o <= IsLWR(dram0_instr);
|
sr_o <= IsLWR(dram0_instr);
|
ol_o <= dram0_ol;
|
ol_o <= dram0_ol;
|
bstate <= B12;
|
bstate <= B12;
|
end
|
end
|
end
|
end
|
else if (dram1_unc && dram1==`DRAMSLOT_BUSY && dram1_load) begin
|
else if (~|wb_v && mem2_available && dram1_unc && dram1==`DRAMSLOT_BUSY && dram1_load && `NUM_MEM > 1) begin
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
if (dbg_lmatch1) begin
|
if (dbg_lmatch1) begin
|
dramB_v <= `TRUE;
|
dramB_v <= `TRUE;
|
dramB_id <= dram1_id;
|
dramB_id <= dram1_id;
|
dramB_exc <= `FLT_DBG;
|
dramB_exc <= `FLT_DBG;
|
| Line 7409... |
Line 8248... |
sr_o <= IsLWR(dram1_instr);
|
sr_o <= IsLWR(dram1_instr);
|
ol_o <= dram1_ol;
|
ol_o <= dram1_ol;
|
bstate <= B12;
|
bstate <= B12;
|
end
|
end
|
end
|
end
|
else if (dram2_unc && dram2==`DRAMSLOT_BUSY && dram2_load) begin
|
else if (~|wb_v && mem3_available && dram2_unc && dram2==`DRAMSLOT_BUSY && dram2_load && `NUM_MEM > 2) begin
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
if (dbg_lmatch2) begin
|
if (dbg_lmatch2) begin
|
dramC_v <= `TRUE;
|
dramC_v <= `TRUE;
|
dramC_id <= dram2_id;
|
dramC_id <= dram2_id;
|
dramC_exc <= `FLT_DBG;
|
dramC_exc <= `FLT_DBG;
|
| Line 7432... |
Line 8271... |
ol_o <= dram2_ol;
|
ol_o <= dram2_ol;
|
bstate <= B12;
|
bstate <= B12;
|
end
|
end
|
end
|
end
|
// Check for L2 cache miss
|
// Check for L2 cache miss
|
else if (!ihit2) begin
|
else if (~|wb_v && !ihitL2) begin
|
cti_o <= 3'b001;
|
cti_o <= 3'b001;
|
bte_o <= 2'b01; // 4 beat burst wrap
|
bte_o <= 2'b00;//2'b01; // 4 beat burst wrap
|
cyc_o <= `HIGH;
|
cyc_o <= `HIGH;
|
stb_o <= `HIGH;
|
stb_o <= `HIGH;
|
sel_o <= 8'hFF;
|
sel_o <= 8'hFF;
|
icl_o <= `HIGH;
|
icl_o <= `HIGH;
|
|
iccnt <= 3'd0;
|
// adr_o <= icwhich ? {pc0[31:5],5'b0} : {pc1[31:5],5'b0};
|
// adr_o <= icwhich ? {pc0[31:5],5'b0} : {pc1[31:5],5'b0};
|
// L2_adr <= icwhich ? {pc0[31:5],5'b0} : {pc1[31:5],5'b0};
|
// L2_adr <= icwhich ? {pc0[31:5],5'b0} : {pc1[31:5],5'b0};
|
adr_o <= {pcr[5:0],L1_adr[31:5],5'h0};
|
adr_o <= {pcr[5:0],L1_adr[31:5],5'h0};
|
ol_o <= ol[0];
|
ol_o <= ol[0];
|
L2_adr <= {pcr[5:0],L1_adr[31:5],5'h0};
|
L2_adr <= {pcr[5:0],L1_adr[31:5],5'h0};
|
L2_xsel <= 1'b0;
|
L2_xsel <= 1'b0;
|
bstate <= B7;
|
bstate <= B7;
|
end
|
end
|
end
|
end
|
// Terminal state for a store operation.
|
// Terminal state for a store operation.
|
|
// Note that if only a single memory channel is selected, bwhich will be a
|
|
// constant 0. This should cause the extra code to be removed.
|
B1:
|
B1:
|
if (acki|err_i) begin
|
if (acki|err_i) begin
|
isStore <= `TRUE;
|
isStore <= `TRUE;
|
cyc_o <= `LOW;
|
cyc_o <= `LOW;
|
stb_o <= `LOW;
|
stb_o <= `LOW;
|
| Line 7465... |
Line 8307... |
// here. The author wanted to avoid the complexity of propagating the
|
// here. The author wanted to avoid the complexity of propagating the
|
// input signal to the commit stage. It does mean that the SWC
|
// input signal to the commit stage. It does mean that the SWC
|
// instruction should be surrounded by SYNC's.
|
// instruction should be surrounded by SYNC's.
|
if (cr_o)
|
if (cr_o)
|
sema[0] <= rbi_i;
|
sema[0] <= rbi_i;
|
|
`ifdef HAS_WB
|
|
for (n = 0; n < QENTRIES; n = n + 1) begin
|
|
if (wbo_id[n]) begin
|
|
iqentry_exc[n] <= wrv_i|err_i ? `FLT_DWF : `FLT_NONE;
|
|
if (err_i|wrv_i) begin
|
|
iqentry_a1[n] <= adr_o;
|
|
wb_v <= 8'h00; // Invalidate write buffer if there is a problem with the store
|
|
wb_en <= `FALSE; // and disable write buffer
|
|
end
|
|
iqentry_cmt[n] <= `VAL;
|
|
iqentry_aq[n] <= `INV;
|
|
end
|
|
end
|
|
`else
|
case(bwhich)
|
case(bwhich)
|
2'd0: begin
|
2'd0: if (mem1_available) begin
|
dram0 <= `DRAMREQ_READY;
|
dram0 <= `DRAMREQ_READY;
|
iqentry_exc[dram0_id[`QBITS]] <= wrv_i|err_i ? `FLT_DWF : `FLT_NONE;
|
iqentry_exc[dram0_id[`QBITS]] <= wrv_i|err_i ? `FLT_DWF : `FLT_NONE;
|
if (err_i|wrv_i) iqentry_a1[dram0_id[`QBITS]] <= adr_o;
|
if (err_i|wrv_i) iqentry_a1[dram0_id[`QBITS]] <= adr_o;
|
iqentry_cmt[ dram0_id[`QBITS] ] <= `VAL;
|
iqentry_cmt[ dram0_id[`QBITS] ] <= `VAL;
|
iqentry_aq[ dram0_id[`QBITS] ] <= `INV;
|
iqentry_aq[ dram0_id[`QBITS] ] <= `INV;
|
//iqentry_out[ dram0_id[`QBITS] ] <= `INV;
|
//iqentry_out[ dram0_id[`QBITS] ] <= `INV;
|
end
|
end
|
2'd1: begin
|
2'd1: if (`NUM_MEM > 1) begin
|
dram1 <= `DRAMREQ_READY;
|
dram1 <= `DRAMREQ_READY;
|
iqentry_exc[dram1_id[`QBITS]] <= wrv_i|err_i ? `FLT_DWF : `FLT_NONE;
|
iqentry_exc[dram1_id[`QBITS]] <= wrv_i|err_i ? `FLT_DWF : `FLT_NONE;
|
if (err_i|wrv_i) iqentry_a1[dram1_id[`QBITS]] <= adr_o;
|
if (err_i|wrv_i) iqentry_a1[dram1_id[`QBITS]] <= adr_o;
|
iqentry_cmt[ dram1_id[`QBITS] ] <= `VAL;
|
iqentry_cmt[ dram1_id[`QBITS] ] <= `VAL;
|
iqentry_aq[ dram1_id[`QBITS] ] <= `INV;
|
iqentry_aq[ dram1_id[`QBITS] ] <= `INV;
|
//iqentry_out[ dram1_id[`QBITS] ] <= `INV;
|
//iqentry_out[ dram1_id[`QBITS] ] <= `INV;
|
end
|
end
|
2'd2: begin
|
2'd2: if (`NUM_MEM > 2) begin
|
dram2 <= `DRAMREQ_READY;
|
dram2 <= `DRAMREQ_READY;
|
iqentry_exc[dram2_id[`QBITS]] <= wrv_i|err_i ? `FLT_DWF : `FLT_NONE;
|
iqentry_exc[dram2_id[`QBITS]] <= wrv_i|err_i ? `FLT_DWF : `FLT_NONE;
|
if (err_i|wrv_i) iqentry_a1[dram2_id[`QBITS]] <= adr_o;
|
if (err_i|wrv_i) iqentry_a1[dram2_id[`QBITS]] <= adr_o;
|
iqentry_cmt[ dram2_id[`QBITS] ] <= `VAL;
|
iqentry_cmt[ dram2_id[`QBITS] ] <= `VAL;
|
iqentry_aq[ dram2_id[`QBITS] ] <= `INV;
|
iqentry_aq[ dram2_id[`QBITS] ] <= `INV;
|
//iqentry_out[ dram2_id[`QBITS] ] <= `INV;
|
//iqentry_out[ dram2_id[`QBITS] ] <= `INV;
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
|
`endif
|
bstate <= B19;
|
bstate <= B19;
|
end
|
end
|
B2:
|
B2:
|
begin
|
begin
|
dccnt <= 2'd0;
|
dccnt <= 2'd0;
|
| Line 7508... |
Line 8365... |
sel_o <= fnSelect(dram0_instr,dram0_addr);
|
sel_o <= fnSelect(dram0_instr,dram0_addr);
|
adr_o <= {dram0_addr[31:5],5'b0};
|
adr_o <= {dram0_addr[31:5],5'b0};
|
ol_o <= dram0_ol;
|
ol_o <= dram0_ol;
|
bstate <= B2d;
|
bstate <= B2d;
|
end
|
end
|
2'd1: begin
|
2'd1: if (`NUM_MEM > 1) begin
|
cti_o <= 3'b001;
|
cti_o <= 3'b001;
|
bte_o <= 2'b01;
|
bte_o <= 2'b01;
|
cyc_o <= `HIGH;
|
cyc_o <= `HIGH;
|
stb_o <= `HIGH;
|
stb_o <= `HIGH;
|
sel_o <= fnSelect(dram1_instr,dram1_addr);
|
sel_o <= fnSelect(dram1_instr,dram1_addr);
|
adr_o <= {dram1_addr[31:5],5'b0};
|
adr_o <= {dram1_addr[31:5],5'b0};
|
ol_o <= dram1_ol;
|
ol_o <= dram1_ol;
|
bstate <= B2d;
|
bstate <= B2d;
|
end
|
end
|
2'd2: begin
|
2'd2: if (`NUM_MEM > 2) begin
|
cti_o <= 3'b001;
|
cti_o <= 3'b001;
|
bte_o <= 2'b01;
|
bte_o <= 2'b01;
|
cyc_o <= `HIGH;
|
cyc_o <= `HIGH;
|
stb_o <= `HIGH;
|
stb_o <= `HIGH;
|
sel_o <= fnSelect(dram2_instr,dram2_addr);
|
sel_o <= fnSelect(dram2_instr,dram2_addr);
|
| Line 7542... |
Line 8399... |
case(bwhich)
|
case(bwhich)
|
2'd0: if (err_i|rdv_i) begin
|
2'd0: if (err_i|rdv_i) begin
|
iqentry_a1[dram0_id[`QBITS]] <= adr_o;
|
iqentry_a1[dram0_id[`QBITS]] <= adr_o;
|
iqentry_exc[dram0_id[`QBITS]] <= err_i ? `FLT_DBE : `FLT_DRF;
|
iqentry_exc[dram0_id[`QBITS]] <= err_i ? `FLT_DBE : `FLT_DRF;
|
end
|
end
|
2'd1: if (err_i|rdv_i) begin
|
2'd1: if ((err_i|rdv_i) && `NUM_MEM > 1) begin
|
iqentry_a1[dram1_id[`QBITS]] <= adr_o;
|
iqentry_a1[dram1_id[`QBITS]] <= adr_o;
|
iqentry_exc[dram1_id[`QBITS]] <= err_i ? `FLT_DBE : `FLT_DRF;
|
iqentry_exc[dram1_id[`QBITS]] <= err_i ? `FLT_DBE : `FLT_DRF;
|
end
|
end
|
2'd2: if (err_i|rdv_i) begin
|
2'd2: if ((err_i|rdv_i) && `NUM_MEM > 2) begin
|
iqentry_a1[dram2_id[`QBITS]] <= adr_o;
|
iqentry_a1[dram2_id[`QBITS]] <= adr_o;
|
iqentry_exc[dram2_id[`QBITS]] <= err_i ? `FLT_DBE : `FLT_DRF;
|
iqentry_exc[dram2_id[`QBITS]] <= err_i ? `FLT_DBE : `FLT_DRF;
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
| Line 7587... |
Line 8444... |
// Ack state for instruction cache load
|
// Ack state for instruction cache load
|
B7:
|
B7:
|
if (ack_i|err_i) begin
|
if (ack_i|err_i) begin
|
errq <= errq | err_i;
|
errq <= errq | err_i;
|
exvq <= exvq | exv_i;
|
exvq <= exvq | exv_i;
|
// L1_en <= 8'h3 << {L2_adr[4:3],1'b0};
|
// L1_en <= 9'h3 << {L2_xsel,L2_adr[4:3],1'b0};
|
// L1_wr0 <= `TRUE;
|
// L1_wr0 <= `TRUE;
|
// L1_wr1 <= `TRUE;
|
// L1_wr1 <= `TRUE;
|
// L1_adr <= L2_adr;
|
// L1_adr <= L2_adr;
|
if (err_i)
|
if (err_i)
|
L2_rdat <= {8{13'b0,3'd7,3'b0,`FLT_IBE,`BRK}};
|
L2_rdat <= {9{11'b0,4'd7,1'b0,`FLT_IBE,2'b00,`BRK}};
|
else
|
else
|
L2_rdat <= {4{dat_i}};
|
L2_rdat <= {dat_i[31:0],{4{dat_i}}};
|
iccnt <= iccnt + 3'd1;
|
iccnt <= iccnt + 3'd1;
|
//stb_o <= `LOW;
|
//stb_o <= `LOW;
|
if (iccnt==3'd3)
|
if (iccnt==3'd3)
|
cti_o <= 3'b111;
|
cti_o <= 3'b111;
|
if (iccnt==3'd4) begin
|
if (iccnt==3'd4) begin
|
| Line 7618... |
Line 8475... |
end
|
end
|
B9:
|
B9:
|
begin
|
begin
|
L1_wr0 <= `FALSE;
|
L1_wr0 <= `FALSE;
|
L1_wr1 <= `FALSE;
|
L1_wr1 <= `FALSE;
|
L1_en <= 8'hFF;
|
L1_wr2 <= `FALSE;
|
|
L1_en <= 9'h1FF;
|
L2_xsel <= 1'b0;
|
L2_xsel <= 1'b0;
|
if (~ack_i) begin
|
if (~ack_i) begin
|
bstate <= BIDLE;
|
bstate <= BIDLE;
|
L2_nxt <= TRUE;
|
L2_nxt <= TRUE;
|
end
|
end
|
| Line 7687... |
Line 8545... |
2'b00: begin
|
2'b00: begin
|
dram0 <= `DRAMREQ_READY;
|
dram0 <= `DRAMREQ_READY;
|
iqentry_exc [ dram0_id[`QBITS] ] <= err_i ? `FLT_DRF : rdv_i ? `FLT_DRF : `FLT_NONE;
|
iqentry_exc [ dram0_id[`QBITS] ] <= err_i ? `FLT_DRF : rdv_i ? `FLT_DRF : `FLT_NONE;
|
if (err_i|rdv_i) iqentry_a1[dram0_id[`QBITS]] <= adr_o;
|
if (err_i|rdv_i) iqentry_a1[dram0_id[`QBITS]] <= adr_o;
|
end
|
end
|
2'b01: begin
|
2'b01: if (`NUM_MEM > 1) begin
|
dram1 <= `DRAMREQ_READY;
|
dram1 <= `DRAMREQ_READY;
|
iqentry_exc [ dram1_id[`QBITS] ] <= err_i ? `FLT_DRF : rdv_i ? `FLT_DRF : `FLT_NONE;
|
iqentry_exc [ dram1_id[`QBITS] ] <= err_i ? `FLT_DRF : rdv_i ? `FLT_DRF : `FLT_NONE;
|
if (err_i|rdv_i) iqentry_a1[dram1_id[`QBITS]] <= adr_o;
|
if (err_i|rdv_i) iqentry_a1[dram1_id[`QBITS]] <= adr_o;
|
end
|
end
|
2'b10: begin
|
2'b10: if (`NUM_MEM > 2) begin
|
dram2 <= `DRAMREQ_READY;
|
dram2 <= `DRAMREQ_READY;
|
iqentry_exc [ dram2_id[`QBITS] ] <= err_i ? `FLT_DRF : rdv_i ? `FLT_DRF : `FLT_NONE;
|
iqentry_exc [ dram2_id[`QBITS] ] <= err_i ? `FLT_DRF : rdv_i ? `FLT_DRF : `FLT_NONE;
|
if (err_i|rdv_i) iqentry_a1[dram2_id[`QBITS]] <= adr_o;
|
if (err_i|rdv_i) iqentry_a1[dram2_id[`QBITS]] <= adr_o;
|
end
|
end
|
default: ;
|
default: ;
|
| Line 7842... |
Line 8700... |
n[4:0]+2, urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b10}], regIsValid[n+2], rf_source[n+2],
|
n[4:0]+2, urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b10}], regIsValid[n+2], rf_source[n+2],
|
n[4:0]+3, urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b11}], regIsValid[n+3], rf_source[n+3]
|
n[4:0]+3, urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b11}], regIsValid[n+3], rf_source[n+3]
|
);
|
);
|
end
|
end
|
`endif
|
`endif
|
|
`ifdef FCU_ENH
|
$display("Call Stack:");
|
$display("Call Stack:");
|
for (n = 0; n < 32; n = n + 4)
|
for (n = 0; n < 16; n = n + 4)
|
$display("%c%d: %h %c%d: %h %c%d: %h %c%d: %h",
|
$display("%c%d: %h %c%d: %h %c%d: %h %c%d: %h",
|
ufb1.ursb1.rasp==n+0 ?">" : " ", n[4:0]+0, ufb1.ursb1.ras[n+0],
|
ufb1.ursb1.rasp==n+0 ?">" : " ", n[4:0]+0, ufb1.ursb1.ras[n+0],
|
ufb1.ursb1.rasp==n+1 ?">" : " ", n[4:0]+1, ufb1.ursb1.ras[n+1],
|
ufb1.ursb1.rasp==n+1 ?">" : " ", n[4:0]+1, ufb1.ursb1.ras[n+1],
|
ufb1.ursb1.rasp==n+2 ?">" : " ", n[4:0]+2, ufb1.ursb1.ras[n+2],
|
ufb1.ursb1.rasp==n+2 ?">" : " ", n[4:0]+2, ufb1.ursb1.ras[n+2],
|
ufb1.ursb1.rasp==n+3 ?">" : " ", n[4:0]+3, ufb1.ursb1.ras[n+3]
|
ufb1.ursb1.rasp==n+3 ?">" : " ", n[4:0]+3, ufb1.ursb1.ras[n+3]
|
);
|
);
|
$display("\n");
|
$display("\n");
|
|
`endif
|
// $display("Return address stack:");
|
// $display("Return address stack:");
|
// for (n = 0; n < 16; n = n + 1)
|
// for (n = 0; n < 16; n = n + 1)
|
// $display("%d %h", rasp+n[3:0], ras[rasp+n[3:0]]);
|
// $display("%d %h", rasp+n[3:0], ras[rasp+n[3:0]]);
|
$display("TakeBr:%d #", take_branch);//, backpc);
|
$display("TakeBr:%d #", take_branch);//, backpc);
|
$display("%c%c A: %d %h %h #",
|
$display("%c%c A: %d %h %h #",
|
| Line 7893... |
Line 8752... |
);
|
);
|
$display("DRAM");
|
$display("DRAM");
|
$display("%d %h %h %c%h %o #",
|
$display("%d %h %h %c%h %o #",
|
dram0, dram0_addr, dram0_data, (IsFlowCtrl(dram0_instr) ? 98 : (IsMem(dram0_instr)) ? 109 : 97),
|
dram0, dram0_addr, dram0_data, (IsFlowCtrl(dram0_instr) ? 98 : (IsMem(dram0_instr)) ? 109 : 97),
|
dram0_instr, dram0_id);
|
dram0_instr, dram0_id);
|
|
if (`NUM_MEM > 1)
|
$display("%d %h %h %c%h %o #",
|
$display("%d %h %h %c%h %o #",
|
dram1, dram1_addr, dram1_data, (IsFlowCtrl(dram1_instr) ? 98 : (IsMem(dram1_instr)) ? 109 : 97),
|
dram1, dram1_addr, dram1_data, (IsFlowCtrl(dram1_instr) ? 98 : (IsMem(dram1_instr)) ? 109 : 97),
|
dram1_instr, dram1_id);
|
dram1_instr, dram1_id);
|
|
if (`NUM_MEM > 2)
|
$display("%d %h %h %c%h %o #",
|
$display("%d %h %h %c%h %o #",
|
dram2, dram2_addr, dram2_data, (IsFlowCtrl(dram2_instr) ? 98 : (IsMem(dram2_instr)) ? 109 : 97),
|
dram2, dram2_addr, dram2_data, (IsFlowCtrl(dram2_instr) ? 98 : (IsMem(dram2_instr)) ? 109 : 97),
|
dram2_instr, dram2_id);
|
dram2_instr, dram2_id);
|
$display("%d %h %o %h #", dramA_v, dramA_bus, dramA_id, dramA_exc);
|
$display("%d %h %o %h #", dramA_v, dramA_bus, dramA_id, dramA_exc);
|
|
if (`NUM_MEM > 1)
|
$display("%d %h %o %h #", dramB_v, dramB_bus, dramB_id, dramB_exc);
|
$display("%d %h %o %h #", dramB_v, dramB_bus, dramB_id, dramB_exc);
|
|
if (`NUM_MEM > 2)
|
$display("%d %h %o %h #", dramC_v, dramC_bus, dramC_id, dramC_exc);
|
$display("%d %h %o %h #", dramC_v, dramC_bus, dramC_id, dramC_exc);
|
$display("ALU");
|
$display("ALU");
|
$display("%d %h %h %h %c%h %d %o %h #",
|
$display("%d %h %h %h %c%h %d %o %h #",
|
alu0_dataready, alu0_argI, alu0_argA, alu0_argB,
|
alu0_dataready, alu0_argI, alu0_argA, alu0_argB,
|
(IsFlowCtrl(alu0_instr) ? 98 : IsMem(alu0_instr) ? 109 : 97),
|
(IsFlowCtrl(alu0_instr) ? 98 : IsMem(alu0_instr) ? 109 : 97),
|
alu0_instr, alu0_bt, alu0_sourceid, alu0_pc);
|
alu0_instr, alu0_bt, alu0_sourceid, alu0_pc);
|
$display("%d %h %o 0 #", alu0_v, alu0_bus, alu0_id);
|
$display("%d %h %o 0 #", alu0_v, alu0_bus, alu0_id);
|
|
if (`NUM_ALU > 1) begin
|
$display("%d %h %h %h %c%h %d %o %h #",
|
$display("%d %h %h %h %c%h %d %o %h #",
|
alu1_dataready, alu1_argI, alu1_argA, alu1_argB,
|
alu1_dataready, alu1_argI, alu1_argA, alu1_argB,
|
(IsFlowCtrl(alu1_instr) ? 98 : IsMem(alu1_instr) ? 109 : 97),
|
(IsFlowCtrl(alu1_instr) ? 98 : IsMem(alu1_instr) ? 109 : 97),
|
alu1_instr, alu1_bt, alu1_sourceid, alu1_pc);
|
alu1_instr, alu1_bt, alu1_sourceid, alu1_pc);
|
$display("%d %h %o 0 #", alu1_v, alu1_bus, alu1_id);
|
$display("%d %h %o 0 #", alu1_v, alu1_bus, alu1_id);
|
|
end
|
$display("FCU");
|
$display("FCU");
|
$display("%d %h %h %h %h #", fcu_v, fcu_bus, fcu_argI, fcu_argA, fcu_argB);
|
$display("%d %h %h %h %h #", fcu_v, fcu_bus, fcu_argI, fcu_argA, fcu_argB);
|
$display("%c %h %h #", fcu_branchmiss?"m":" ", fcu_sourceid, fcu_misspc);
|
$display("%c %h %h #", fcu_branchmiss?"m":" ", fcu_sourceid, fcu_misspc);
|
$display("Commit");
|
$display("Commit");
|
$display("0: %c %h %o %d #", commit0_v?"v":" ", commit0_bus, commit0_id, commit0_tgt[4:0]);
|
$display("0: %c %h %o %d #", commit0_v?"v":" ", commit0_bus, commit0_id, commit0_tgt[4:0]);
|
$display("1: %c %h %o %d #", commit1_v?"v":" ", commit1_bus, commit1_id, commit1_tgt[4:0]);
|
$display("1: %c %h %o %d #", commit1_v?"v":" ", commit1_bus, commit1_id, commit1_tgt[4:0]);
|
$display("instructions committed: %d ticks: %d ", I, tick);
|
$display("instructions committed: %d ticks: %d ", I, tick);
|
|
$display("Write merges: %d", wb_merges);
|
|
|
//
|
//
|
// $display("\n\n\n\n\n\n\n\n");
|
// $display("\n\n\n\n\n\n\n\n");
|
// $display("TIME %0d", $time);
|
// $display("TIME %0d", $time);
|
// $display(" pc0=%h", pc0);
|
// $display(" pc0=%h", pc0);
|
| Line 8127... |
Line 8992... |
seq_num <= seq_num + 5'd2;
|
seq_num <= seq_num + 5'd2;
|
else if (queued1)
|
else if (queued1)
|
seq_num <= seq_num + 5'd1;
|
seq_num <= seq_num + 5'd1;
|
end
|
end
|
*/
|
*/
|
|
|
|
task wb_update;
|
|
input [`QBITS] id;
|
|
input rmw;
|
|
input [7:0] sel;
|
|
input [1:0] ol;
|
|
input [`ABITS] addr;
|
|
input [63:0] data;
|
|
begin
|
|
if (wbptr > 0 && wb_addr[wbptr-1][AMSB:3]==addr[AMSB:3] && wb_ol[wbptr-1]==ol && wb_rmw[wbptr-1]==rmw) begin
|
|
wb_sel[wbptr-1] <= wb_sel[wbptr-1] | sel;
|
|
if (sel[0]) wb_data[wbptr-1][ 7: 0] <= data[ 7: 0];
|
|
if (sel[1]) wb_data[wbptr-1][15: 8] <= data[15: 8];
|
|
if (sel[2]) wb_data[wbptr-1][23:16] <= data[23:16];
|
|
if (sel[3]) wb_data[wbptr-1][31:24] <= data[31:24];
|
|
if (sel[4]) wb_data[wbptr-1][39:32] <= data[39:32];
|
|
if (sel[5]) wb_data[wbptr-1][47:40] <= data[47:40];
|
|
if (sel[6]) wb_data[wbptr-1][55:48] <= data[55:48];
|
|
if (sel[7]) wb_data[wbptr-1][63:56] <= data[63:56];
|
|
wb_id[wbptr-1] <= wb_id[wbptr-1] | (16'd1 << id);
|
|
wb_merges <= wb_merges + 32'd1;
|
|
end
|
|
else begin
|
|
wb_v[wbptr] <= wb_en;
|
|
wb_id[wbptr] <= (16'd1 << id);
|
|
wb_rmw[wbptr] <= rmw;
|
|
wb_ol[wbptr] <= ol;
|
|
wb_sel[wbptr] <= sel;
|
|
wb_addr[wbptr] <= {addr[AMSB:3],3'b0};
|
|
wb_data[wbptr] <= data;
|
|
end
|
|
end
|
|
endtask
|
// Increment the head pointers
|
// Increment the head pointers
|
// Also increments the instruction counter
|
// Also increments the instruction counter
|
// Used when instructions are committed.
|
// Used when instructions are committed.
|
// Also clear any outstanding state bits that foul things up.
|
// Also clear any outstanding state bits that foul things up.
|
//
|
//
|
| Line 8144... |
Line 9042... |
head4 <= head4 + amt;
|
head4 <= head4 + amt;
|
head5 <= head5 + amt;
|
head5 <= head5 + amt;
|
head6 <= head6 + amt;
|
head6 <= head6 + amt;
|
head7 <= head7 + amt;
|
head7 <= head7 + amt;
|
I <= I + amt;
|
I <= I + amt;
|
if (amt==3'd2) begin
|
if (amt==3'd3) begin
|
|
iqentry_agen[head0] <= `INV;
|
|
iqentry_agen[head1] <= `INV;
|
|
iqentry_agen[head2] <= `INV;
|
|
iqentry_mem[head0] <= `FALSE;
|
|
iqentry_mem[head1] <= `FALSE;
|
|
iqentry_mem[head2] <= `FALSE;
|
|
iqentry_iv[head0] <= `INV;
|
|
iqentry_iv[head1] <= `INV;
|
|
iqentry_iv[head2] <= `INV;
|
|
iqentry_alu[head0] <= `FALSE;
|
|
iqentry_alu[head1] <= `FALSE;
|
|
iqentry_alu[head2] <= `FALSE;
|
|
end
|
|
else if (amt==3'd2) begin
|
iqentry_agen[head0] <= `INV;
|
iqentry_agen[head0] <= `INV;
|
iqentry_agen[head1] <= `INV;
|
iqentry_agen[head1] <= `INV;
|
|
iqentry_mem[head0] <= `FALSE;
|
|
iqentry_mem[head1] <= `FALSE;
|
|
iqentry_iv[head0] <= `INV;
|
|
iqentry_iv[head1] <= `INV;
|
|
iqentry_alu[head0] <= `FALSE;
|
|
iqentry_alu[head1] <= `FALSE;
|
end else if (amt==3'd1) begin
|
end else if (amt==3'd1) begin
|
iqentry_agen[head0] <= `INV;
|
iqentry_agen[head0] <= `INV;
|
|
iqentry_mem[head0] <= `FALSE;
|
|
iqentry_iv[head0] <= `INV;
|
|
iqentry_alu[head0] <= `FALSE;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
task setargs;
|
task setargs;
|
| Line 8410... |
Line 9331... |
cause[{thread,3'd0}] <= {8'd0,iqentry_exc[head]};
|
cause[{thread,3'd0}] <= {8'd0,iqentry_exc[head]};
|
mstatus[5:3] <= 3'd0;
|
mstatus[5:3] <= 3'd0;
|
mstatus[13:6] <= 8'h00;
|
mstatus[13:6] <= 8'h00;
|
mstatus[19:14] <= 6'd0;
|
mstatus[19:14] <= 6'd0;
|
`endif
|
`endif
|
|
wb_en <= `TRUE;
|
sema[0] <= 1'b0;
|
sema[0] <= 1'b0;
|
ve_hold <= {vqet1,10'd0,vqe1,10'd0,vqet0,10'd0,vqe0};
|
ve_hold <= {vqet1,10'd0,vqe1,10'd0,vqet0,10'd0,vqe0};
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
dbg_ctrl[62:55] <= {dbg_ctrl[61:55],dbg_ctrl[63]};
|
dbg_ctrl[62:55] <= {dbg_ctrl[61:55],dbg_ctrl[63]};
|
dbg_ctrl[63] <= FALSE;
|
dbg_ctrl[63] <= FALSE;
|
| Line 8568... |
Line 9490... |
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
dbg_ctrl[62:55] <= {FALSE,dbg_ctrl[62:56]};
|
dbg_ctrl[62:55] <= {FALSE,dbg_ctrl[62:56]};
|
dbg_ctrl[63] <= dbg_ctrl[55];
|
dbg_ctrl[63] <= dbg_ctrl[55];
|
`endif
|
`endif
|
end
|
end
|
|
default: ;
|
|
endcase
|
|
`MEMNDX:
|
|
case(iqentry_instr[head][`INSTRUCTION_S2])
|
`CACHEX:
|
`CACHEX:
|
case(iqentry_instr[head][20:16])
|
case(iqentry_instr[head][22:18])
|
5'h03: invic <= TRUE;
|
5'h03: invic <= TRUE;
|
5'h10: cr0[30] <= FALSE;
|
5'h10: cr0[30] <= FALSE;
|
5'h11: cr0[30] <= TRUE;
|
5'h11: cr0[30] <= TRUE;
|
default: ;
|
default: ;
|
endcase
|
endcase
|
| Line 8599... |
Line 9525... |
cause[{thread,iqentry_instr[head][13:11]}] <= cause[{thread,ol}];
|
cause[{thread,iqentry_instr[head][13:11]}] <= cause[{thread,ol}];
|
mstatus[13:6] <= iqentry_instr[head][23:16] | iqentry_a1[head][7:0];
|
mstatus[13:6] <= iqentry_instr[head][23:16] | iqentry_a1[head][7:0];
|
end
|
end
|
`endif
|
`endif
|
`CACHE:
|
`CACHE:
|
case(iqentry_instr[head][15:11])
|
case(iqentry_instr[head][17:13])
|
5'h03: invic <= TRUE;
|
5'h03: invic <= TRUE;
|
5'h10: cr0[30] <= FALSE;
|
5'h10: cr0[30] <= FALSE;
|
5'h11: cr0[30] <= TRUE;
|
5'h11: cr0[30] <= TRUE;
|
default: ;
|
default: ;
|
endcase
|
endcase
|
`FLOAT:
|
`FLOAT:
|
case(iqentry_instr[head][`INSTRUCTION_S2])
|
case(iqentry_instr[head][`INSTRUCTION_S2])
|
`FRM: fp_rm <= iqentry_res[head][2:0];
|
`FRM: begin
|
|
fp1_rm <= iqentry_res[head][2:0];
|
|
fp2_rm <= iqentry_res[head][2:0];
|
|
end
|
`FCX:
|
`FCX:
|
begin
|
begin
|
fp_sx <= fp_sx & ~iqentry_res[head][5];
|
fp1_sx <= fp1_sx & ~iqentry_res[head][5];
|
fp_inex <= fp_inex & ~iqentry_res[head][4];
|
fp1_inex <= fp1_inex & ~iqentry_res[head][4];
|
fp_dbzx <= fp_dbzx & ~(iqentry_res[head][3]|iqentry_res[head][0]);
|
fp1_dbzx <= fp1_dbzx & ~(iqentry_res[head][3]|iqentry_res[head][0]);
|
fp_underx <= fp_underx & ~iqentry_res[head][2];
|
fp1_underx <= fp1_underx & ~iqentry_res[head][2];
|
fp_overx <= fp_overx & ~iqentry_res[head][1];
|
fp1_overx <= fp1_overx & ~iqentry_res[head][1];
|
fp_giopx <= fp_giopx & ~iqentry_res[head][0];
|
fp1_giopx <= fp1_giopx & ~iqentry_res[head][0];
|
fp_infdivx <= fp_infdivx & ~iqentry_res[head][0];
|
fp1_infdivx <= fp1_infdivx & ~iqentry_res[head][0];
|
fp_zerozerox <= fp_zerozerox & ~iqentry_res[head][0];
|
fp1_zerozerox <= fp1_zerozerox & ~iqentry_res[head][0];
|
fp_subinfx <= fp_subinfx & ~iqentry_res[head][0];
|
fp1_subinfx <= fp1_subinfx & ~iqentry_res[head][0];
|
fp_infzerox <= fp_infzerox & ~iqentry_res[head][0];
|
fp1_infzerox <= fp1_infzerox & ~iqentry_res[head][0];
|
fp_NaNCmpx <= fp_NaNCmpx & ~iqentry_res[head][0];
|
fp1_NaNCmpx <= fp1_NaNCmpx & ~iqentry_res[head][0];
|
fp_swtx <= 1'b0;
|
fp1_swtx <= 1'b0;
|
end
|
end
|
`FDX:
|
`FDX:
|
begin
|
begin
|
fp_inexe <= fp_inexe & ~iqentry_res[head][4];
|
fp1_inexe <= fp1_inexe & ~iqentry_res[head][4];
|
fp_dbzxe <= fp_dbzxe & ~iqentry_res[head][3];
|
fp1_dbzxe <= fp1_dbzxe & ~iqentry_res[head][3];
|
fp_underxe <= fp_underxe & ~iqentry_res[head][2];
|
fp1_underxe <= fp1_underxe & ~iqentry_res[head][2];
|
fp_overxe <= fp_overxe & ~iqentry_res[head][1];
|
fp1_overxe <= fp1_overxe & ~iqentry_res[head][1];
|
fp_invopxe <= fp_invopxe & ~iqentry_res[head][0];
|
fp1_invopxe <= fp1_invopxe & ~iqentry_res[head][0];
|
end
|
end
|
`FEX:
|
`FEX:
|
begin
|
begin
|
fp_inexe <= fp_inexe | iqentry_res[head][4];
|
fp1_inexe <= fp1_inexe | iqentry_res[head][4];
|
fp_dbzxe <= fp_dbzxe | iqentry_res[head][3];
|
fp1_dbzxe <= fp1_dbzxe | iqentry_res[head][3];
|
fp_underxe <= fp_underxe | iqentry_res[head][2];
|
fp1_underxe <= fp1_underxe | iqentry_res[head][2];
|
fp_overxe <= fp_overxe | iqentry_res[head][1];
|
fp1_overxe <= fp1_overxe | iqentry_res[head][1];
|
fp_invopxe <= fp_invopxe | iqentry_res[head][0];
|
fp1_invopxe <= fp1_invopxe | iqentry_res[head][0];
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
// 31 to 29 is rounding mode
|
// 31 to 29 is rounding mode
|
// 28 to 24 are exception enables
|
// 28 to 24 are exception enables
|
// 23 is nsfp
|
// 23 is nsfp
|
// 22 is a fractie
|
// 22 is a fractie
|
fp_fractie <= iqentry_a0[head][22];
|
fp1_fractie <= iqentry_a0[head][22];
|
fp_raz <= iqentry_a0[head][21];
|
fp1_raz <= iqentry_a0[head][21];
|
// 20 is a 0
|
// 20 is a 0
|
fp_neg <= iqentry_a0[head][19];
|
fp1_neg <= iqentry_a0[head][19];
|
fp_pos <= iqentry_a0[head][18];
|
fp1_pos <= iqentry_a0[head][18];
|
fp_zero <= iqentry_a0[head][17];
|
fp1_zero <= iqentry_a0[head][17];
|
fp_inf <= iqentry_a0[head][16];
|
fp1_inf <= iqentry_a0[head][16];
|
// 15 swtx
|
// 15 swtx
|
// 14
|
// 14
|
fp_inex <= fp_inex | (fp_inexe & iqentry_a0[head][14]);
|
fp1_inex <= fp1_inex | (fp1_inexe & iqentry_a0[head][14]);
|
fp_dbzx <= fp_dbzx | (fp_dbzxe & iqentry_a0[head][13]);
|
fp1_dbzx <= fp1_dbzx | (fp1_dbzxe & iqentry_a0[head][13]);
|
fp_underx <= fp_underx | (fp_underxe & iqentry_a0[head][12]);
|
fp1_underx <= fp1_underx | (fp1_underxe & iqentry_a0[head][12]);
|
fp_overx <= fp_overx | (fp_overxe & iqentry_a0[head][11]);
|
fp1_overx <= fp1_overx | (fp1_overxe & iqentry_a0[head][11]);
|
//fp_giopx <= fp_giopx | (fp_giopxe & iqentry_res2[head][10]);
|
//fp_giopx <= fp_giopx | (fp_giopxe & iqentry_res2[head][10]);
|
//fp_invopx <= fp_invopx | (fp_invopxe & iqentry_res2[head][24]);
|
//fp_invopx <= fp_invopx | (fp_invopxe & iqentry_res2[head][24]);
|
//
|
//
|
fp_cvtx <= fp_cvtx | (fp_giopxe & iqentry_a0[head][7]);
|
fp1_cvtx <= fp1_cvtx | (fp1_giopxe & iqentry_a0[head][7]);
|
fp_sqrtx <= fp_sqrtx | (fp_giopxe & iqentry_a0[head][6]);
|
fp1_sqrtx <= fp1_sqrtx | (fp1_giopxe & iqentry_a0[head][6]);
|
fp_NaNCmpx <= fp_NaNCmpx | (fp_giopxe & iqentry_a0[head][5]);
|
fp1_NaNCmpx <= fp1_NaNCmpx | (fp1_giopxe & iqentry_a0[head][5]);
|
fp_infzerox <= fp_infzerox | (fp_giopxe & iqentry_a0[head][4]);
|
fp1_infzerox <= fp1_infzerox | (fp1_giopxe & iqentry_a0[head][4]);
|
fp_zerozerox <= fp_zerozerox | (fp_giopxe & iqentry_a0[head][3]);
|
fp1_zerozerox <= fp1_zerozerox | (fp1_giopxe & iqentry_a0[head][3]);
|
fp_infdivx <= fp_infdivx | (fp_giopxe & iqentry_a0[head][2]);
|
fp1_infdivx <= fp1_infdivx | (fp1_giopxe & iqentry_a0[head][2]);
|
fp_subinfx <= fp_subinfx | (fp_giopxe & iqentry_a0[head][1]);
|
fp1_subinfx <= fp1_subinfx | (fp1_giopxe & iqentry_a0[head][1]);
|
fp_snanx <= fp_snanx | (fp_giopxe & iqentry_a0[head][0]);
|
fp1_snanx <= fp1_snanx | (fp1_giopxe & iqentry_a0[head][0]);
|
|
|
end
|
end
|
endcase
|
endcase
|
default: ;
|
default: ;
|
endcase
|
endcase
|
| Line 8698... |
Line 9627... |
`CSR_CR0: dat <= cr0;
|
`CSR_CR0: dat <= cr0;
|
`CSR_HARTID: dat <= hartid;
|
`CSR_HARTID: dat <= hartid;
|
`CSR_TICK: dat <= tick;
|
`CSR_TICK: dat <= tick;
|
`CSR_PCR: dat <= pcr;
|
`CSR_PCR: dat <= pcr;
|
`CSR_PCR2: dat <= pcr2;
|
`CSR_PCR2: dat <= pcr2;
|
|
`CSR_PMR: dat <= pmr;
|
`CSR_WBRCD: dat <= wbrcd;
|
`CSR_WBRCD: dat <= wbrcd;
|
`CSR_SEMA: dat <= sema;
|
`CSR_SEMA: dat <= sema;
|
`CSR_SBL: dat <= sbl;
|
`CSR_SBL: dat <= sbl;
|
`CSR_SBU: dat <= sbu;
|
`CSR_SBU: dat <= sbu;
|
`CSR_TCB: dat <= tcb;
|
`CSR_TCB: dat <= tcb;
|
`CSR_FSTAT: dat <= {fp_rgs,fp_status};
|
`CSR_FSTAT: dat <= {fp1_rgs,fp1_status};
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
`CSR_DBAD0: dat <= dbg_adr0;
|
`CSR_DBAD0: dat <= dbg_adr0;
|
`CSR_DBAD1: dat <= dbg_adr1;
|
`CSR_DBAD1: dat <= dbg_adr1;
|
`CSR_DBAD2: dat <= dbg_adr2;
|
`CSR_DBAD2: dat <= dbg_adr2;
|
`CSR_DBAD3: dat <= dbg_adr3;
|
`CSR_DBAD3: dat <= dbg_adr3;
|
| Line 8787... |
Line 9717... |
2'd1: // CSRRW
|
2'd1: // CSRRW
|
casez(csrno[9:0])
|
casez(csrno[9:0])
|
`CSR_CR0: cr0 <= dat;
|
`CSR_CR0: cr0 <= dat;
|
`CSR_PCR: pcr <= dat[31:0];
|
`CSR_PCR: pcr <= dat[31:0];
|
`CSR_PCR2: pcr2 <= dat;
|
`CSR_PCR2: pcr2 <= dat;
|
|
`CSR_PMR: case(`NUM_IDU)
|
|
0,1: pmr[0] <= 1'b1;
|
|
2:
|
|
begin
|
|
if (dat[1:0]==2'b00)
|
|
pmr[1:0] <= 2'b01;
|
|
else
|
|
pmr[1:0] <= dat[1:0];
|
|
pmr[63:2] <= dat[63:2];
|
|
end
|
|
3:
|
|
begin
|
|
if (dat[2:0]==3'b000)
|
|
pmr[2:0] <= 3'b001;
|
|
else
|
|
pmr[2:0] <= dat[2:0];
|
|
pmr[63:3] <= dat[63:3];
|
|
end
|
|
default: pmr[0] <= 1'b1;
|
|
endcase
|
`CSR_WBRCD: wbrcd <= dat;
|
`CSR_WBRCD: wbrcd <= dat;
|
`CSR_SEMA: sema <= dat;
|
`CSR_SEMA: sema <= dat;
|
`CSR_SBL: sbl <= dat[31:0];
|
`CSR_SBL: sbl <= dat[31:0];
|
`CSR_SBU: sbu <= dat[31:0];
|
`CSR_SBU: sbu <= dat[31:0];
|
`CSR_TCB: tcb <= dat;
|
`CSR_TCB: tcb <= dat;
|
`CSR_FSTAT: fpu_csr[37:32] <= dat[37:32];
|
`CSR_FSTAT: fpu1_csr[37:32] <= dat[37:32];
|
`CSR_BADADR: badaddr[{thread,csrno[13:11]}] <= dat;
|
`CSR_BADADR: badaddr[{thread,csrno[13:11]}] <= dat;
|
`CSR_CAUSE: cause[{thread,csrno[13:11]}] <= dat[15:0];
|
`CSR_CAUSE: cause[{thread,csrno[13:11]}] <= dat[15:0];
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
`CSR_DBAD0: dbg_adr0 <= dat[AMSB:0];
|
`CSR_DBAD0: dbg_adr0 <= dat[AMSB:0];
|
`CSR_DBAD1: dbg_adr1 <= dat[AMSB:0];
|
`CSR_DBAD1: dbg_adr1 <= dat[AMSB:0];
|
| Line 8845... |
Line 9795... |
2'd2: // CSRRS
|
2'd2: // CSRRS
|
case(csrno[9:0])
|
case(csrno[9:0])
|
`CSR_CR0: cr0 <= cr0 | dat;
|
`CSR_CR0: cr0 <= cr0 | dat;
|
`CSR_PCR: pcr[31:0] <= pcr[31:0] | dat[31:0];
|
`CSR_PCR: pcr[31:0] <= pcr[31:0] | dat[31:0];
|
`CSR_PCR2: pcr2 <= pcr2 | dat;
|
`CSR_PCR2: pcr2 <= pcr2 | dat;
|
|
`CSR_PMR: pmr <= pmr | dat;
|
`CSR_WBRCD: wbrcd <= wbrcd | dat;
|
`CSR_WBRCD: wbrcd <= wbrcd | dat;
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
`CSR_DBCTRL: dbg_ctrl <= dbg_ctrl | dat;
|
`CSR_DBCTRL: dbg_ctrl <= dbg_ctrl | dat;
|
`endif
|
`endif
|
`CSR_SEMA: sema <= sema | dat;
|
`CSR_SEMA: sema <= sema | dat;
|
| Line 8862... |
Line 9813... |
2'd3: // CSRRC
|
2'd3: // CSRRC
|
case(csrno[9:0])
|
case(csrno[9:0])
|
`CSR_CR0: cr0 <= cr0 & ~dat;
|
`CSR_CR0: cr0 <= cr0 & ~dat;
|
`CSR_PCR: pcr <= pcr & ~dat;
|
`CSR_PCR: pcr <= pcr & ~dat;
|
`CSR_PCR2: pcr2 <= pcr2 & ~dat;
|
`CSR_PCR2: pcr2 <= pcr2 & ~dat;
|
|
`CSR_PMR: begin
|
|
if (dat[1:0]==2'b11)
|
|
pmr[1:0] <= 2'b01;
|
|
else
|
|
pmr[1:0] <= pmr[1:0] & ~dat[1:0];
|
|
pmr[63:2] <= pmr[63:2] & ~dat[63:2];
|
|
end
|
`CSR_WBRCD: wbrcd <= wbrcd & ~dat;
|
`CSR_WBRCD: wbrcd <= wbrcd & ~dat;
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
`CSR_DBCTRL: dbg_ctrl <= dbg_ctrl & ~dat;
|
`CSR_DBCTRL: dbg_ctrl <= dbg_ctrl & ~dat;
|
`endif
|
`endif
|
`CSR_SEMA: sema <= sema & ~dat;
|
`CSR_SEMA: sema <= sema & ~dat;
|
| Line 8880... |
Line 9838... |
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
/*
|
/*
|
function [63:0] assign_a0;
|
|
input [31:0] fb_instr;
|
|
begin
|
|
if (IsShifti(fb_instr)||IsVShifti(fb_instr)||IsSEI(fb_instr)||IsRTI(fb_instr))
|
|
assign_a0 = {58'd0,fb_instr[21:16]};
|
|
// else if (IsBranch(fb_instr))
|
|
// assign_a0 = {{51{fb_instr[`INSTRUCTION_SB]}},fb_instr[31:22],fb_instr[0],2'b00};
|
|
// else if (fb_instr[`INSTRUCTION_OP] == `CALL || fb_instr[`INSTRUCTION_OP] == `JMP)
|
|
// assign_a0 = {{36{fb_instr[31]}},fb_instr[31:6],2'd0};
|
|
else
|
|
assign_a0 = {{48{fb_instr[`INSTRUCTION_SB]}},fb_instr[31:16]};
|
|
end
|
|
endfunction
|
|
*/
|
|
/*
|
|
task aluissue;
|
task aluissue;
|
input alu_idle;
|
input alu_idle;
|
input [QENTRIES-1:0] iq_alu0;
|
input [QENTRIES-1:0] iq_alu0;
|
input [1:0] slot;
|
input [1:0] slot;
|
begin
|
begin
|
