| Line 302... |
Line 302... |
reg isCAS, isAMO, isInc, isSpt, isRMW;
|
reg isCAS, isAMO, isInc, isSpt, isRMW;
|
reg [`QBITS] casid;
|
reg [`QBITS] casid;
|
reg [`ABITS] sbl, sbu;
|
reg [`ABITS] sbl, sbu;
|
reg [4:0] regLR = 5'd29;
|
reg [4:0] regLR = 5'd29;
|
|
|
reg [2:0] fp1_rm;
|
reg [2:0] fp_rm;
|
reg fp1_inexe;
|
reg fp_inexe;
|
reg fp1_dbzxe;
|
reg fp_dbzxe;
|
reg fp1_underxe;
|
reg fp_underxe;
|
reg fp1_overxe;
|
reg fp_overxe;
|
reg fp1_invopxe;
|
reg fp_invopxe;
|
reg fp1_giopxe;
|
reg fp_giopxe;
|
reg fp1_nsfp = 1'b0;
|
reg fp_nsfp = 1'b0;
|
reg fp1_fractie;
|
reg fp_fractie;
|
reg fp1_raz;
|
reg fp_raz;
|
|
|
reg fp1_neg;
|
reg fp_neg;
|
reg fp1_pos;
|
reg fp_pos;
|
reg fp1_zero;
|
reg fp_zero;
|
reg fp1_inf;
|
reg fp_inf;
|
|
|
reg fp1_inex; // inexact exception
|
reg fp_inex; // inexact exception
|
reg fp1_dbzx; // divide by zero exception
|
reg fp_dbzx; // divide by zero exception
|
reg fp1_underx; // underflow exception
|
reg fp_underx; // underflow exception
|
reg fp1_overx; // overflow exception
|
reg fp_overx; // overflow exception
|
reg fp1_giopx; // global invalid operation exception
|
reg fp_giopx; // global invalid operation exception
|
reg fp1_sx; // summary exception
|
reg fp_sx; // summary exception
|
reg fp1_swtx; // software triggered exception
|
reg fp_swtx; // software triggered exception
|
reg fp1_gx;
|
reg fp_gx;
|
reg fp1_invopx;
|
reg fp_invopx;
|
|
|
reg fp1_infzerox;
|
reg fp_infzerox;
|
reg fp1_zerozerox;
|
reg fp_zerozerox;
|
reg fp1_subinfx;
|
reg fp_subinfx;
|
reg fp1_infdivx;
|
reg fp_infdivx;
|
reg fp1_NaNCmpx;
|
reg fp_NaNCmpx;
|
reg fp1_cvtx;
|
reg fp_cvtx;
|
reg fp1_sqrtx;
|
reg fp_sqrtx;
|
reg fp1_snanx;
|
reg fp_snanx;
|
|
|
reg [2:0] fp2_rm;
|
wire [31:0] fp_status = {
|
reg fp2_inexe;
|
|
reg fp2_dbzxe;
|
fp_rm,
|
reg fp2_underxe;
|
fp_inexe,
|
reg fp2_overxe;
|
fp_dbzxe,
|
reg fp2_invopxe;
|
fp_underxe,
|
reg fp2_giopxe;
|
fp_overxe,
|
reg fp2_nsfp = 1'b0;
|
fp_invopxe,
|
reg fp2_fractie;
|
fp_nsfp,
|
reg fp2_raz;
|
|
|
|
reg fp2_neg;
|
|
reg fp2_pos;
|
|
reg fp2_zero;
|
|
reg fp2_inf;
|
|
|
|
reg fp2_inex; // inexact exception
|
|
reg fp2_dbzx; // divide by zero exception
|
|
reg fp2_underx; // underflow exception
|
|
reg fp2_overx; // overflow exception
|
|
reg fp2_giopx; // global invalid operation exception
|
|
reg fp2_sx; // summary exception
|
|
reg fp2_swtx; // software triggered exception
|
|
reg fp2_gx;
|
|
reg fp2_invopx;
|
|
|
|
reg fp2_infzerox;
|
|
reg fp2_zerozerox;
|
|
reg fp2_subinfx;
|
|
reg fp2_infdivx;
|
|
reg fp2_NaNCmpx;
|
|
reg fp2_cvtx;
|
|
reg fp2_sqrtx;
|
|
reg fp2_snanx;
|
|
|
|
wire [31:0] fp1_status = {
|
|
|
|
fp1_rm,
|
|
fp1_inexe,
|
|
fp1_dbzxe,
|
|
fp1_underxe,
|
|
fp1_overxe,
|
|
fp1_invopxe,
|
|
fp1_nsfp,
|
|
|
|
fp1_fractie,
|
fp_fractie,
|
fp1_raz,
|
fp_raz,
|
1'b0,
|
1'b0,
|
fp1_neg,
|
fp_neg,
|
fp1_pos,
|
fp_pos,
|
fp1_zero,
|
fp_zero,
|
fp1_inf,
|
fp_inf,
|
|
|
fp1_swtx,
|
fp_swtx,
|
fp1_inex,
|
fp_inex,
|
fp1_dbzx,
|
fp_dbzx,
|
fp1_underx,
|
fp_underx,
|
fp1_overx,
|
fp_overx,
|
fp1_giopx,
|
fp_giopx,
|
fp1_gx,
|
fp_gx,
|
fp1_sx,
|
fp_sx,
|
|
|
fp1_cvtx,
|
fp_cvtx,
|
fp1_sqrtx,
|
fp_sqrtx,
|
fp1_NaNCmpx,
|
fp_NaNCmpx,
|
fp1_infzerox,
|
fp_infzerox,
|
fp1_zerozerox,
|
fp_zerozerox,
|
fp1_infdivx,
|
fp_infdivx,
|
fp1_subinfx,
|
fp_subinfx,
|
fp1_snanx
|
fp_snanx
|
};
|
};
|
|
|
wire [31:0] fp2_status = {
|
reg [63:0] fpu_csr;
|
|
wire [5:0] fp_rgs = fpu_csr[37:32];
|
fp2_rm,
|
|
fp2_inexe,
|
|
fp2_dbzxe,
|
|
fp2_underxe,
|
|
fp2_overxe,
|
|
fp2_invopxe,
|
|
fp2_nsfp,
|
|
|
|
fp2_fractie,
|
|
fp2_raz,
|
|
1'b0,
|
|
fp2_neg,
|
|
fp2_pos,
|
|
fp2_zero,
|
|
fp2_inf,
|
|
|
|
fp2_swtx,
|
|
fp2_inex,
|
|
fp2_dbzx,
|
|
fp2_underx,
|
|
fp2_overx,
|
|
fp2_giopx,
|
|
fp2_gx,
|
|
fp2_sx,
|
|
|
|
fp2_cvtx,
|
|
fp2_sqrtx,
|
|
fp2_NaNCmpx,
|
|
fp2_infzerox,
|
|
fp2_zerozerox,
|
|
fp2_infdivx,
|
|
fp2_subinfx,
|
|
fp2_snanx
|
|
};
|
|
|
|
reg [63:0] fpu1_csr;
|
|
wire [5:0] fp1_rgs = fpu1_csr[37:32];
|
|
|
|
//reg [25:0] m[0:8191];
|
//reg [25:0] m[0:8191];
|
reg [3:0] panic; // indexes the message structure
|
reg [3:0] panic; // indexes the message structure
|
reg [128:0] message [0:15]; // indexed by panic
|
reg [128:0] message [0:15]; // indexed by panic
|
|
|
| Line 484... |
Line 412... |
reg [QENTRIES-1:0] iqentry_out; // instruction has been issued to an ALU ...
|
reg [QENTRIES-1:0] iqentry_out; // instruction has been issued to an ALU ...
|
reg [QENTRIES-1:0] iqentry_done; // instruction result valid
|
reg [QENTRIES-1:0] iqentry_done; // instruction result valid
|
reg [QENTRIES-1:0] iqentry_cmt;
|
reg [QENTRIES-1:0] iqentry_cmt;
|
reg [QENTRIES-1:0] iqentry_thrd; // which thread the instruction is in
|
reg [QENTRIES-1:0] iqentry_thrd; // which thread the instruction is in
|
reg [QENTRIES-1:0] iqentry_pt; // predict taken
|
reg [QENTRIES-1:0] iqentry_pt; // predict taken
|
reg [QENTRIES-1:0] iqentry_bt; // branch-taken (used only for branches)
|
reg [QENTRIES-1:0] iqentry_bt; // update branch target buffer
|
|
reg [QENTRIES-1:0] iqentry_jal;
|
reg [QENTRIES-1:0] iqentry_agen; // address-generate ... signifies that address is ready (only for LW/SW)
|
reg [QENTRIES-1:0] iqentry_agen; // address-generate ... signifies that address is ready (only for LW/SW)
|
reg [1:0] iqentry_state [0:QENTRIES-1];
|
reg [1:0] iqentry_state [0:QENTRIES-1];
|
reg [QENTRIES-1:0] iqentry_alu = 8'h00; // alu type instruction
|
reg [QENTRIES-1:0] iqentry_alu = 8'h00; // alu type instruction
|
reg [QENTRIES-1:0] iqentry_alu0; // only valid on alu #0
|
reg [QENTRIES-1:0] iqentry_alu0; // only valid on alu #0
|
reg [QENTRIES-1:0] iqentry_fpu; // floating point instruction
|
reg [QENTRIES-1:0] iqentry_fpu; // floating point instruction
|
| Line 511... |
Line 440... |
reg [QENTRIES-1:0] iqentry_aq; // memory aquire
|
reg [QENTRIES-1:0] iqentry_aq; // memory aquire
|
reg [QENTRIES-1:0] iqentry_rl; // memory release
|
reg [QENTRIES-1:0] iqentry_rl; // memory release
|
reg [QENTRIES-1:0] iqentry_shft48;
|
reg [QENTRIES-1:0] iqentry_shft48;
|
reg [QENTRIES-1:0] iqentry_jmp; // changes control flow: 1 if BEQ/JALR
|
reg [QENTRIES-1:0] iqentry_jmp; // changes control flow: 1 if BEQ/JALR
|
reg [QENTRIES-1:0] iqentry_br; // Bcc (for predictor)
|
reg [QENTRIES-1:0] iqentry_br; // Bcc (for predictor)
|
|
reg [QENTRIES-1:0] iqentry_ret;
|
|
reg [QENTRIES-1:0] iqentry_irq;
|
|
reg [QENTRIES-1:0] iqentry_brk;
|
|
reg [QENTRIES-1:0] iqentry_rti;
|
reg [QENTRIES-1:0] iqentry_sync; // sync instruction
|
reg [QENTRIES-1:0] iqentry_sync; // sync instruction
|
reg [QENTRIES-1:0] iqentry_fsync;
|
reg [QENTRIES-1:0] iqentry_fsync;
|
reg [QENTRIES-1:0] iqentry_rfw = 8'h00; // writes to register file
|
reg [QENTRIES-1:0] iqentry_rfw = 8'h00; // writes to register file
|
reg [7:0] iqentry_we [0:QENTRIES-1]; // enable strobe
|
reg [7:0] iqentry_we [0:QENTRIES-1]; // enable strobe
|
reg [63:0] iqentry_res [0:QENTRIES-1]; // instruction result
|
reg [63:0] iqentry_res [0:QENTRIES-1]; // instruction result
|
| Line 626... |
Line 559... |
wire [`ABITS] fetchbuf0_pc;
|
wire [`ABITS] fetchbuf0_pc;
|
wire fetchbuf0_v;
|
wire fetchbuf0_v;
|
wire fetchbuf0_thrd;
|
wire fetchbuf0_thrd;
|
wire fetchbuf0_mem;
|
wire fetchbuf0_mem;
|
wire fetchbuf0_memld;
|
wire fetchbuf0_memld;
|
wire fetchbuf0_jmp;
|
|
wire fetchbuf0_rfw;
|
wire fetchbuf0_rfw;
|
wire [47:0] fetchbuf1_instr;
|
wire [47:0] fetchbuf1_instr;
|
wire [2:0] fetchbuf1_insln;
|
wire [2:0] fetchbuf1_insln;
|
wire [`ABITS] fetchbuf1_pc;
|
wire [`ABITS] fetchbuf1_pc;
|
wire fetchbuf1_v;
|
wire fetchbuf1_v;
|
wire fetchbuf1_thrd;
|
wire fetchbuf1_thrd;
|
wire fetchbuf1_mem;
|
wire fetchbuf1_mem;
|
wire fetchbuf1_memld;
|
wire fetchbuf1_memld;
|
wire fetchbuf1_jmp;
|
|
wire fetchbuf1_rfw;
|
wire fetchbuf1_rfw;
|
|
|
wire [47:0] fetchbufA_instr;
|
wire [47:0] fetchbufA_instr;
|
wire [`ABITS] fetchbufA_pc;
|
wire [`ABITS] fetchbufA_pc;
|
wire fetchbufA_v;
|
wire fetchbufA_v;
|
| Line 662... |
Line 593... |
reg [5:0] id1_ven;
|
reg [5:0] id1_ven;
|
reg [7:0] id1_vl;
|
reg [7:0] id1_vl;
|
reg id1_thrd;
|
reg id1_thrd;
|
reg id1_pt;
|
reg id1_pt;
|
reg [4:0] id1_Rt;
|
reg [4:0] id1_Rt;
|
wire [127:0] id1_bus;
|
wire [143:0] id1_bus;
|
|
|
reg id2_v;
|
reg id2_v;
|
reg [4:0] id2_id;
|
reg [4:0] id2_id;
|
reg [47:0] id2_instr;
|
reg [47:0] id2_instr;
|
reg [5:0] id2_ven;
|
reg [5:0] id2_ven;
|
reg [7:0] id2_vl;
|
reg [7:0] id2_vl;
|
reg id2_thrd;
|
reg id2_thrd;
|
reg id2_pt;
|
reg id2_pt;
|
reg [4:0] id2_Rt;
|
reg [4:0] id2_Rt;
|
wire [127:0] id2_bus;
|
wire [143:0] id2_bus;
|
|
|
reg id3_v;
|
reg id3_v;
|
reg [4:0] id3_id;
|
reg [4:0] id3_id;
|
reg [47:0] id3_instr;
|
reg [47:0] id3_instr;
|
reg [5:0] id3_ven;
|
reg [5:0] id3_ven;
|
reg [7:0] id3_vl;
|
reg [7:0] id3_vl;
|
reg id3_thrd;
|
reg id3_thrd;
|
reg id3_pt;
|
reg id3_pt;
|
reg [4:0] id3_Rt;
|
reg [4:0] id3_Rt;
|
wire [127:0] id3_bus;
|
wire [143:0] id3_bus;
|
|
|
reg alu0_ld;
|
reg alu0_ld;
|
reg alu0_dataready;
|
reg alu0_dataready;
|
wire alu0_done;
|
wire alu0_done;
|
wire alu0_idle;
|
wire alu0_idle;
|
| Line 778... |
Line 709... |
reg fcu_done;
|
reg fcu_done;
|
reg fcu_idle = 1'b1;
|
reg fcu_idle = 1'b1;
|
reg [3:0] fcu_sourceid;
|
reg [3:0] fcu_sourceid;
|
reg [47:0] fcu_instr;
|
reg [47:0] fcu_instr;
|
reg [2:0] fcu_insln;
|
reg [2:0] fcu_insln;
|
|
reg fcu_branch;
|
reg fcu_call;
|
reg fcu_call;
|
|
reg fcu_ret;
|
|
reg fcu_jal;
|
|
reg fcu_brk;
|
|
reg fcu_rti;
|
reg fcu_bt;
|
reg fcu_bt;
|
reg [63:0] fcu_argA;
|
reg [63:0] fcu_argA;
|
reg [63:0] fcu_argB;
|
reg [63:0] fcu_argB;
|
reg [63:0] fcu_argC;
|
reg [63:0] fcu_argC;
|
reg [63:0] fcu_argI; // only used by BEQ
|
reg [63:0] fcu_argI; // only used by BEQ
|
reg [63:0] fcu_argT;
|
reg [63:0] fcu_argT;
|
reg [63:0] fcu_argT2;
|
reg [63:0] fcu_argT2;
|
reg [`ABITS] fcu_retadr;
|
|
reg fcu_retadr_v;
|
|
reg [`ABITS] fcu_pc;
|
reg [`ABITS] fcu_pc;
|
reg [`ABITS] fcu_nextpc;
|
reg [`ABITS] fcu_nextpc;
|
reg [`ABITS] fcu_brdisp;
|
reg [`ABITS] fcu_brdisp;
|
wire [63:0] fcu_bus;
|
wire [63:0] fcu_bus;
|
wire [3:0] fcu_id;
|
wire [3:0] fcu_id;
|
| Line 1124... |
Line 1058... |
wire predict_takenD1;
|
wire predict_takenD1;
|
|
|
wire [`ABITS] btgtA, btgtB, btgtC, btgtD;
|
wire [`ABITS] btgtA, btgtB, btgtC, btgtD;
|
wire btbwr0 = iqentry_v[head0] && iqentry_done[head0] &&
|
wire btbwr0 = iqentry_v[head0] && iqentry_done[head0] &&
|
(
|
(
|
iqentry_instr[head0][`INSTRUCTION_OP]==`JAL ||
|
iqentry_jal[head0] ||
|
iqentry_instr[head0][`INSTRUCTION_OP]==`BRK ||
|
iqentry_brk[head0] ||
|
IsRTI(iqentry_instr[head0]));
|
iqentry_rti[head0]);
|
wire btbwr1 = iqentry_v[head1] && iqentry_done[head1] &&
|
wire btbwr1 = iqentry_v[head1] && iqentry_done[head1] &&
|
(
|
(
|
iqentry_instr[head1][`INSTRUCTION_OP]==`JAL ||
|
iqentry_jal[head1] ||
|
iqentry_instr[head1][`INSTRUCTION_OP]==`BRK ||
|
iqentry_brk[head1] ||
|
IsRTI(iqentry_instr[head1]));
|
iqentry_rti[head1]);
|
|
|
wire fcu_clk;
|
wire fcu_clk;
|
`ifdef FCU_ENH
|
`ifdef FCU_ENH
|
//BUFGCE ufcuclk
|
//BUFGCE ufcuclk
|
//(
|
//(
|
| Line 1696... |
Line 1630... |
3'd0: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd0: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd1: fnRa = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RA]};
|
3'd1: fnRa = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RA]};
|
3'd2: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd2: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd3: fnRa = {rs_stack[thrd][5:0],1'b0,isn[`INSTRUCTION_RA]};
|
3'd3: fnRa = {rs_stack[thrd][5:0],1'b0,isn[`INSTRUCTION_RA]};
|
3'd4: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd4: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd5: fnRa = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd5: fnRa = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd6: fnRa = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
3'd6: fnRa = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
default:fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
default:fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
`VMOV:
|
`VMOV:
|
case (isn[`INSTRUCTION_S1])
|
case (isn[`INSTRUCTION_S1])
|
5'h0: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
5'h0: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
5'h1: fnRa = {6'h3F,1'b1,isn[`INSTRUCTION_RA]};
|
5'h1: fnRa = {6'h3F,1'b1,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
default: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
default: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
`FLOAT: fnRa = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
`FLOAT: fnRa = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
default: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
default: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [RBIT:0] fnRb;
|
function [RBIT:0] fnRb;
|
| Line 1742... |
Line 1676... |
fnRb = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
fnRb = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
`VSHL,`VSHR,`VASR:
|
`VSHL,`VSHR,`VASR:
|
fnRb = {isn[25],isn[22]}==2'b00 ? {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]} : {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
fnRb = {isn[25],isn[22]}==2'b00 ? {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]} : {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
default: fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
default: fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
`FLOAT: fnRb = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
`FLOAT: fnRb = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
default: fnRb = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
default: fnRb = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [RBIT:0] fnRc;
|
function [RBIT:0] fnRc;
|
| Line 1765... |
Line 1699... |
`IVECTOR:
|
`IVECTOR:
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`VSxx,`VSxxS,`VSxxU,`VSxxSU: fnRc = {6'h3F,1'b1,2'b0,isn[18:16]};
|
`VSxx,`VSxxS,`VSxxU,`VSxxSU: fnRc = {6'h3F,1'b1,2'b0,isn[18:16]};
|
default: fnRc = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
default: fnRc = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
endcase
|
endcase
|
`FLOAT: fnRc = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
`FLOAT: fnRc = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
default: fnRc = {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
default: fnRc = {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [RBIT:0] fnRt;
|
function [RBIT:0] fnRt;
|
| Line 1801... |
Line 1735... |
case(isn[25:23])
|
case(isn[25:23])
|
3'd0: fnRt = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RB]};
|
3'd0: fnRt = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RB]};
|
3'd1: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd1: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd2: fnRt = {rs_stack[thrd][5:0],1'b0,isn[`INSTRUCTION_RB]};
|
3'd2: fnRt = {rs_stack[thrd][5:0],1'b0,isn[`INSTRUCTION_RB]};
|
3'd3: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd3: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd4: fnRt = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd4: fnRt = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd5: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd5: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd6: fnRt = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
3'd6: fnRt = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
default:fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
default:fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
`VMOV:
|
`VMOV:
|
case (isn[`INSTRUCTION_S1])
|
case (isn[`INSTRUCTION_S1])
|
5'h0: fnRt = {6'h3F,1'b1,isn[`INSTRUCTION_RB]};
|
5'h0: fnRt = {6'h3F,1'b1,isn[`INSTRUCTION_RB]};
|
| Line 1845... |
Line 1779... |
`FLOAT:
|
`FLOAT:
|
case(isn[31:26])
|
case(isn[31:26])
|
`FTX,`FCX,`FEX,`FDX,`FRM:
|
`FTX,`FCX,`FEX,`FDX,`FRM:
|
fnRt = 12'd0;
|
fnRt = 12'd0;
|
`FSYNC: fnRt = 12'd0;
|
`FSYNC: fnRt = 12'd0;
|
default: fnRt = {fp1_rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
default: fnRt = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
endcase
|
endcase
|
`BRK: fnRt = 12'd0;
|
`BRK: fnRt = 12'd0;
|
`REX: fnRt = 12'd0;
|
`REX: fnRt = 12'd0;
|
`CHK: fnRt = 12'd0;
|
`CHK: fnRt = 12'd0;
|
`EXEC: fnRt = 12'd0;
|
`EXEC: fnRt = 12'd0;
|
| Line 1899... |
Line 1833... |
3'd0: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd0: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd1: fnRa = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RA]};
|
3'd1: fnRa = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RA]};
|
3'd2: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd2: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd3: fnRa = {rs_stack[5:0],1'b0,isn[`INSTRUCTION_RA]};
|
3'd3: fnRa = {rs_stack[5:0],1'b0,isn[`INSTRUCTION_RA]};
|
3'd4: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd4: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd5: fnRa = {fp1_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd5: fnRa = {fp_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd6: fnRa = {fp1_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
3'd6: fnRa = {fp_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
default:fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
default:fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
`VMOV:
|
`VMOV:
|
case (isn[`INSTRUCTION_S1])
|
case (isn[`INSTRUCTION_S1])
|
5'h0: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
5'h0: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
5'h1: fnRa = {6'h3F,1'b1,isn[`INSTRUCTION_RA]};
|
5'h1: fnRa = {6'h3F,1'b1,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
default: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
default: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
`FLOAT: fnRa = {fp1_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
`FLOAT: fnRa = {fp_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
default: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
default: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [RBIT:0] fnRb;
|
function [RBIT:0] fnRb;
|
| Line 1945... |
Line 1879... |
fnRb = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
fnRb = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
`VSHL,`VSHR,`VASR:
|
`VSHL,`VSHR,`VASR:
|
fnRb = {isn[25],isn[22]}==2'b00 ? {rgs,1'b0,isn[`INSTRUCTION_RB]} : {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
fnRb = {isn[25],isn[22]}==2'b00 ? {rgs,1'b0,isn[`INSTRUCTION_RB]} : {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
default: fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
default: fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
`FLOAT: fnRb = {fp1_rgs,1'b0,isn[`INSTRUCTION_RB]};
|
`FLOAT: fnRb = {fp_rgs,1'b0,isn[`INSTRUCTION_RB]};
|
default: fnRb = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
default: fnRb = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [RBIT:0] fnRc;
|
function [RBIT:0] fnRc;
|
| Line 1968... |
Line 1902... |
`IVECTOR:
|
`IVECTOR:
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`VSxx,`VSxxS,`VSxxU,`VSxxSU: fnRc = {6'h3F,1'b1,2'b0,isn[18:16]};
|
`VSxx,`VSxxS,`VSxxU,`VSxxSU: fnRc = {6'h3F,1'b1,2'b0,isn[18:16]};
|
default: fnRc = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
default: fnRc = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
endcase
|
endcase
|
`FLOAT: fnRc = {fp1_rgs,1'b0,isn[`INSTRUCTION_RC]};
|
`FLOAT: fnRc = {fp_rgs,1'b0,isn[`INSTRUCTION_RC]};
|
default: fnRc = {rgs,1'b0,isn[`INSTRUCTION_RC]};
|
default: fnRc = {rgs,1'b0,isn[`INSTRUCTION_RC]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [RBIT:0] fnRt;
|
function [RBIT:0] fnRt;
|
| Line 2023... |
Line 1957... |
case(isn[25:23])
|
case(isn[25:23])
|
3'd0: fnRt = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RB]};
|
3'd0: fnRt = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RB]};
|
3'd1: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd1: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd2: fnRt = {rs_stack[5:0],1'b0,isn[`INSTRUCTION_RB]};
|
3'd2: fnRt = {rs_stack[5:0],1'b0,isn[`INSTRUCTION_RB]};
|
3'd3: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd3: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd4: fnRt = {fp1_rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd4: fnRt = {fp_rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd5: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd5: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd6: fnRt = {fp1_rgs,1'b0,isn[`INSTRUCTION_RB]};
|
3'd6: fnRt = {fp_rgs,1'b0,isn[`INSTRUCTION_RB]};
|
default:fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
default:fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
`VMOV:
|
`VMOV:
|
case (isn[`INSTRUCTION_S1])
|
case (isn[`INSTRUCTION_S1])
|
5'h0: fnRt = {6'h3F,1'b1,isn[`INSTRUCTION_RB]};
|
5'h0: fnRt = {6'h3F,1'b1,isn[`INSTRUCTION_RB]};
|
| Line 2067... |
Line 2001... |
`FLOAT:
|
`FLOAT:
|
case(isn[31:26])
|
case(isn[31:26])
|
`FTX,`FCX,`FEX,`FDX,`FRM:
|
`FTX,`FCX,`FEX,`FDX,`FRM:
|
fnRt = 12'd0;
|
fnRt = 12'd0;
|
`FSYNC: fnRt = 12'd0;
|
`FSYNC: fnRt = 12'd0;
|
default: fnRt = {fp1_rgs,1'b0,isn[`INSTRUCTION_RC]};
|
default: fnRt = {fp_rgs,1'b0,isn[`INSTRUCTION_RC]};
|
endcase
|
endcase
|
`BRK: fnRt = 12'd0;
|
`BRK: fnRt = 12'd0;
|
`REX: fnRt = 12'd0;
|
`REX: fnRt = 12'd0;
|
`CHK: fnRt = 12'd0;
|
`CHK: fnRt = 12'd0;
|
`EXEC: fnRt = 12'd0;
|
`EXEC: fnRt = 12'd0;
|
| Line 2177... |
Line 2111... |
`INC: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`INC: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`CAS: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`CAS: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`JAL: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`JAL: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`RET: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`RET: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`CSRRW: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`CSRRW: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
`BITFIELD: case(isn[31:28])
|
`BITFIELD: case(isn[47:44])
|
`BFINSI: Source1Valid = TRUE;
|
`BFINSI: Source1Valid = TRUE;
|
default: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
default: Source1Valid = isn[`INSTRUCTION_RA]==5'd0 || isn[30]==1'b0;
|
endcase
|
endcase
|
`IVECTOR:
|
`IVECTOR:
|
Source1Valid = FALSE;
|
Source1Valid = FALSE;
|
default: Source1Valid = TRUE;
|
default: Source1Valid = TRUE;
|
endcase
|
endcase
|
| Line 2246... |
Line 2180... |
default: Source2Valid = FALSE;
|
default: Source2Valid = FALSE;
|
endcase
|
endcase
|
`LV: Source2Valid = TRUE;
|
`LV: Source2Valid = TRUE;
|
`SV: Source2Valid = FALSE;
|
`SV: Source2Valid = FALSE;
|
`AMO: Source2Valid = isn[31] || isn[`INSTRUCTION_RB]==5'd0;
|
`AMO: Source2Valid = isn[31] || isn[`INSTRUCTION_RB]==5'd0;
|
|
`BITFIELD: Source2Valid = isn[`INSTRUCTION_RB]==5'd0 || isn[31]==1'b0;
|
default: Source2Valid = TRUE;
|
default: Source2Valid = TRUE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function Source3Valid;
|
function Source3Valid;
|
| Line 2287... |
Line 2222... |
`SWX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`SWX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`SWCX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`SWCX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`CASX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
`CASX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
default: Source3Valid = TRUE;
|
default: Source3Valid = TRUE;
|
endcase
|
endcase
|
|
`BITFIELD: Source3Valid = isn[`INSTRUCTION_RC]==5'd0 || isn[32]==1'b0;
|
default: Source3Valid = TRUE;
|
default: Source3Valid = TRUE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function SourceTValid;
|
|
input [31:0] isn;
|
|
SourceTValid = FALSE;
|
|
endfunction
|
|
function SourceT2Valid;
|
|
input [31:0] isn;
|
|
case(isn[`INSTRUCTION_OP])
|
|
`Bcc: SourceT2Valid = TRUE;
|
|
`ORI: SourceT2Valid = TRUE;
|
|
default: SourceT2Valid = FALSE;
|
|
endcase
|
|
endfunction
|
|
|
|
// Used to indicate to the queue logic that the instruction needs to be
|
// Used to indicate to the queue logic that the instruction needs to be
|
// recycled to the queue VL number of times.
|
// recycled to the queue VL number of times.
|
function IsVector;
|
function IsVector;
|
input [47:0] isn;
|
input [47:0] isn;
|
case(isn[`INSTRUCTION_OP])
|
case(isn[`INSTRUCTION_OP])
|
`MEMNDX: case(isn[`INSTRUCTION_S2])
|
`MEMNDX:
|
|
case(isn[`INSTRUCTION_S2])
|
`LVX,`SVX: IsVector = TRUE;
|
`LVX,`SVX: IsVector = TRUE;
|
default: IsVector = FALSE;
|
default: IsVector = FALSE;
|
endcase
|
endcase
|
`IVECTOR:
|
`IVECTOR:
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
| Line 2439... |
Line 2363... |
`LVHX: IsLoad = TRUE;
|
`LVHX: IsLoad = TRUE;
|
`LVHUX: IsLoad = TRUE;
|
`LVHUX: IsLoad = TRUE;
|
`LVWX: IsLoad = TRUE;
|
`LVWX: IsLoad = TRUE;
|
`LWRX: IsLoad = TRUE;
|
`LWRX: IsLoad = TRUE;
|
`LVX: IsLoad = TRUE;
|
`LVX: IsLoad = TRUE;
|
`LVx: IsLoad = TRUE;
|
|
default: IsLoad = FALSE;
|
default: IsLoad = FALSE;
|
endcase
|
endcase
|
else
|
else
|
IsLoad = FALSE;
|
IsLoad = FALSE;
|
`LB: IsLoad = TRUE;
|
`LB: IsLoad = TRUE;
|
| Line 2576... |
Line 2499... |
function IsWait;
|
function IsWait;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsWait = isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`WAIT;
|
IsWait = isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`WAIT;
|
endfunction
|
endfunction
|
|
|
function IsBrk;
|
|
input [47:0] isn;
|
|
IsBrk = isn[`INSTRUCTION_OP]==`BRK && isn[`INSTRUCTION_L2]==2'b00;
|
|
endfunction
|
|
|
|
function IsIrq;
|
|
input [47:0] isn;
|
|
IsIrq = isn[`INSTRUCTION_OP]==`BRK && isn[`INSTRUCTION_L2]==2'b00 && isn[23:20]==4'h0;
|
|
endfunction
|
|
|
|
function IsRTI;
|
|
input [47:0] isn;
|
|
IsRTI = isn[`INSTRUCTION_OP]==`RR && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`RTI;
|
|
endfunction
|
|
|
|
function IsJAL;
|
|
input [47:0] isn;
|
|
IsJAL = isn[`INSTRUCTION_OP]==`JAL && isn[7]==1'b0;
|
|
endfunction
|
|
|
|
function IsCall;
|
function IsCall;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsCall = isn[`INSTRUCTION_OP]==`CALL && isn[7]==1'b0;
|
IsCall = isn[`INSTRUCTION_OP]==`CALL && isn[7]==1'b0;
|
endfunction
|
endfunction
|
|
|
function IsJmp;
|
function IsJmp;
|
input [47:0] isn;
|
input [47:0] isn;
|
IsJmp = isn[`INSTRUCTION_OP]==`JMP && isn[7]==1'b0;
|
IsJmp = isn[`INSTRUCTION_OP]==`JMP && isn[7]==1'b0;
|
endfunction
|
endfunction
|
|
|
function IsRet;
|
|
input [47:0] isn;
|
|
IsRet = isn[`INSTRUCTION_OP]==`RET && isn[7]==1'b0;
|
|
endfunction
|
|
|
|
function IsFlowCtrl;
|
function IsFlowCtrl;
|
input [47:0] isn;
|
input [47:0] isn;
|
casez(isn[`INSTRUCTION_OP])
|
casez(isn[`INSTRUCTION_OP])
|
`BRK: IsFlowCtrl = TRUE;
|
`BRK: IsFlowCtrl = TRUE;
|
`R2: case(isn[`INSTRUCTION_S2])
|
`R2: case(isn[`INSTRUCTION_S2])
|
| Line 3356... |
Line 3254... |
// FETCH
|
// FETCH
|
// ---------------------------------------------------------------------------
|
// ---------------------------------------------------------------------------
|
//
|
//
|
assign fetchbuf0_mem = IsMem(fetchbuf0_instr);
|
assign fetchbuf0_mem = IsMem(fetchbuf0_instr);
|
assign fetchbuf0_memld = IsMem(fetchbuf0_instr) & IsLoad(fetchbuf0_instr);
|
assign fetchbuf0_memld = IsMem(fetchbuf0_instr) & IsLoad(fetchbuf0_instr);
|
assign fetchbuf0_jmp = IsFlowCtrl(fetchbuf0_instr);
|
|
assign fetchbuf0_rfw = IsRFW(fetchbuf0_instr,vqe0,vl,fetchbuf0_thrd);
|
assign fetchbuf0_rfw = IsRFW(fetchbuf0_instr,vqe0,vl,fetchbuf0_thrd);
|
|
|
assign fetchbuf1_mem = IsMem(fetchbuf1_instr);
|
assign fetchbuf1_mem = IsMem(fetchbuf1_instr);
|
assign fetchbuf1_memld = IsMem(fetchbuf1_instr) & IsLoad(fetchbuf1_instr);
|
assign fetchbuf1_memld = IsMem(fetchbuf1_instr) & IsLoad(fetchbuf1_instr);
|
assign fetchbuf1_jmp = IsFlowCtrl(fetchbuf1_instr);
|
|
assign fetchbuf1_rfw = IsRFW(fetchbuf1_instr,vqe1,vl,fetchbuf1_thrd);
|
assign fetchbuf1_rfw = IsRFW(fetchbuf1_instr,vqe1,vl,fetchbuf1_thrd);
|
|
|
FT64_fetchbuf #(AMSB,RSTPC) ufb1
|
FT64_fetchbuf #(AMSB,RSTPC) ufb1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
| Line 5266... |
Line 5162... |
.stomp(iqentry_stomp)
|
.stomp(iqentry_stomp)
|
);
|
);
|
|
|
always @*
|
always @*
|
begin
|
begin
|
if (iqentry_stomp[0] && IsRet(iqentry_instr[0]))
|
if (iqentry_stomp[0] && iqentry_ret[0])
|
stompedOnRets = stompedOnRets + 4'd1;
|
stompedOnRets = stompedOnRets + 4'd1;
|
if (iqentry_stomp[1] && IsRet(iqentry_instr[1]))
|
if (iqentry_stomp[1] && iqentry_ret[1])
|
stompedOnRets = stompedOnRets + 4'd1;
|
stompedOnRets = stompedOnRets + 4'd1;
|
if (iqentry_stomp[2] && IsRet(iqentry_instr[2]))
|
if (iqentry_stomp[2] && iqentry_ret[2])
|
stompedOnRets = stompedOnRets + 4'd1;
|
stompedOnRets = stompedOnRets + 4'd1;
|
if (iqentry_stomp[3] && IsRet(iqentry_instr[3]))
|
if (iqentry_stomp[3] && iqentry_ret[3])
|
stompedOnRets = stompedOnRets + 4'd1;
|
stompedOnRets = stompedOnRets + 4'd1;
|
if (iqentry_stomp[4] && IsRet(iqentry_instr[4]))
|
if (iqentry_stomp[4] && iqentry_ret[4])
|
stompedOnRets = stompedOnRets + 4'd1;
|
stompedOnRets = stompedOnRets + 4'd1;
|
if (iqentry_stomp[5] && IsRet(iqentry_instr[5]))
|
if (iqentry_stomp[5] && iqentry_ret[5])
|
stompedOnRets = stompedOnRets + 4'd1;
|
stompedOnRets = stompedOnRets + 4'd1;
|
if (iqentry_stomp[6] && IsRet(iqentry_instr[6]))
|
if (iqentry_stomp[6] && iqentry_ret[6])
|
stompedOnRets = stompedOnRets + 4'd1;
|
stompedOnRets = stompedOnRets + 4'd1;
|
if (iqentry_stomp[7] && IsRet(iqentry_instr[7]))
|
if (iqentry_stomp[7] && iqentry_ret[7])
|
stompedOnRets = stompedOnRets + 4'd1;
|
stompedOnRets = stompedOnRets + 4'd1;
|
end
|
end
|
|
|
reg id1_vi, id2_vi, id3_vi;
|
reg id1_vi, id2_vi, id3_vi;
|
wire [4:0] id1_ido, id2_ido, id3_ido;
|
wire [4:0] id1_ido, id2_ido, id3_ido;
|
| Line 5458... |
Line 5354... |
.a(fpu1_argA),
|
.a(fpu1_argA),
|
.b(fpu1_argB),
|
.b(fpu1_argB),
|
.imm(fpu1_argI),
|
.imm(fpu1_argI),
|
.o(fpu1_bus),
|
.o(fpu1_bus),
|
.csr_i(),
|
.csr_i(),
|
.status(fpu1_status),
|
.status(fpu_status),
|
.exception(),
|
.exception(),
|
.done(fpu1_done)
|
.done(fpu1_done)
|
);
|
);
|
end
|
end
|
if (`NUM_FPU > 1) begin
|
if (`NUM_FPU > 1) begin
|
| Line 5485... |
Line 5381... |
.a(fpu2_argA),
|
.a(fpu2_argA),
|
.b(fpu2_argB),
|
.b(fpu2_argB),
|
.imm(fpu2_argI),
|
.imm(fpu2_argI),
|
.o(fpu2_bus),
|
.o(fpu2_bus),
|
.csr_i(),
|
.csr_i(),
|
.status(fpu2_status),
|
.status(fpu_status),
|
.exception(),
|
.exception(),
|
.done(fpu2_done)
|
.done(fpu2_done)
|
);
|
);
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
assign fpu_exc = fpu1_available ? (|fpu1_status[15:0] ? `FLT_FLT : `FLT_NONE) : `FLT_UNIMP;
|
assign fpu_exc = (fpu1_available|fpu2_available) ?
|
|
((|fpu1_status[15:0] || |fpu2_status[15:0]) ? `FLT_FLT : `FLT_NONE) : `FLT_UNIMP;
|
|
|
assign alu0_v = alu0_dataready,
|
assign alu0_v = alu0_dataready,
|
alu1_v = alu1_dataready;
|
alu1_v = alu1_dataready;
|
assign alu0_id = alu0_sourceid,
|
assign alu0_id = alu0_sourceid,
|
alu1_id = alu1_sourceid;
|
alu1_id = alu1_sourceid;
|
| Line 5576... |
Line 5473... |
|
|
// To avoid false branch mispredicts the branch isn't evaluated until the
|
// To avoid false branch mispredicts the branch isn't evaluated until the
|
// following instruction queues. The address of the next instruction is
|
// following instruction queues. The address of the next instruction is
|
// looked at to see if the BTB predicted correctly.
|
// looked at to see if the BTB predicted correctly.
|
|
|
wire fcu_brk_miss = (IsBrk(fcu_instr) || IsRTI(fcu_instr)) && fcu_v;
|
wire fcu_brk_miss = (fcu_brk || fcu_rti) && fcu_v;
|
wire fcu_ret_miss = IsRet(fcu_instr) && fcu_v && (fcu_argB != iqentry_pc[idp2(fcu_id)]);
|
wire fcu_ret_miss = fcu_ret && fcu_v && (fcu_argB != iqentry_pc[nid]);
|
wire fcu_jal_miss = IsJAL(fcu_instr) && fcu_v && fcu_argA + fcu_argI != iqentry_pc[idp2(fcu_id)];
|
wire fcu_jal_miss = fcu_jal && fcu_v && fcu_argA + fcu_argI != iqentry_pc[nid];
|
wire fcu_followed = iqentry_sn[nid] > iqentry_sn[fcu_id[`QBITS]];
|
wire fcu_followed = iqentry_sn[nid] > iqentry_sn[fcu_id[`QBITS]];
|
always @*
|
always @*
|
if (fcu_dataready) begin
|
if (fcu_dataready) begin
|
// if (fcu_timeout[7])
|
// if (fcu_timeout[7])
|
// fcu_branchmiss = TRUE;
|
// fcu_branchmiss = TRUE;
|
| Line 5602... |
Line 5499... |
if (fcu_instr[`INSTRUCTION_OP] == `REX && (im < ~ol) && fcu_v)
|
if (fcu_instr[`INSTRUCTION_OP] == `REX && (im < ~ol) && fcu_v)
|
`endif
|
`endif
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
else if (fcu_ret_miss)
|
else if (fcu_ret_miss)
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
else if (IsBranch(fcu_instr) && fcu_v && (((fcu_takb && (~fcu_bt || (fcu_misspc != iqentry_pc[nid]))) ||
|
else if (fcu_branch && fcu_v && (((fcu_takb && (~fcu_bt || (fcu_misspc != iqentry_pc[nid]))) ||
|
(~fcu_takb && ( fcu_bt || (fcu_pc + 32'd4 != iqentry_pc[nid])))) || iqentry_v[nid]))
|
(~fcu_takb && ( fcu_bt || (fcu_pc + 32'd4 != iqentry_pc[nid])))) || iqentry_v[nid]))
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
else if (fcu_jal_miss)
|
else if (fcu_jal_miss)
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
else if (fcu_instr[`INSTRUCTION_OP] == `CHK && ~fcu_takb && fcu_v)
|
else if (fcu_instr[`INSTRUCTION_OP] == `CHK && ~fcu_takb && fcu_v)
|
| Line 5639... |
Line 5536... |
fcu_branchmiss = FALSE;
|
fcu_branchmiss = FALSE;
|
end
|
end
|
end
|
end
|
else
|
else
|
fcu_branchmiss = FALSE;
|
fcu_branchmiss = FALSE;
|
/*
|
|
assign fcu_branchmiss = fcu_dataready &&
|
|
// and the following instruction is queued
|
|
iqentry_v[idp1(fcu_id)] && iqentry_sn[idp1(fcu_id)]==iqentry_sn[fcu_id[`QBITS]]+5'd1 &&
|
|
((IsBrk(fcu_instr) || IsRTI(fcu_instr)) ||
|
|
((fcu_instr[`INSTRUCTION_OP] == `REX && (im < ~ol)) ||
|
|
(fcu_instr[`INSTRUCTION_OP] == `CHK && ~fcu_bus[0]) ||
|
|
(IsRTI(fcu_instr) && epc != iqentry_pc[idp1(fcu_id[`QBITS])]) ||
|
|
// If it's a ret and the return address doesn't match the address of the
|
|
// next queued instruction then the return prediction was wrong.
|
|
(/*IsRet(fcu_instr) &&
|
|
IsRet(fcu_instr) && ((fcu_argB != iqentry_pc[idp1(fcu_id)]) || (iqentry_sn[fcu_id[`QBITS]]+5'd1!=iqentry_sn[idp1(fcu_id)]) || !iqentry_v[idp1(fcu_id)])) ||
|
|
(IsBrk(fcu_instr) && {tvec[0][31:8], ol, 5'h0} != iqentry_pc[idp1(fcu_id)]) ||
|
|
// (fcu_instr[`INSTRUCTION_OP] == `BccR && fcu_argC != iqentry_pc[(fcu_id[`QBITS]+3'd1)&7] && fcu_bus[0]) ||
|
|
(IsBranch(fcu_instr) && ((fcu_bus[0] && (~fcu_bt || (fcu_misspc != iqentry_pc[idp1(fcu_id)]))) ||
|
|
(~fcu_bus[0] && ( fcu_bt || (fcu_pc + 32'd4 != iqentry_pc[idp1(fcu_id)]))))) ||
|
|
(IsJAL(fcu_instr)) && fcu_argA + fcu_argI != iqentry_pc[idp1(fcu_id)]));
|
|
*/
|
|
|
|
// Flow control ops don't issue until the next instruction queues.
|
// Flow control ops don't issue until the next instruction queues.
|
// The fcu_timeout tracks how long the flow control op has been in the "out" state.
|
// The fcu_timeout tracks how long the flow control op has been in the "out" state.
|
// It should never be that way more than a couple of cycles. Sometimes the fcu_wr pulse got missed
|
// It should never be that way more than a couple of cycles. Sometimes the fcu_wr pulse got missed
|
// because the following instruction got stomped on during a branchmiss, hence iqentry_v isn't true.
|
// because the following instruction got stomped on during a branchmiss, hence iqentry_v isn't true.
|
| Line 5731... |
Line 5610... |
commit1_tgt <= 12'h000;
|
commit1_tgt <= 12'h000;
|
commit1_we <= 8'h00;
|
commit1_we <= 8'h00;
|
end
|
end
|
end
|
end
|
|
|
assign int_commit = (commit0_v && IsIrq(iqentry_instr[head0])) ||
|
assign int_commit = (commit0_v && iqentry_irq[head0]) ||
|
(commit0_v && commit1_v && IsIrq(iqentry_instr[head1]) && `NUM_CMT > 1);
|
(commit0_v && commit1_v && iqentry_irq[head1] && `NUM_CMT > 1);
|
|
|
// Detect if a given register will become valid during the current cycle.
|
// Detect if a given register will become valid during the current cycle.
|
// We want a signal that is active during the current clock cycle for the read
|
// We want a signal that is active during the current clock cycle for the read
|
// through register file, which trims a cycle off register access for every
|
// through register file, which trims a cycle off register access for every
|
// instruction. But two different kinds of assignment statements can't be
|
// instruction. But two different kinds of assignment statements can't be
|
| Line 6003... |
Line 5882... |
iqentry_fpu2_issue[n] <= FALSE;
|
iqentry_fpu2_issue[n] <= FALSE;
|
iqentry_fsync[n] <= FALSE;
|
iqentry_fsync[n] <= FALSE;
|
iqentry_fc[n] <= FALSE;
|
iqentry_fc[n] <= FALSE;
|
iqentry_fcu_issue[n] <= FALSE;
|
iqentry_fcu_issue[n] <= FALSE;
|
iqentry_jmp[n] <= FALSE;
|
iqentry_jmp[n] <= FALSE;
|
|
iqentry_jal[n] <= FALSE;
|
|
iqentry_ret[n] <= FALSE;
|
|
iqentry_brk[n] <= FALSE;
|
|
iqentry_irq[n] <= FALSE;
|
|
iqentry_rti[n] <= FALSE;
|
iqentry_ldcmp[n] <= FALSE;
|
iqentry_ldcmp[n] <= FALSE;
|
iqentry_load[n] <= FALSE;
|
iqentry_load[n] <= FALSE;
|
iqentry_rtop[n] <= FALSE;
|
iqentry_rtop[n] <= FALSE;
|
iqentry_sei[n] <= FALSE;
|
iqentry_sei[n] <= FALSE;
|
iqentry_shft48[n] <= FALSE;
|
iqentry_shft48[n] <= FALSE;
|
| Line 6093... |
Line 5977... |
alu1_tgt <= 6'h00;
|
alu1_tgt <= 6'h00;
|
alu1_ven <= 6'd0;
|
alu1_ven <= 6'd0;
|
`endif
|
`endif
|
fcu_dataready <= 0;
|
fcu_dataready <= 0;
|
fcu_instr <= `NOP_INSN;
|
fcu_instr <= `NOP_INSN;
|
fcu_retadr_v <= 0;
|
|
dramA_v <= 0;
|
dramA_v <= 0;
|
dramB_v <= 0;
|
dramB_v <= 0;
|
dramC_v <= 0;
|
dramC_v <= 0;
|
I <= 0;
|
I <= 0;
|
icstate <= IDLE;
|
icstate <= IDLE;
|
| Line 6122... |
Line 6005... |
pcr <= 32'd0;
|
pcr <= 32'd0;
|
pcr2 <= 64'd0;
|
pcr2 <= 64'd0;
|
for (n = 0; n < PREGS; n = n + 1)
|
for (n = 0; n < PREGS; n = n + 1)
|
rf_v[n] <= `VAL;
|
rf_v[n] <= `VAL;
|
tgtq <= FALSE;
|
tgtq <= FALSE;
|
fp1_rm <= 3'd0; // round nearest even - default rounding mode
|
fp_rm <= 3'd0; // round nearest even - default rounding mode
|
fp2_rm <= 3'd0;
|
fpu_csr[37:32] <= 5'd31; // register set #31
|
waitctr <= 64'd0;
|
waitctr <= 64'd0;
|
for (n = 0; n < 16; n = n + 1)
|
for (n = 0; n < 16; n = n + 1)
|
badaddr[n] <= 64'd0;
|
badaddr[n] <= 64'd0;
|
sbl <= 32'h0;
|
sbl <= 32'h0;
|
sbu <= 32'hFFFFFFFF;
|
sbu <= 32'hFFFFFFFF;
|
| Line 6216... |
Line 6099... |
alu0_ld <= FALSE;
|
alu0_ld <= FALSE;
|
alu1_ld <= FALSE;
|
alu1_ld <= FALSE;
|
fpu1_ld <= FALSE;
|
fpu1_ld <= FALSE;
|
fpu2_ld <= FALSE;
|
fpu2_ld <= FALSE;
|
fcu_ld <= FALSE;
|
fcu_ld <= FALSE;
|
fcu_retadr_v <= FALSE;
|
|
dramA_v <= FALSE;
|
dramA_v <= FALSE;
|
dramB_v <= FALSE;
|
dramB_v <= FALSE;
|
dramC_v <= FALSE;
|
dramC_v <= FALSE;
|
cr0[17] <= 1'b0;
|
cr0[17] <= 1'b0;
|
if (waitctr != 64'd0)
|
if (waitctr != 64'd0)
|
| Line 6886... |
Line 6768... |
iqentry_a0 [ fpu1_id[`QBITS] ] <= fpu1_status;
|
iqentry_a0 [ fpu1_id[`QBITS] ] <= fpu1_status;
|
iqentry_exc [ fpu1_id[`QBITS] ] <= fpu1_exc;
|
iqentry_exc [ fpu1_id[`QBITS] ] <= fpu1_exc;
|
iqentry_done[ fpu1_id[`QBITS] ] <= fpu1_done;
|
iqentry_done[ fpu1_id[`QBITS] ] <= fpu1_done;
|
iqentry_cmt[ fpu1_id[`QBITS] ] <= fpu1_done;
|
iqentry_cmt[ fpu1_id[`QBITS] ] <= fpu1_done;
|
iqentry_out [ fpu1_id[`QBITS] ] <= `INV;
|
iqentry_out [ fpu1_id[`QBITS] ] <= `INV;
|
//iqentry_agen[ fpu_id[`QBITS] ] <= `VAL; // RET
|
|
fpu1_dataready <= FALSE;
|
fpu1_dataready <= FALSE;
|
end
|
end
|
|
|
if (fpu2_v && `NUM_FPU > 1) begin
|
if (fpu2_v && `NUM_FPU > 1) begin
|
iqentry_res [ fpu2_id[`QBITS] ] <= fpu2_bus;
|
iqentry_res [ fpu2_id[`QBITS] ] <= fpu2_bus;
|
| Line 6902... |
Line 6783... |
//iqentry_agen[ fpu_id[`QBITS] ] <= `VAL; // RET
|
//iqentry_agen[ fpu_id[`QBITS] ] <= `VAL; // RET
|
fpu2_dataready <= FALSE;
|
fpu2_dataready <= FALSE;
|
end
|
end
|
|
|
if (fcu_wr & ~fcu_done) begin
|
if (fcu_wr & ~fcu_done) begin
|
|
fcu_done <= `TRUE;
|
if (fcu_ld)
|
if (fcu_ld)
|
waitctr <= fcu_argA;
|
waitctr <= fcu_argA;
|
iqentry_res [ fcu_id[`QBITS] ] <= fcu_bus;
|
iqentry_res [ fcu_id[`QBITS] ] <= fcu_bus;
|
iqentry_exc [ fcu_id[`QBITS] ] <= fcu_exc;
|
iqentry_exc [ fcu_id[`QBITS] ] <= fcu_exc;
|
if (IsWait(fcu_instr)) begin
|
if (IsWait(fcu_instr)) begin
|
iqentry_done [ fcu_id[`QBITS] ] <= (waitctr==64'd1) || signal_i[fcu_argA[4:0]|fcu_argI[4:0]];
|
iqentry_done [ fcu_id[`QBITS] ] <= (waitctr==64'd1) || signal_i[fcu_argA[4:0]|fcu_argI[4:0]];
|
iqentry_cmt [ fcu_id[`QBITS] ] <= (waitctr==64'd1) || signal_i[fcu_argA[4:0]|fcu_argI[4:0]];
|
iqentry_cmt [ fcu_id[`QBITS] ] <= (waitctr==64'd1) || signal_i[fcu_argA[4:0]|fcu_argI[4:0]];
|
fcu_done <= `TRUE;
|
|
end
|
end
|
else begin
|
else begin
|
iqentry_done[ fcu_id[`QBITS] ] <= `TRUE;
|
iqentry_done[ fcu_id[`QBITS] ] <= `TRUE;
|
iqentry_cmt[ fcu_id[`QBITS] ] <= `TRUE;
|
iqentry_cmt[ fcu_id[`QBITS] ] <= `TRUE;
|
fcu_done <= `TRUE;
|
|
end
|
end
|
// if (IsWait(fcu_instr) ? (waitctr==64'd1) || signal_i[fcu_argA[4:0]|fcu_argI[4:0]] : !IsMem(fcu_instr) && !IsImmp(fcu_instr))
|
|
// iqentry_instr[ dram_id[`QBITS]] <= `NOP_INSN;
|
|
// Only safe place to propagate the miss pc is a0.
|
// Only safe place to propagate the miss pc is a0.
|
iqentry_a0[ fcu_id[`QBITS] ] <= fcu_misspc;
|
iqentry_a0[ fcu_id[`QBITS] ] <= fcu_misspc;
|
// Update branch taken indicator.
|
// Update branch taken indicator.
|
if (IsJAL(fcu_instr) || IsRet(fcu_instr) || IsBrk(fcu_instr) || IsRTI(fcu_instr) ) begin
|
if (fcu_jal || fcu_ret || fcu_brk || fcu_rti) begin
|
iqentry_bt[ fcu_id[`QBITS] ] <= `VAL;
|
iqentry_bt[ fcu_id[`QBITS] ] <= `VAL;
|
// Only safe place to propagate the miss pc is a0.
|
|
// iqentry_a0[ fcu_id[`QBITS] ] <= fcu_misspc;
|
|
end
|
|
else if (IsBranch(fcu_instr)) begin
|
|
iqentry_bt[ fcu_id[`QBITS] ] <= fcu_takb;
|
|
// iqentry_a0[ fcu_id[`QBITS] ] <= fcu_misspc;
|
|
end
|
end
|
|
// Branch target is only updated for branch-to-register
|
|
// else if (fcu_branch) begin
|
|
// iqentry_bt[ fcu_id[`QBITS] ] <= fcu_takb;
|
|
// end
|
iqentry_out [ fcu_id[`QBITS] ] <= `INV;
|
iqentry_out [ fcu_id[`QBITS] ] <= `INV;
|
//iqentry_agen[ fcu_id[`QBITS] ] <= `VAL;//!IsRet(fcu_instr);
|
//iqentry_agen[ fcu_id[`QBITS] ] <= `VAL;//!IsRet(fcu_instr);
|
fcu_dataready <= `VAL;
|
fcu_dataready <= `VAL;
|
//fcu_dataready <= fcu_branchmiss || !iqentry_agen[ fcu_id[`QBITS] ] || !(iqentry_mem[ fcu_id[`QBITS] ] && IsLoad(iqentry_instr[fcu_id[`QBITS]]));
|
//fcu_dataready <= fcu_branchmiss || !iqentry_agen[ fcu_id[`QBITS] ] || !(iqentry_mem[ fcu_id[`QBITS] ] && IsLoad(iqentry_instr[fcu_id[`QBITS]]));
|
//fcu_instr[`INSTRUCTION_OP] <= fcu_branchmiss|| (!IsMem(fcu_instr) && !IsWait(fcu_instr))? `NOP : fcu_instr[`INSTRUCTION_OP]; // to clear branchmiss
|
//fcu_instr[`INSTRUCTION_OP] <= fcu_branchmiss|| (!IsMem(fcu_instr) && !IsWait(fcu_instr))? `NOP : fcu_instr[`INSTRUCTION_OP]; // to clear branchmiss
|
| Line 6941... |
Line 6817... |
// Clear a branch miss when target instruction is fetched.
|
// Clear a branch miss when target instruction is fetched.
|
if (fcu_branchmiss) begin
|
if (fcu_branchmiss) begin
|
if ((fetchbuf0_v && fetchbuf0_pc==misspc) ||
|
if ((fetchbuf0_v && fetchbuf0_pc==misspc) ||
|
(fetchbuf1_v && fetchbuf1_pc==misspc))
|
(fetchbuf1_v && fetchbuf1_pc==misspc))
|
fcu_clearbm <= `TRUE;
|
fcu_clearbm <= `TRUE;
|
//fcu_instr[`INSTRUCTION_OP] <= `NOP;
|
|
//iqentry_instr[fcu_id][`INSTRUCTION_OP] <= `NOP;
|
|
end
|
end
|
// if (dram_v && iqentry_v[ dram_id[`QBITS] ] && iqentry_mem[ dram_id[`QBITS] ] ) begin // if data for stomped instruction, ignore
|
|
if (mem1_available && dramA_v && iqentry_v[ dramA_id[`QBITS] ] && iqentry_load[ dramA_id[`QBITS] ]) begin // if data for stomped instruction, ignore
|
if (mem1_available && dramA_v && iqentry_v[ dramA_id[`QBITS] ] && iqentry_load[ dramA_id[`QBITS] ]) begin
|
iqentry_res [ dramA_id[`QBITS] ] <= dramA_bus;
|
iqentry_res [ dramA_id[`QBITS] ] <= dramA_bus;
|
iqentry_exc [ dramA_id[`QBITS] ] <= dramA_exc;
|
iqentry_exc [ dramA_id[`QBITS] ] <= dramA_exc;
|
iqentry_done[ dramA_id[`QBITS] ] <= `VAL;
|
iqentry_done[ dramA_id[`QBITS] ] <= `VAL;
|
iqentry_out [ dramA_id[`QBITS] ] <= `INV;
|
iqentry_out [ dramA_id[`QBITS] ] <= `INV;
|
iqentry_cmt[ dramA_id[`QBITS] ] <= `VAL;
|
iqentry_cmt[ dramA_id[`QBITS] ] <= `VAL;
|
iqentry_aq [ dramA_id[`QBITS] ] <= `INV;
|
iqentry_aq [ dramA_id[`QBITS] ] <= `INV;
|
// if (iqentry_lptr[dram0_id[`QBITS]])
|
|
// wbrcd[pcr[5:0]] <= 1'b1;
|
|
end
|
end
|
if (mem2_available && `NUM_MEM > 1 && dramB_v && iqentry_v[ dramB_id[`QBITS] ] && iqentry_load[ dramB_id[`QBITS] ]) begin // if data for stomped instruction, ignore
|
if (mem2_available && `NUM_MEM > 1 && dramB_v && iqentry_v[ dramB_id[`QBITS] ] && iqentry_load[ dramB_id[`QBITS] ]) begin
|
iqentry_res [ dramB_id[`QBITS] ] <= dramB_bus;
|
iqentry_res [ dramB_id[`QBITS] ] <= dramB_bus;
|
iqentry_exc [ dramB_id[`QBITS] ] <= dramB_exc;
|
iqentry_exc [ dramB_id[`QBITS] ] <= dramB_exc;
|
iqentry_done[ dramB_id[`QBITS] ] <= `VAL;
|
iqentry_done[ dramB_id[`QBITS] ] <= `VAL;
|
iqentry_out [ dramB_id[`QBITS] ] <= `INV;
|
iqentry_out [ dramB_id[`QBITS] ] <= `INV;
|
iqentry_cmt[ dramB_id[`QBITS] ] <= `VAL;
|
iqentry_cmt[ dramB_id[`QBITS] ] <= `VAL;
|
iqentry_aq [ dramB_id[`QBITS] ] <= `INV;
|
iqentry_aq [ dramB_id[`QBITS] ] <= `INV;
|
// if (iqentry_lptr[dram1_id[`QBITS]])
|
|
// wbrcd[pcr[5:0]] <= 1'b1;
|
|
end
|
end
|
if (mem3_available && `NUM_MEM > 2 && dramC_v && iqentry_v[ dramC_id[`QBITS] ] && iqentry_load[ dramC_id[`QBITS] ]) begin // if data for stomped instruction, ignore
|
if (mem3_available && `NUM_MEM > 2 && dramC_v && iqentry_v[ dramC_id[`QBITS] ] && iqentry_load[ dramC_id[`QBITS] ]) begin
|
iqentry_res [ dramC_id[`QBITS] ] <= dramC_bus;
|
iqentry_res [ dramC_id[`QBITS] ] <= dramC_bus;
|
iqentry_exc [ dramC_id[`QBITS] ] <= dramC_exc;
|
iqentry_exc [ dramC_id[`QBITS] ] <= dramC_exc;
|
iqentry_done[ dramC_id[`QBITS] ] <= `VAL;
|
iqentry_done[ dramC_id[`QBITS] ] <= `VAL;
|
iqentry_out [ dramC_id[`QBITS] ] <= `INV;
|
iqentry_out [ dramC_id[`QBITS] ] <= `INV;
|
iqentry_cmt[ dramC_id[`QBITS] ] <= `VAL;
|
iqentry_cmt[ dramC_id[`QBITS] ] <= `VAL;
|
| Line 7316... |
Line 7186... |
fcu_instr <= iqentry_instr[n];
|
fcu_instr <= iqentry_instr[n];
|
fcu_insln <= iqentry_insln[n];
|
fcu_insln <= iqentry_insln[n];
|
fcu_pc <= iqentry_pc[n];
|
fcu_pc <= iqentry_pc[n];
|
fcu_nextpc <= iqentry_pc[n] + iqentry_insln[n];
|
fcu_nextpc <= iqentry_pc[n] + iqentry_insln[n];
|
fcu_brdisp <= {{52{iqentry_instr[n][31]}},iqentry_instr[n][31:21],1'b0};
|
fcu_brdisp <= {{52{iqentry_instr[n][31]}},iqentry_instr[n][31:21],1'b0};
|
fcu_call <= IsCall(iqentry_instr[n])|IsJAL(iqentry_instr[n]);
|
fcu_branch <= iqentry_br[n];
|
|
fcu_call <= IsCall(iqentry_instr[n])|iqentry_jal[n];
|
|
fcu_jal <= iqentry_jal[n];
|
|
fcu_ret <= iqentry_ret[n];
|
|
fcu_brk <= iqentry_brk[n];
|
|
fcu_rti <= iqentry_rti[n];
|
fcu_bt <= iqentry_bt[n];
|
fcu_bt <= iqentry_bt[n];
|
fcu_pc <= iqentry_pc[n];
|
fcu_pc <= iqentry_pc[n];
|
fcu_argA <= iqentry_a1_v[n] ? iqentry_a1[n]
|
fcu_argA <= iqentry_a1_v[n] ? iqentry_a1[n]
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a1_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
: (iqentry_a1_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
: alu1_bus;
|
: alu1_bus;
|
`ifdef SUPPORT_SMT
|
`ifdef SUPPORT_SMT
|
fcu_argB <= IsRTI(iqentry_instr[n]) ? epc0[iqentry_thrd[n]]
|
fcu_argB <= iqentry_rti[n] ? epc0[iqentry_thrd[n]]
|
`else
|
`else
|
fcu_argB <= IsRTI(iqentry_instr[n]) ? epc0
|
fcu_argB <= iqentry_rti[n] ? epc0
|
`endif
|
`endif
|
: (iqentry_a2_v[n] ? iqentry_a2[n]
|
: (iqentry_a2_v[n] ? iqentry_a2[n]
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
: (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
: alu1_bus);
|
: alu1_bus);
|
| Line 7342... |
Line 7217... |
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
fcu_argI <= iqentry_a0[n];
|
fcu_argI <= iqentry_a0[n];
|
fcu_thrd <= iqentry_thrd[n];
|
fcu_thrd <= iqentry_thrd[n];
|
fcu_dataready <= `VAL;
|
fcu_dataready <= `VAL;
|
fcu_clearbm <= `FALSE;
|
fcu_clearbm <= `FALSE;
|
fcu_retadr_v <= `INV;
|
|
fcu_ld <= TRUE;
|
fcu_ld <= TRUE;
|
fcu_timeout <= 8'h00;
|
fcu_timeout <= 8'h00;
|
iqentry_out[n] <= `VAL;
|
iqentry_out[n] <= `VAL;
|
fcu_done <= `FALSE;
|
fcu_done <= `FALSE;
|
end
|
end
|
| Line 7512... |
Line 7386... |
end
|
end
|
end
|
end
|
if (last_issue < 8)
|
if (last_issue < 8)
|
iqentry_out[last_issue] <= `VAL;
|
iqentry_out[last_issue] <= `VAL;
|
|
|
// It's better to check a sequence number here because if the code is in a
|
|
// loop that such that the previous iteration of the loop is still in the
|
|
// queue the PC could match when we don;t really want a prefix for that
|
|
// iteration.
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
for (n = 0; n < QENTRIES; n = n + 1)
|
begin
|
begin
|
if (!iqentry_v[n])
|
if (!iqentry_v[n])
|
iqentry_done[n] <= FALSE;
|
iqentry_done[n] <= FALSE;
|
end
|
end
|
| Line 8086... |
Line 7956... |
`endif
|
`endif
|
// cr_o <= IsSWC(dram0_instr);
|
// cr_o <= IsSWC(dram0_instr);
|
end
|
end
|
end
|
end
|
// Check for read misses on the data cache
|
// Check for read misses on the data cache
|
else if (mem1_available && !dram0_unc && dram0==`DRAMSLOT_REQBUS && dram0_load) begin
|
else if (~|wb_v && mem1_available && !dram0_unc && dram0==`DRAMSLOT_REQBUS && dram0_load) begin
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
if (dbg_lmatch0) begin
|
if (dbg_lmatch0) begin
|
dramA_v <= `TRUE;
|
dramA_v <= `TRUE;
|
dramA_id <= dram0_id;
|
dramA_id <= dram0_id;
|
dramA_exc <= `FLT_DBG;
|
dramA_exc <= `FLT_DBG;
|
| Line 8594... |
Line 8464... |
tail1 <= 3'd0;
|
tail1 <= 3'd0;
|
end
|
end
|
// otherwise, it is the last instruction in the queue that has been mispredicted ... do nothing
|
// otherwise, it is the last instruction in the queue that has been mispredicted ... do nothing
|
end
|
end
|
`endif
|
`endif
|
|
|
/*
|
/*
|
if (pebm)
|
if (pebm)
|
seq_num <= seq_num + 5'd3;
|
seq_num <= seq_num + 5'd3;
|
else if (queued2)
|
else if (queued2)
|
seq_num <= seq_num + 5'd2;
|
seq_num <= seq_num + 5'd2;
|
else if (queued1)
|
else if (queued1)
|
seq_num <= seq_num + 5'd1;
|
seq_num <= seq_num + 5'd1;
|
*/
|
*/
|
// #5 rf[0] = 0; rf_v[0] = 1; rf_source[0] = 0;
|
// #5 rf[0] = 0; rf_v[0] = 1; rf_source[0] = 0;
|
|
`ifdef SIM
|
$display("\n\n\n\n\n\n\n\n");
|
$display("\n\n\n\n\n\n\n\n");
|
$display("TIME %0d", $time);
|
$display("TIME %0d", $time);
|
$display("%h #", pc0);
|
$display("%h #", pc0);
|
`ifdef SUPPORT_SMT
|
`ifdef SUPPORT_SMT
|
$display ("Regfile: %d", rgs[0]);
|
$display ("Regfile: %d", rgs[0]);
|
| Line 8651... |
Line 8523... |
`endif
|
`endif
|
// $display("Return address stack:");
|
// $display("Return address stack:");
|
// for (n = 0; n < 16; n = n + 1)
|
// for (n = 0; n < 16; n = n + 1)
|
// $display("%d %h", rasp+n[3:0], ras[rasp+n[3:0]]);
|
// $display("%d %h", rasp+n[3:0], ras[rasp+n[3:0]]);
|
$display("TakeBr:%d #", take_branch);//, backpc);
|
$display("TakeBr:%d #", take_branch);//, backpc);
|
|
$display("Insn%d: %h", 0, insn0);
|
|
if (`WAYS > 1)
|
|
$display("Insn%d: %h", 1, insn1);
|
$display("%c%c A: %d %h %h #",
|
$display("%c%c A: %d %h %h #",
|
45, fetchbuf?45:62, fetchbufA_v, fetchbufA_instr, fetchbufA_pc);
|
45, fetchbuf?45:62, fetchbufA_v, fetchbufA_instr, fetchbufA_pc);
|
$display("%c%c B: %d %h %h #",
|
$display("%c%c B: %d %h %h #",
|
45, fetchbuf?45:62, fetchbufB_v, fetchbufB_instr, fetchbufB_pc);
|
45, fetchbuf?45:62, fetchbufB_v, fetchbufB_instr, fetchbufB_pc);
|
$display("%c%c C: %d %h %h #",
|
$display("%c%c C: %d %h %h #",
|
| Line 8722... |
Line 8597... |
$display("Commit");
|
$display("Commit");
|
$display("0: %c %h %o %d #", commit0_v?"v":" ", commit0_bus, commit0_id, commit0_tgt[4:0]);
|
$display("0: %c %h %o %d #", commit0_v?"v":" ", commit0_bus, commit0_id, commit0_tgt[4:0]);
|
$display("1: %c %h %o %d #", commit1_v?"v":" ", commit1_bus, commit1_id, commit1_tgt[4:0]);
|
$display("1: %c %h %o %d #", commit1_v?"v":" ", commit1_bus, commit1_id, commit1_tgt[4:0]);
|
$display("instructions committed: %d ticks: %d ", I, tick);
|
$display("instructions committed: %d ticks: %d ", I, tick);
|
$display("Write merges: %d", wb_merges);
|
$display("Write merges: %d", wb_merges);
|
|
`endif // SIM
|
|
|
//
|
//
|
// $display("\n\n\n\n\n\n\n\n");
|
// $display("\n\n\n\n\n\n\n\n");
|
// $display("TIME %0d", $time);
|
// $display("TIME %0d", $time);
|
// $display(" pc0=%h", pc0);
|
// $display(" pc0=%h", pc0);
|
| Line 8929... |
Line 8805... |
else if (queued1)
|
else if (queued1)
|
seq_num <= seq_num + 5'd1;
|
seq_num <= seq_num + 5'd1;
|
end
|
end
|
*/
|
*/
|
|
|
|
// Update the write buffer.
|
task wb_update;
|
task wb_update;
|
input [`QBITS] id;
|
input [`QBITS] id;
|
input rmw;
|
input rmw;
|
input [7:0] sel;
|
input [7:0] sel;
|
input [1:0] ol;
|
input [1:0] ol;
|
| Line 9035... |
Line 8912... |
|
|
task setinsn;
|
task setinsn;
|
input [`QBITS] nn;
|
input [`QBITS] nn;
|
input [4:0] id;
|
input [4:0] id;
|
input v;
|
input v;
|
input [127:0] bus;
|
input [143:0] bus;
|
begin
|
begin
|
if (iqentry_iv[nn] == `INV && iqentry_is[nn] == id && iqentry_v[nn] == `VAL && v == `VAL) begin
|
if (iqentry_iv[nn] == `INV && iqentry_is[nn] == id && iqentry_v[nn] == `VAL && v == `VAL) begin
|
iqentry_iv [nn] <= `VAL;
|
iqentry_iv [nn] <= `VAL;
|
// iqentry_Rt [nn] <= bus[`IB_RT];
|
// iqentry_Rt [nn] <= bus[`IB_RT];
|
// iqentry_Rc [nn] <= bus[`IB_RC];
|
// iqentry_Rc [nn] <= bus[`IB_RC];
|
// iqentry_Ra [nn] <= bus[`IB_RA];
|
// iqentry_Ra [nn] <= bus[`IB_RA];
|
iqentry_a0 [nn] <= bus[`IB_CONST];
|
iqentry_a0 [nn] <= bus[`IB_CONST];
|
iqentry_imm [nn] <= bus[`IB_IMM];
|
iqentry_imm [nn] <= bus[`IB_IMM];
|
iqentry_insln[nn] <= bus[`IB_LN];
|
iqentry_insln[nn] <= bus[`IB_LN];
|
|
iqentry_jal [nn] <= bus[`IB_JAL];
|
|
iqentry_ret [nn] <= bus[`IB_RET];
|
|
iqentry_irq [nn] <= bus[`IB_IRQ];
|
|
iqentry_brk [nn] <= bus[`IB_BRK];
|
|
iqentry_rti [nn] <= bus[`IB_RTI];
|
iqentry_bt [nn] <= bus[`IB_BT];
|
iqentry_bt [nn] <= bus[`IB_BT];
|
iqentry_alu [nn] <= bus[`IB_ALU];
|
iqentry_alu [nn] <= bus[`IB_ALU];
|
iqentry_alu0 [nn] <= bus[`IB_ALU0];
|
iqentry_alu0 [nn] <= bus[`IB_ALU0];
|
iqentry_fpu [nn] <= bus[`IB_FPU];
|
iqentry_fpu [nn] <= bus[`IB_FPU];
|
iqentry_fc [nn] <= bus[`IB_FC];
|
iqentry_fc [nn] <= bus[`IB_FC];
|
| Line 9206... |
Line 9088... |
thread = iqentry_thrd[head];
|
thread = iqentry_thrd[head];
|
if (v) begin
|
if (v) begin
|
if (|iqentry_exc[head]) begin
|
if (|iqentry_exc[head]) begin
|
excmiss <= TRUE;
|
excmiss <= TRUE;
|
`ifdef SUPPORT_SMT
|
`ifdef SUPPORT_SMT
|
excmisspc <= {tvec[3'd0][31:8],ol[thread],5'h00};
|
excmisspc <= {tvec[3'd0][31:8],1'b0,ol[thread],5'h00};
|
excthrd <= iqentry_thrd[head];
|
excthrd <= iqentry_thrd[head];
|
badaddr[{thread,3'd0}] <= iqentry_a1[head];
|
badaddr[{thread,3'd0}] <= iqentry_a1[head];
|
epc0[thread] <= iqentry_pc[head]+ 32'd4;
|
epc0[thread] <= iqentry_pc[head]+ 32'd4;
|
epc1[thread] <= epc0[thread];
|
epc1[thread] <= epc0[thread];
|
epc2[thread] <= epc1[thread];
|
epc2[thread] <= epc1[thread];
|
| Line 9227... |
Line 9109... |
cause[{thread,3'd0}] <= {8'd0,iqentry_exc[head]};
|
cause[{thread,3'd0}] <= {8'd0,iqentry_exc[head]};
|
mstatus[thread][5:3] <= 3'd0;
|
mstatus[thread][5:3] <= 3'd0;
|
mstatus[thread][13:6] <= 8'h00;
|
mstatus[thread][13:6] <= 8'h00;
|
mstatus[thread][19:14] <= 6'd0;
|
mstatus[thread][19:14] <= 6'd0;
|
`else
|
`else
|
excmisspc <= {tvec[3'd0][31:8],ol,5'h00};
|
excmisspc <= {tvec[3'd0][31:8],1'b0,ol,5'h00};
|
excthrd <= iqentry_thrd[head];
|
excthrd <= iqentry_thrd[head];
|
badaddr[{thread,3'd0}] <= iqentry_a1[head];
|
badaddr[{thread,3'd0}] <= iqentry_a1[head];
|
epc0 <= iqentry_pc[head]+ 32'd4;
|
epc0 <= iqentry_pc[head]+ 32'd4;
|
epc1 <= epc0;
|
epc1 <= epc0;
|
epc2 <= epc1;
|
epc2 <= epc1;
|
| Line 9264... |
Line 9146... |
// BRK is treated as a nop unless it's a software interrupt or a
|
// BRK is treated as a nop unless it's a software interrupt or a
|
// hardware interrupt at a higher priority than the current priority.
|
// hardware interrupt at a higher priority than the current priority.
|
if ((iqentry_instr[head][23:19] > 5'd0) || iqentry_instr[head][18:16] > im) begin
|
if ((iqentry_instr[head][23:19] > 5'd0) || iqentry_instr[head][18:16] > im) begin
|
excmiss <= TRUE;
|
excmiss <= TRUE;
|
`ifdef SUPPORT_SMT
|
`ifdef SUPPORT_SMT
|
excmisspc <= {tvec[3'd0][31:8],ol[thread],5'h00};
|
excmisspc <= {tvec[3'd0][31:8],1'b0,ol[thread],5'h00};
|
excthrd <= iqentry_thrd[head];
|
excthrd <= iqentry_thrd[head];
|
epc0[thread] <= iqentry_pc[head] + {iqentry_instr[head][23:19],2'b00};
|
epc0[thread] <= iqentry_pc[head] + {iqentry_instr[head][23:19],2'b00};
|
epc1[thread] <= epc0[thread];
|
epc1[thread] <= epc0[thread];
|
epc2[thread] <= epc1[thread];
|
epc2[thread] <= epc1[thread];
|
epc3[thread] <= epc2[thread];
|
epc3[thread] <= epc2[thread];
|
| Line 9293... |
Line 9175... |
mstatus[thread][19:14] <= {3'b0,iqentry_instr[head][18:16]};
|
mstatus[thread][19:14] <= {3'b0,iqentry_instr[head][18:16]};
|
end
|
end
|
else
|
else
|
mstatus[thread][19:14] <= 6'd0;
|
mstatus[thread][19:14] <= 6'd0;
|
`else
|
`else
|
excmisspc <= {tvec[3'd0][31:8],ol,5'h00};
|
excmisspc <= {tvec[3'd0][31:8],1'b0,ol,5'h00};
|
excthrd <= iqentry_thrd[head];
|
excthrd <= iqentry_thrd[head];
|
epc0 <= iqentry_pc[head] + {iqentry_instr[head][23:19],2'b00};
|
epc0 <= iqentry_pc[head] + {iqentry_instr[head][23:19],2'b00};
|
epc1 <= epc0;
|
epc1 <= epc0;
|
epc2 <= epc1;
|
epc2 <= epc1;
|
epc3 <= epc2;
|
epc3 <= epc2;
|
| Line 9374... |
Line 9256... |
epc3[thread] <= epc4[thread];
|
epc3[thread] <= epc4[thread];
|
epc4[thread] <= epc5[thread];
|
epc4[thread] <= epc5[thread];
|
epc5[thread] <= epc6[thread];
|
epc5[thread] <= epc6[thread];
|
epc6[thread] <= epc7[thread];
|
epc6[thread] <= epc7[thread];
|
epc7[thread] <= epc8[thread];
|
epc7[thread] <= epc8[thread];
|
epc8[thread] <= {tvec[0][31:8], ol[thread], 5'h0};
|
epc8[thread] <= {tvec[0][31:8], 1'b0, ol[thread], 5'h0};
|
`else
|
`else
|
excmisspc <= epc0;
|
excmisspc <= epc0;
|
excthrd <= thread;
|
excthrd <= thread;
|
mstatus[3:0] <= im_stack[3:0];
|
mstatus[3:0] <= im_stack[3:0];
|
mstatus[5:4] <= ol_stack[1:0];
|
mstatus[5:4] <= ol_stack[1:0];
|
| Line 9394... |
Line 9276... |
epc3 <= epc4;
|
epc3 <= epc4;
|
epc4 <= epc5;
|
epc4 <= epc5;
|
epc5 <= epc6;
|
epc5 <= epc6;
|
epc6 <= epc7;
|
epc6 <= epc7;
|
epc7 <= epc8;
|
epc7 <= epc8;
|
epc8 <= {tvec[0][31:8], ol, 5'h0};
|
epc8 <= {tvec[0][31:8], 1'b0, ol, 5'h0};
|
`endif
|
`endif
|
sema[0] <= 1'b0;
|
sema[0] <= 1'b0;
|
sema[iqentry_res[head][5:0]] <= 1'b0;
|
sema[iqentry_res[head][5:0]] <= 1'b0;
|
vqe0 <= ve_hold[ 5: 0];
|
vqe0 <= ve_hold[ 5: 0];
|
vqet0 <= ve_hold[21:16];
|
vqet0 <= ve_hold[21:16];
|
| Line 9422... |
Line 9304... |
endcase
|
endcase
|
default: ;
|
default: ;
|
endcase
|
endcase
|
`CSRRW:
|
`CSRRW:
|
begin
|
begin
|
write_csr(iqentry_instr[head][31:16],iqentry_a1[head],thread);
|
write_csr(iqentry_instr[head][31:18],iqentry_a1[head],thread);
|
end
|
end
|
`REX:
|
`REX:
|
`ifdef SUPPORT_SMT
|
`ifdef SUPPORT_SMT
|
// Can only redirect to a lower level
|
// Can only redirect to a lower level
|
if (ol[thread] < iqentry_instr[head][13:11]) begin
|
if (ol[thread] < iqentry_instr[head][13:11]) begin
|
| Line 9451... |
Line 9333... |
default: ;
|
default: ;
|
endcase
|
endcase
|
`FLOAT:
|
`FLOAT:
|
case(iqentry_instr[head][`INSTRUCTION_S2])
|
case(iqentry_instr[head][`INSTRUCTION_S2])
|
`FRM: begin
|
`FRM: begin
|
fp1_rm <= iqentry_res[head][2:0];
|
fp_rm <= iqentry_res[head][2:0];
|
fp2_rm <= iqentry_res[head][2:0];
|
|
end
|
end
|
`FCX:
|
`FCX:
|
begin
|
begin
|
fp1_sx <= fp1_sx & ~iqentry_res[head][5];
|
fp_sx <= fp_sx & ~iqentry_res[head][5];
|
fp1_inex <= fp1_inex & ~iqentry_res[head][4];
|
fp_inex <= fp_inex & ~iqentry_res[head][4];
|
fp1_dbzx <= fp1_dbzx & ~(iqentry_res[head][3]|iqentry_res[head][0]);
|
fp_dbzx <= fp_dbzx & ~(iqentry_res[head][3]|iqentry_res[head][0]);
|
fp1_underx <= fp1_underx & ~iqentry_res[head][2];
|
fp_underx <= fp_underx & ~iqentry_res[head][2];
|
fp1_overx <= fp1_overx & ~iqentry_res[head][1];
|
fp_overx <= fp_overx & ~iqentry_res[head][1];
|
fp1_giopx <= fp1_giopx & ~iqentry_res[head][0];
|
fp_giopx <= fp_giopx & ~iqentry_res[head][0];
|
fp1_infdivx <= fp1_infdivx & ~iqentry_res[head][0];
|
fp_infdivx <= fp_infdivx & ~iqentry_res[head][0];
|
fp1_zerozerox <= fp1_zerozerox & ~iqentry_res[head][0];
|
fp_zerozerox <= fp_zerozerox & ~iqentry_res[head][0];
|
fp1_subinfx <= fp1_subinfx & ~iqentry_res[head][0];
|
fp_subinfx <= fp_subinfx & ~iqentry_res[head][0];
|
fp1_infzerox <= fp1_infzerox & ~iqentry_res[head][0];
|
fp_infzerox <= fp_infzerox & ~iqentry_res[head][0];
|
fp1_NaNCmpx <= fp1_NaNCmpx & ~iqentry_res[head][0];
|
fp_NaNCmpx <= fp_NaNCmpx & ~iqentry_res[head][0];
|
fp1_swtx <= 1'b0;
|
fp_swtx <= 1'b0;
|
end
|
end
|
`FDX:
|
`FDX:
|
begin
|
begin
|
fp1_inexe <= fp1_inexe & ~iqentry_res[head][4];
|
fp_inexe <= fp_inexe & ~iqentry_res[head][4];
|
fp1_dbzxe <= fp1_dbzxe & ~iqentry_res[head][3];
|
fp_dbzxe <= fp_dbzxe & ~iqentry_res[head][3];
|
fp1_underxe <= fp1_underxe & ~iqentry_res[head][2];
|
fp_underxe <= fp_underxe & ~iqentry_res[head][2];
|
fp1_overxe <= fp1_overxe & ~iqentry_res[head][1];
|
fp_overxe <= fp_overxe & ~iqentry_res[head][1];
|
fp1_invopxe <= fp1_invopxe & ~iqentry_res[head][0];
|
fp_invopxe <= fp_invopxe & ~iqentry_res[head][0];
|
end
|
end
|
`FEX:
|
`FEX:
|
begin
|
begin
|
fp1_inexe <= fp1_inexe | iqentry_res[head][4];
|
fp_inexe <= fp_inexe | iqentry_res[head][4];
|
fp1_dbzxe <= fp1_dbzxe | iqentry_res[head][3];
|
fp_dbzxe <= fp_dbzxe | iqentry_res[head][3];
|
fp1_underxe <= fp1_underxe | iqentry_res[head][2];
|
fp_underxe <= fp_underxe | iqentry_res[head][2];
|
fp1_overxe <= fp1_overxe | iqentry_res[head][1];
|
fp_overxe <= fp_overxe | iqentry_res[head][1];
|
fp1_invopxe <= fp1_invopxe | iqentry_res[head][0];
|
fp_invopxe <= fp_invopxe | iqentry_res[head][0];
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
// 31 to 29 is rounding mode
|
// 31 to 29 is rounding mode
|
// 28 to 24 are exception enables
|
// 28 to 24 are exception enables
|
// 23 is nsfp
|
// 23 is nsfp
|
// 22 is a fractie
|
// 22 is a fractie
|
fp1_fractie <= iqentry_a0[head][22];
|
fp_fractie <= iqentry_a0[head][22];
|
fp1_raz <= iqentry_a0[head][21];
|
fp_raz <= iqentry_a0[head][21];
|
// 20 is a 0
|
// 20 is a 0
|
fp1_neg <= iqentry_a0[head][19];
|
fp_neg <= iqentry_a0[head][19];
|
fp1_pos <= iqentry_a0[head][18];
|
fp_pos <= iqentry_a0[head][18];
|
fp1_zero <= iqentry_a0[head][17];
|
fp_zero <= iqentry_a0[head][17];
|
fp1_inf <= iqentry_a0[head][16];
|
fp_inf <= iqentry_a0[head][16];
|
// 15 swtx
|
// 15 swtx
|
// 14
|
// 14
|
fp1_inex <= fp1_inex | (fp1_inexe & iqentry_a0[head][14]);
|
fp_inex <= fp_inex | (fp_inexe & iqentry_a0[head][14]);
|
fp1_dbzx <= fp1_dbzx | (fp1_dbzxe & iqentry_a0[head][13]);
|
fp_dbzx <= fp_dbzx | (fp_dbzxe & iqentry_a0[head][13]);
|
fp1_underx <= fp1_underx | (fp1_underxe & iqentry_a0[head][12]);
|
fp_underx <= fp_underx | (fp_underxe & iqentry_a0[head][12]);
|
fp1_overx <= fp1_overx | (fp1_overxe & iqentry_a0[head][11]);
|
fp_overx <= fp_overx | (fp_overxe & iqentry_a0[head][11]);
|
//fp_giopx <= fp_giopx | (fp_giopxe & iqentry_res2[head][10]);
|
//fp_giopx <= fp_giopx | (fp_giopxe & iqentry_res2[head][10]);
|
//fp_invopx <= fp_invopx | (fp_invopxe & iqentry_res2[head][24]);
|
//fp_invopx <= fp_invopx | (fp_invopxe & iqentry_res2[head][24]);
|
//
|
//
|
fp1_cvtx <= fp1_cvtx | (fp1_giopxe & iqentry_a0[head][7]);
|
fp_cvtx <= fp_cvtx | (fp_giopxe & iqentry_a0[head][7]);
|
fp1_sqrtx <= fp1_sqrtx | (fp1_giopxe & iqentry_a0[head][6]);
|
fp_sqrtx <= fp_sqrtx | (fp_giopxe & iqentry_a0[head][6]);
|
fp1_NaNCmpx <= fp1_NaNCmpx | (fp1_giopxe & iqentry_a0[head][5]);
|
fp_NaNCmpx <= fp_NaNCmpx | (fp_giopxe & iqentry_a0[head][5]);
|
fp1_infzerox <= fp1_infzerox | (fp1_giopxe & iqentry_a0[head][4]);
|
fp_infzerox <= fp_infzerox | (fp_giopxe & iqentry_a0[head][4]);
|
fp1_zerozerox <= fp1_zerozerox | (fp1_giopxe & iqentry_a0[head][3]);
|
fp_zerozerox <= fp_zerozerox | (fp_giopxe & iqentry_a0[head][3]);
|
fp1_infdivx <= fp1_infdivx | (fp1_giopxe & iqentry_a0[head][2]);
|
fp_infdivx <= fp_infdivx | (fp_giopxe & iqentry_a0[head][2]);
|
fp1_subinfx <= fp1_subinfx | (fp1_giopxe & iqentry_a0[head][1]);
|
fp_subinfx <= fp_subinfx | (fp_giopxe & iqentry_a0[head][1]);
|
fp1_snanx <= fp1_snanx | (fp1_giopxe & iqentry_a0[head][0]);
|
fp_snanx <= fp_snanx | (fp_giopxe & iqentry_a0[head][0]);
|
|
|
end
|
end
|
endcase
|
endcase
|
default: ;
|
default: ;
|
endcase
|
endcase
|
| Line 9529... |
Line 9410... |
end
|
end
|
endtask
|
endtask
|
|
|
// CSR access tasks
|
// CSR access tasks
|
task read_csr;
|
task read_csr;
|
input [13:0] csrno;
|
input [11:0] csrno;
|
output [63:0] dat;
|
output [63:0] dat;
|
input thread;
|
input thread;
|
begin
|
begin
|
`ifdef SUPPORT_SMT
|
`ifdef SUPPORT_SMT
|
if (csrno[11:10] >= ol[thread])
|
if (csrno[11:10] >= ol[thread])
|
| Line 9550... |
Line 9431... |
`CSR_WBRCD: dat <= wbrcd;
|
`CSR_WBRCD: dat <= wbrcd;
|
`CSR_SEMA: dat <= sema;
|
`CSR_SEMA: dat <= sema;
|
`CSR_SBL: dat <= sbl;
|
`CSR_SBL: dat <= sbl;
|
`CSR_SBU: dat <= sbu;
|
`CSR_SBU: dat <= sbu;
|
`CSR_TCB: dat <= tcb;
|
`CSR_TCB: dat <= tcb;
|
`CSR_FSTAT: dat <= {fp1_rgs,fp1_status};
|
`CSR_FSTAT: dat <= {fp_rgs,fp_status};
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
`CSR_DBAD0: dat <= dbg_adr0;
|
`CSR_DBAD0: dat <= dbg_adr0;
|
`CSR_DBAD1: dat <= dbg_adr1;
|
`CSR_DBAD1: dat <= dbg_adr1;
|
`CSR_DBAD2: dat <= dbg_adr2;
|
`CSR_DBAD2: dat <= dbg_adr2;
|
`CSR_DBAD3: dat <= dbg_adr3;
|
`CSR_DBAD3: dat <= dbg_adr3;
|
| Line 9659... |
Line 9540... |
`CSR_WBRCD: wbrcd <= dat;
|
`CSR_WBRCD: wbrcd <= dat;
|
`CSR_SEMA: sema <= dat;
|
`CSR_SEMA: sema <= dat;
|
`CSR_SBL: sbl <= dat[31:0];
|
`CSR_SBL: sbl <= dat[31:0];
|
`CSR_SBU: sbu <= dat[31:0];
|
`CSR_SBU: sbu <= dat[31:0];
|
`CSR_TCB: tcb <= dat;
|
`CSR_TCB: tcb <= dat;
|
`CSR_FSTAT: fpu1_csr[37:32] <= dat[37:32];
|
`CSR_FSTAT: fpu_csr[37:32] <= dat[37:32];
|
`CSR_BADADR: badaddr[{thread,csrno[13:11]}] <= dat;
|
`CSR_BADADR: badaddr[{thread,csrno[13:11]}] <= dat;
|
`CSR_CAUSE: cause[{thread,csrno[13:11]}] <= dat[15:0];
|
`CSR_CAUSE: cause[{thread,csrno[13:11]}] <= dat[15:0];
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
`CSR_DBAD0: dbg_adr0 <= dat[AMSB:0];
|
`CSR_DBAD0: dbg_adr0 <= dat[AMSB:0];
|
`CSR_DBAD1: dbg_adr1 <= dat[AMSB:0];
|
`CSR_DBAD1: dbg_adr1 <= dat[AMSB:0];
|
| Line 9754... |
Line 9635... |
default: ;
|
default: ;
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
/*
|
|
task aluissue;
|
|
input alu_idle;
|
|
input [QENTRIES-1:0] iq_alu0;
|
|
input [1:0] slot;
|
|
begin
|
|
if (alu_idle) begin
|
|
if (could_issue[head0] && iqentry_alu[head0]
|
|
&& !iq_alu0[head0] // alu0only
|
|
&& !iqentry_issue[head0]) begin
|
|
iqentry_issue[head0] = `TRUE;
|
|
iqentry_islot[head0] = slot;
|
|
end
|
|
else if (could_issue[head1] && !iqentry_issue[head1] && iqentry_alu[head1]
|
|
&& !iq_alu0[head1])
|
|
begin
|
|
iqentry_issue[head1] = `TRUE;
|
|
iqentry_islot[head1] = slot;
|
|
end
|
|
else if (could_issue[head2] && !iqentry_issue[head2] && iqentry_alu[head2]
|
|
&& !iq_alu0[head2]
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
|
)
|
|
begin
|
|
iqentry_issue[head2] = `TRUE;
|
|
iqentry_islot[head2] = slot;
|
|
end
|
|
else if (could_issue[head3] && !iqentry_issue[head3] && iqentry_alu[head3]
|
|
&& !iq_alu0[head3]
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
) begin
|
|
iqentry_issue[head3] = `TRUE;
|
|
iqentry_islot[head3] = slot;
|
|
end
|
|
else if (could_issue[head4] && !iqentry_issue[head4] && iqentry_alu[head4]
|
|
&& !iq_alu0[head4]
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2]))
|
|
)
|
|
) begin
|
|
iqentry_issue[head4] = `TRUE;
|
|
iqentry_islot[head4] = slot;
|
|
end
|
|
else if (could_issue[head5] && !iqentry_issue[head5] && iqentry_alu[head5]
|
|
&& !iq_alu0[head5]
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2]))
|
|
)
|
|
&& (!(iqentry_v[head4] && iqentry_sync[head4]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3]))
|
|
)
|
|
) begin
|
|
iqentry_issue[head5] = `TRUE;
|
|
iqentry_islot[head5] = slot;
|
|
end
|
|
else if (could_issue[head6] && !iqentry_issue[head6] && iqentry_alu[head6]
|
|
&& !iq_alu0[head6]
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2]))
|
|
)
|
|
&& (!(iqentry_v[head4] && iqentry_sync[head4]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3]))
|
|
)
|
|
&& (!(iqentry_v[head5] && iqentry_sync[head5]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4]))
|
|
)
|
|
) begin
|
|
iqentry_issue[head6] = `TRUE;
|
|
iqentry_islot[head6] = slot;
|
|
end
|
|
else if (could_issue[head7] && !iqentry_issue[head7] && iqentry_alu[head7]
|
|
&& !iq_alu0[head7]
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2]))
|
|
)
|
|
&& (!(iqentry_v[head4] && iqentry_sync[head4]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3]))
|
|
)
|
|
&& (!(iqentry_v[head5] && iqentry_sync[head5]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4]))
|
|
)
|
|
&& (!(iqentry_v[head6] && iqentry_sync[head6]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4])
|
|
&& (!iqentry_v[head5]))
|
|
)
|
|
) begin
|
|
iqentry_issue[head7] = `TRUE;
|
|
iqentry_islot[head7] = slot;
|
|
end
|
|
end
|
|
end
|
|
endtask
|
|
|
|
task fpuissue;
|
|
input fp_idle;
|
|
input [1:0] slot;
|
|
begin
|
|
if (fp_idle) begin
|
|
if (could_issue[head0] && iqentry_fpu[head0]) begin
|
|
iqentry_fpu_issue[head0] = `TRUE;
|
|
iqentry_fpu_islot[head0] = slot;
|
|
end
|
|
else if (could_issue[head1] && iqentry_fpu[head1])
|
|
begin
|
|
iqentry_fpu_issue[head1] = `TRUE;
|
|
iqentry_fpu_islot[head1] = slot;
|
|
end
|
|
else if (could_issue[head2] && iqentry_fpu[head2]
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
|
) begin
|
|
iqentry_fpu_issue[head2] = `TRUE;
|
|
iqentry_fpu_islot[head2] = slot;
|
|
end
|
|
else if (could_issue[head3] && iqentry_fpu[head3]
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
) begin
|
|
iqentry_fpu_issue[head3] = `TRUE;
|
|
iqentry_fpu_islot[head3] = slot;
|
|
end
|
|
else if (could_issue[head4] && iqentry_fpu[head4]
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_v[head3] && (iqentry_sync[head3] || iqentry_fsync[head3])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2]))
|
|
)
|
|
) begin
|
|
iqentry_fpu_issue[head4] = `TRUE;
|
|
iqentry_fpu_islot[head4] = slot;
|
|
end
|
|
else if (could_issue[head5] && iqentry_fpu[head5]
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_v[head3] && (iqentry_sync[head3] || iqentry_fsync[head3])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2]))
|
|
)
|
|
&& (!(iqentry_v[head4] && (iqentry_sync[head4] || iqentry_fsync[head4])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3]))
|
|
)
|
|
) begin
|
|
iqentry_fpu_issue[head5] = `TRUE;
|
|
iqentry_fpu_islot[head5] = slot;
|
|
end
|
|
else if (could_issue[head6] && iqentry_fpu[head6]
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_v[head3] && (iqentry_sync[head3] || iqentry_fsync[head3])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2]))
|
|
)
|
|
&& (!(iqentry_v[head4] && (iqentry_sync[head4] || iqentry_fsync[head4])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3]))
|
|
)
|
|
&& (!(iqentry_v[head5] && (iqentry_sync[head5] || iqentry_fsync[head5])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4]))
|
|
)
|
|
) begin
|
|
iqentry_fpu_issue[head6] = `TRUE;
|
|
iqentry_fpu_islot[head6] = slot;
|
|
end
|
|
else if (could_issue[head7] && iqentry_fpu[head7]
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_v[head3] && (iqentry_sync[head3] || iqentry_fsync[head3])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2]))
|
|
)
|
|
&& (!(iqentry_v[head4] && (iqentry_sync[head4] || iqentry_fsync[head4])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3]))
|
|
)
|
|
&& (!(iqentry_v[head5] && (iqentry_sync[head5] || iqentry_fsync[head5])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4]))
|
|
)
|
|
&& (!(iqentry_v[head6] && (iqentry_sync[head6] || iqentry_fsync[head6])) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4])
|
|
&& (!iqentry_v[head5]))
|
|
)
|
|
)
|
|
begin
|
|
iqentry_fpu_issue[head7] = `TRUE;
|
|
iqentry_fpu_islot[head7] = slot;
|
|
end
|
|
end
|
|
end
|
|
endtask
|
|
*/
|
|
endmodule
|
endmodule
|
|
|
|
|
module decoder5 (num, out);
|
module decoder5 (num, out);
|
input [4:0] num;
|
input [4:0] num;
|
