| Line 97... |
Line 97... |
parameter ABW = 32;
|
parameter ABW = 32;
|
parameter AMSB = ABW-1;
|
parameter AMSB = ABW-1;
|
parameter NTHREAD = 1;
|
parameter NTHREAD = 1;
|
reg [3:0] i;
|
reg [3:0] i;
|
integer n;
|
integer n;
|
integer j;
|
integer j, k;
|
genvar g;
|
genvar g;
|
parameter TRUE = 1'b1;
|
parameter TRUE = 1'b1;
|
parameter FALSE = 1'b0;
|
parameter FALSE = 1'b0;
|
// Memory access sizes
|
// Memory access sizes
|
parameter byt = 3'd0;
|
parameter byt = 3'd0;
|
| Line 165... |
Line 165... |
reg [63:0] ptrmask [0:NTHREAD];
|
reg [63:0] ptrmask [0:NTHREAD];
|
reg [63:0] ptrkey = " OBJECT";
|
reg [63:0] ptrkey = " OBJECT";
|
reg [63:0] wbrcd;
|
reg [63:0] wbrcd;
|
|
|
reg [PREGS-1:0] rf_v;
|
reg [PREGS-1:0] rf_v;
|
reg [4:0] rf_source[0:AREGS-1];
|
reg [5:0] rf_source[0:AREGS-1];
|
initial begin
|
initial begin
|
for (n = 0; n < AREGS; n = n + 1)
|
for (n = 0; n < AREGS; n = n + 1)
|
rf_source[n] = 5'd0;
|
rf_source[n] = 6'd0;
|
end
|
end
|
wire [`ABITS] pc0;
|
wire [`ABITS] pc0;
|
wire [`ABITS] pc1;
|
wire [`ABITS] pc1;
|
wire [`ABITS] pc2;
|
wire [`ABITS] pc2;
|
|
|
| Line 195... |
Line 195... |
// CSR's
|
// CSR's
|
reg [63:0] cr0;
|
reg [63:0] cr0;
|
wire snr = cr0[17]; // sequence number reset
|
wire snr = cr0[17]; // sequence number reset
|
wire dce = cr0[30]; // data cache enable
|
wire dce = cr0[30]; // data cache enable
|
wire bpe = cr0[32]; // branch predictor enable
|
wire bpe = cr0[32]; // branch predictor enable
|
|
wire wbm = cr0[34];
|
wire ctgtxe = cr0[33];
|
wire ctgtxe = cr0[33];
|
reg [63:0] pmr;
|
reg [63:0] pmr;
|
wire id1_available = pmr[0];
|
wire id1_available = pmr[0];
|
wire id2_available = pmr[1];
|
wire id2_available = pmr[1];
|
wire id3_available = pmr[2];
|
wire id3_available = pmr[2];
|
| Line 384... |
Line 385... |
reg [128:0] message [0:15]; // indexed by panic
|
reg [128:0] message [0:15]; // indexed by panic
|
|
|
wire int_commit;
|
wire int_commit;
|
reg StatusHWI;
|
reg StatusHWI;
|
reg [47:0] insn0, insn1, insn2;
|
reg [47:0] insn0, insn1, insn2;
|
wire [47:0] insn0a, insn1a, insn1b, insn2a, insn2b;
|
wire [47:0] insn0a, insn1b, insn2b;
|
|
reg [47:0] insn1a, insn2a;
|
reg tgtq;
|
reg tgtq;
|
// Only need enough bits in the seqnence number to cover the instructions in
|
// Only need enough bits in the seqnence number to cover the instructions in
|
// the queue plus an extra count for skipping on branch misses. In this case
|
// the queue plus an extra count for skipping on branch misses. In this case
|
// that would be four bits minimum (count 0 to 8).
|
// that would be four bits minimum (count 0 to 8).
|
reg [31:0] seq_num;
|
reg [31:0] seq_num;
|
| Line 400... |
Line 402... |
reg queued1;
|
reg queued1;
|
reg queued2;
|
reg queued2;
|
reg queuedNop;
|
reg queuedNop;
|
|
|
reg [47:0] codebuf[0:63];
|
reg [47:0] codebuf[0:63];
|
reg [7:0] setpred;
|
reg [QENTRIES-1:0] setpred;
|
|
|
// instruction queue (ROB)
|
// instruction queue (ROB)
|
reg [31:0] iqentry_sn [0:QENTRIES-1]; // instruction sequence number
|
reg [31:0] iqentry_sn [0:QENTRIES-1]; // instruction sequence number
|
reg [QENTRIES-1:0] iqentry_v; // entry valid? -- this should be the first bit
|
reg [QENTRIES-1:0] iqentry_v; // entry valid? -- this should be the first bit
|
reg [QENTRIES-1:0] iqentry_iv; // instruction is valid
|
reg [QENTRIES-1:0] iqentry_iv; // instruction is valid
|
| Line 413... |
Line 415... |
reg [QENTRIES-1:0] iqentry_done; // instruction result valid
|
reg [QENTRIES-1:0] iqentry_done; // instruction result valid
|
reg [QENTRIES-1:0] iqentry_cmt;
|
reg [QENTRIES-1:0] iqentry_cmt;
|
reg [QENTRIES-1:0] iqentry_thrd; // which thread the instruction is in
|
reg [QENTRIES-1:0] iqentry_thrd; // which thread the instruction is in
|
reg [QENTRIES-1:0] iqentry_pt; // predict taken
|
reg [QENTRIES-1:0] iqentry_pt; // predict taken
|
reg [QENTRIES-1:0] iqentry_bt; // update branch target buffer
|
reg [QENTRIES-1:0] iqentry_bt; // update branch target buffer
|
|
reg [QENTRIES-1:0] iqentry_takb; // take branch record
|
reg [QENTRIES-1:0] iqentry_jal;
|
reg [QENTRIES-1:0] iqentry_jal;
|
reg [QENTRIES-1:0] iqentry_agen; // address-generate ... signifies that address is ready (only for LW/SW)
|
reg [QENTRIES-1:0] iqentry_agen; // address-generate ... signifies that address is ready (only for LW/SW)
|
reg [1:0] iqentry_state [0:QENTRIES-1];
|
reg [1:0] iqentry_state [0:QENTRIES-1];
|
reg [QENTRIES-1:0] iqentry_alu = 8'h00; // alu type instruction
|
reg [QENTRIES-1:0] iqentry_alu = 8'h00; // alu type instruction
|
reg [QENTRIES-1:0] iqentry_alu0; // only valid on alu #0
|
reg [QENTRIES-1:0] iqentry_alu0; // only valid on alu #0
|
| Line 509... |
Line 512... |
wire [PREGS-1:1] iqentry_3_livetarget;
|
wire [PREGS-1:1] iqentry_3_livetarget;
|
wire [PREGS-1:1] iqentry_4_livetarget;
|
wire [PREGS-1:1] iqentry_4_livetarget;
|
wire [PREGS-1:1] iqentry_5_livetarget;
|
wire [PREGS-1:1] iqentry_5_livetarget;
|
wire [PREGS-1:1] iqentry_6_livetarget;
|
wire [PREGS-1:1] iqentry_6_livetarget;
|
wire [PREGS-1:1] iqentry_7_livetarget;
|
wire [PREGS-1:1] iqentry_7_livetarget;
|
|
wire [PREGS-1:1] iqentry_8_livetarget;
|
|
wire [PREGS-1:1] iqentry_9_livetarget;
|
|
wire [PREGS-1:1] iqentry_livetarget [0:QENTRIES-1];
|
|
assign iqentry_livetarget[0] = iqentry_0_livetarget;
|
|
assign iqentry_livetarget[1] = iqentry_1_livetarget;
|
|
assign iqentry_livetarget[2] = iqentry_2_livetarget;
|
|
assign iqentry_livetarget[3] = iqentry_3_livetarget;
|
|
assign iqentry_livetarget[4] = iqentry_4_livetarget;
|
|
assign iqentry_livetarget[5] = iqentry_5_livetarget;
|
|
assign iqentry_livetarget[6] = iqentry_6_livetarget;
|
|
assign iqentry_livetarget[7] = iqentry_7_livetarget;
|
|
assign iqentry_livetarget[8] = iqentry_8_livetarget;
|
|
assign iqentry_livetarget[9] = iqentry_9_livetarget;
|
wire [PREGS-1:1] iqentry_0_latestID;
|
wire [PREGS-1:1] iqentry_0_latestID;
|
wire [PREGS-1:1] iqentry_1_latestID;
|
wire [PREGS-1:1] iqentry_1_latestID;
|
wire [PREGS-1:1] iqentry_2_latestID;
|
wire [PREGS-1:1] iqentry_2_latestID;
|
wire [PREGS-1:1] iqentry_3_latestID;
|
wire [PREGS-1:1] iqentry_3_latestID;
|
wire [PREGS-1:1] iqentry_4_latestID;
|
wire [PREGS-1:1] iqentry_4_latestID;
|
wire [PREGS-1:1] iqentry_5_latestID;
|
wire [PREGS-1:1] iqentry_5_latestID;
|
wire [PREGS-1:1] iqentry_6_latestID;
|
wire [PREGS-1:1] iqentry_6_latestID;
|
wire [PREGS-1:1] iqentry_7_latestID;
|
wire [PREGS-1:1] iqentry_7_latestID;
|
|
wire [PREGS-1:1] iqentry_8_latestID;
|
|
wire [PREGS-1:1] iqentry_9_latestID;
|
wire [PREGS-1:1] iqentry_0_cumulative;
|
wire [PREGS-1:1] iqentry_0_cumulative;
|
wire [PREGS-1:1] iqentry_1_cumulative;
|
wire [PREGS-1:1] iqentry_1_cumulative;
|
wire [PREGS-1:1] iqentry_2_cumulative;
|
wire [PREGS-1:1] iqentry_2_cumulative;
|
wire [PREGS-1:1] iqentry_3_cumulative;
|
wire [PREGS-1:1] iqentry_3_cumulative;
|
wire [PREGS-1:1] iqentry_4_cumulative;
|
wire [PREGS-1:1] iqentry_4_cumulative;
|
wire [PREGS-1:1] iqentry_5_cumulative;
|
wire [PREGS-1:1] iqentry_5_cumulative;
|
wire [PREGS-1:1] iqentry_6_cumulative;
|
wire [PREGS-1:1] iqentry_6_cumulative;
|
wire [PREGS-1:1] iqentry_7_cumulative;
|
wire [PREGS-1:1] iqentry_7_cumulative;
|
|
wire [PREGS-1:1] iqentry_8_cumulative;
|
|
wire [PREGS-1:1] iqentry_9_cumulative;
|
|
reg [PREGS-1:1] iqentry_cumulative [0:QENTRIES-1];
|
wire [PREGS-1:1] iq0_out;
|
wire [PREGS-1:1] iq0_out;
|
wire [PREGS-1:1] iq1_out;
|
wire [PREGS-1:1] iq1_out;
|
wire [PREGS-1:1] iq2_out;
|
wire [PREGS-1:1] iq2_out;
|
wire [PREGS-1:1] iq3_out;
|
wire [PREGS-1:1] iq3_out;
|
wire [PREGS-1:1] iq4_out;
|
wire [PREGS-1:1] iq4_out;
|
wire [PREGS-1:1] iq5_out;
|
wire [PREGS-1:1] iq5_out;
|
wire [PREGS-1:1] iq6_out;
|
wire [PREGS-1:1] iq6_out;
|
wire [PREGS-1:1] iq7_out;
|
wire [PREGS-1:1] iq7_out;
|
|
wire [PREGS-1:1] iq8_out;
|
|
wire [PREGS-1:1] iq9_out;
|
|
|
reg [`QBITS] tail0;
|
reg [`QBITS] tail0;
|
reg [`QBITS] tail1;
|
reg [`QBITS] tail1;
|
reg [`QBITS] head0;
|
reg [`QBITS] head0;
|
reg [`QBITS] head1;
|
reg [`QBITS] head1;
|
| Line 544... |
Line 567... |
reg [`QBITS] head3; // used only to determine memory-access ordering
|
reg [`QBITS] head3; // used only to determine memory-access ordering
|
reg [`QBITS] head4; // used only to determine memory-access ordering
|
reg [`QBITS] head4; // used only to determine memory-access ordering
|
reg [`QBITS] head5; // used only to determine memory-access ordering
|
reg [`QBITS] head5; // used only to determine memory-access ordering
|
reg [`QBITS] head6; // used only to determine memory-access ordering
|
reg [`QBITS] head6; // used only to determine memory-access ordering
|
reg [`QBITS] head7; // used only to determine memory-access ordering
|
reg [`QBITS] head7; // used only to determine memory-access ordering
|
|
reg [`QBITS] head8;
|
|
reg [`QBITS] head9;
|
|
|
wire take_branch0;
|
wire take_branch0;
|
wire take_branch1;
|
wire take_branch1;
|
|
|
reg [3:0] nop_fetchbuf;
|
reg [3:0] nop_fetchbuf;
|
| Line 665... |
Line 690... |
wire [`XBITS] alu1_exc;
|
wire [`XBITS] alu1_exc;
|
wire alu1_v;
|
wire alu1_v;
|
wire alu1_branchmiss;
|
wire alu1_branchmiss;
|
wire [`ABITS] alu1_misspc;
|
wire [`ABITS] alu1_misspc;
|
|
|
|
wire [`XBITS] fpu_exc;
|
reg fpu1_ld;
|
reg fpu1_ld;
|
reg fpu1_dataready = 1'b1;
|
reg fpu1_dataready = 1'b1;
|
wire fpu1_done = 1'b1;
|
wire fpu1_done = 1'b1;
|
wire fpu1_idle;
|
wire fpu1_idle;
|
reg [3:0] fpu1_sourceid;
|
reg [3:0] fpu1_sourceid;
|
| Line 750... |
Line 776... |
reg [`WB_DEPTH-1:0] wb_rmw;
|
reg [`WB_DEPTH-1:0] wb_rmw;
|
reg [QENTRIES-1:0] wb_id [0:`WB_DEPTH-1];
|
reg [QENTRIES-1:0] wb_id [0:`WB_DEPTH-1];
|
reg [QENTRIES-1:0] wbo_id;
|
reg [QENTRIES-1:0] wbo_id;
|
reg [7:0] wb_sel [0:`WB_DEPTH-1];
|
reg [7:0] wb_sel [0:`WB_DEPTH-1];
|
reg wb_en;
|
reg wb_en;
|
|
reg wb_shift;
|
|
|
reg branchmiss = 1'b0;
|
reg branchmiss = 1'b0;
|
reg branchmiss_thrd = 1'b0;
|
reg branchmiss_thrd = 1'b0;
|
reg [`ABITS] misspc;
|
reg [`ABITS] misspc;
|
reg [`QBITS] missid;
|
reg [`QBITS] missid;
|
| Line 937... |
Line 964... |
endfunction
|
endfunction
|
|
|
wire [`ABITS] pc0plus6 = pc0 + 32'd6;
|
wire [`ABITS] pc0plus6 = pc0 + 32'd6;
|
wire [`ABITS] pc0plus12 = pc0 + 32'd12;
|
wire [`ABITS] pc0plus12 = pc0 + 32'd12;
|
|
|
`ifdef SUPPORT_SMT
|
|
generate begin : gInsnVar
|
|
if (`WAYS > 1) begin
|
|
assign insn1a = insn1b;
|
|
end
|
|
if (`WAYS > 2) begin
|
|
assign insn2a = insn2b;
|
|
end
|
|
end
|
|
endgenerate
|
|
`else
|
|
generate begin : gInsnVar
|
generate begin : gInsnVar
|
if (`WAYS > 1) begin
|
if (`WAYS > 1) begin
|
assign insn1a = {insn1b,insn0a} >> {fnInsLength(insn0a),3'b0};
|
always @*
|
|
if (thread_en)
|
|
insn1a <= insn1b;
|
|
else
|
|
insn1a = {insn1b,insn0a} >> {fnInsLength(insn0a),3'b0};
|
end
|
end
|
if (`WAYS > 2) begin
|
if (`WAYS > 2) begin
|
assign insn2a = {insn2b,insn1b,insn0a} >> {fnInsLength(insn0a) + fnInsLength(insn1a),3'b0};
|
always @*
|
|
if (thread_en)
|
|
insn2a <= insn2b;
|
|
else
|
|
insn2a = {insn2b,insn1b,insn0a} >> {fnInsLength(insn0a) + fnInsLength(insn1a),3'b0};
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
`endif
|
|
|
|
FT64_L1_icache uic0
|
FT64_L1_icache uic0
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.clk(clk),
|
.clk(clk),
|
| Line 983... |
Line 1006... |
.rst(rst),
|
.rst(rst),
|
.clk(clk),
|
.clk(clk),
|
.nxt(icnxt),
|
.nxt(icnxt),
|
.wr(L1_wr1),
|
.wr(L1_wr1),
|
.en(L1_en),
|
.en(L1_en),
|
`ifdef SUPPORT_SMT
|
.adr(icstate==IDLE||icstate==IC8 ? (thread_en ? {pcr[5:0],pc1}: {pcr[5:0],pc0plus6} ): L1_adr),
|
.adr(icstate==IDLE||icstate==IC8 ? {pcr[5:0],pc1} : L1_adr),
|
|
`else
|
|
.adr(icstate==IDLE||icstate==IC8 ? {pcr[5:0],pc0plus6} : L1_adr),
|
|
`endif
|
|
.wadr(L1_adr),
|
.wadr(L1_adr),
|
.i(L2_rdat),
|
.i(L2_rdat),
|
.o(insn1b),
|
.o(insn1b),
|
.hit(ihit1),
|
.hit(ihit1),
|
.invall(invic),
|
.invall(invic),
|
| Line 1007... |
Line 1026... |
.rst(rst),
|
.rst(rst),
|
.clk(clk),
|
.clk(clk),
|
.nxt(icnxt),
|
.nxt(icnxt),
|
.wr(L1_wr2),
|
.wr(L1_wr2),
|
.en(L1_en),
|
.en(L1_en),
|
`ifdef SUPPORT_SMT
|
.adr(icstate==IDLE||icstate==IC8 ? (thread_en ? {pcr[5:0],pc2} : {pcr[5:0],pc0plus12}) : L1_adr),
|
.adr(icstate==IDLE||icstate==IC8 ? {pcr[5:0],pc2} : L1_adr),
|
|
`else
|
|
.adr(icstate==IDLE||icstate==IC8 ? {pcr[5:0],pc0plus12} : L1_adr),
|
|
`endif
|
|
.wadr(L1_adr),
|
.wadr(L1_adr),
|
.i(L2_rdat),
|
.i(L2_rdat),
|
.o(insn2b),
|
.o(insn2b),
|
.hit(ihit2),
|
.hit(ihit2),
|
.invall(invic),
|
.invall(invic),
|
| Line 1125... |
Line 1140... |
.pcB(fetchbufB_pc),
|
.pcB(fetchbufB_pc),
|
.pcC(fetchbufC_pc),
|
.pcC(fetchbufC_pc),
|
.pcD(fetchbufD_pc),
|
.pcD(fetchbufD_pc),
|
.xpc0(iqentry_pc[head0]),
|
.xpc0(iqentry_pc[head0]),
|
.xpc1(iqentry_pc[head1]),
|
.xpc1(iqentry_pc[head1]),
|
.takb0(commit0_v & iqentry_res[head0][0]),
|
.takb0(commit0_v & iqentry_takb[head0]),
|
.takb1(commit1_v & iqentry_res[head1][0]),
|
.takb1(commit1_v & iqentry_takb[head1]),
|
.predict_takenA(predict_takenA),
|
.predict_takenA(predict_takenA),
|
.predict_takenB(predict_takenB),
|
.predict_takenB(predict_takenB),
|
.predict_takenC(predict_takenC),
|
.predict_takenC(predict_takenC),
|
.predict_takenD(predict_takenD)
|
.predict_takenD(predict_takenD)
|
);
|
);
|
| Line 1379... |
Line 1394... |
`endif
|
`endif
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
|
|
// hirq squashes the pc increment if there's an irq.
|
// freezePC squashes the pc increment if there's an irq.
|
wire hirq = (irq_i > im) && ~int_commit;
|
wire freezePC = (irq_i > im) && ~int_commit;
|
always @*
|
always @*
|
if (hirq)
|
if (freezePC)
|
insn0 <= {8'd0,3'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
|
insn0 <= {8'd0,3'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
|
else if (phit) begin
|
else if (phit) begin
|
if (insn0a[`INSTRUCTION_OP]==`BRK && insn0a[23:21]==3'd0 && insn0a[7:6]==2'b00)
|
if (insn0a[`INSTRUCTION_OP]==`BRK && insn0a[23:21]==3'd0 && insn0a[7:6]==2'b00)
|
insn0 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
insn0 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
else
|
else
|
| Line 1395... |
Line 1410... |
else
|
else
|
insn0 <= `NOP_INSN;
|
insn0 <= `NOP_INSN;
|
generate begin : gInsnMux
|
generate begin : gInsnMux
|
if (`WAYS > 1) begin
|
if (`WAYS > 1) begin
|
always @*
|
always @*
|
if (phit) begin
|
if (freezePC && !thread_en)
|
|
insn1 <= {8'd0,3'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
|
|
else if (phit) begin
|
if (insn1a[`INSTRUCTION_OP]==`BRK && insn1a[23:21]==3'd0 && insn1a[7:6]==2'b00)
|
if (insn1a[`INSTRUCTION_OP]==`BRK && insn1a[23:21]==3'd0 && insn1a[7:6]==2'b00)
|
insn1 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
insn1 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
else
|
else
|
insn1 <= insn1a;
|
insn1 <= insn1a;
|
end
|
end
|
else
|
else
|
insn1 <= `NOP_INSN;
|
insn1 <= `NOP_INSN;
|
end
|
end
|
if (`WAYS > 2) begin
|
if (`WAYS > 2) begin
|
always @*
|
always @*
|
if (phit) begin
|
if (freezePC && !thread_en)
|
|
insn2 <= {8'd0,3'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
|
|
else if (phit) begin
|
if (insn2a[`INSTRUCTION_OP]==`BRK && insn1a[23:21]==3'd0 && insn2a[7:6]==2'b00)
|
if (insn2a[`INSTRUCTION_OP]==`BRK && insn1a[23:21]==3'd0 && insn2a[7:6]==2'b00)
|
insn2 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
insn2 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
else
|
else
|
insn2 <= insn2a;
|
insn2 <= insn2a;
|
end
|
end
|
| Line 1490... |
Line 1509... |
end
|
end
|
endgenerate
|
endgenerate
|
|
|
function [`QBITS] idp1;
|
function [`QBITS] idp1;
|
input [`QBITS] id;
|
input [`QBITS] id;
|
case(id)
|
idp1 = (id + 1) % QENTRIES;
|
3'd0: idp1 = 3'd1;
|
|
3'd1: idp1 = 3'd2;
|
|
3'd2: idp1 = 3'd3;
|
|
3'd3: idp1 = 3'd4;
|
|
3'd4: idp1 = 3'd5;
|
|
3'd5: idp1 = 3'd6;
|
|
3'd6: idp1 = 3'd7;
|
|
3'd7: idp1 = 3'd0;
|
|
endcase
|
|
endfunction
|
endfunction
|
|
|
function [`QBITS] idp2;
|
function [`QBITS] idp2;
|
input [`QBITS] id;
|
input [`QBITS] id;
|
case(id)
|
idp2 = (id + 2) % QENTRIES;
|
3'd0: idp2 = 3'd2;
|
|
3'd1: idp2 = 3'd3;
|
|
3'd2: idp2 = 3'd4;
|
|
3'd3: idp2 = 3'd5;
|
|
3'd4: idp2 = 3'd6;
|
|
3'd5: idp2 = 3'd7;
|
|
3'd6: idp2 = 3'd0;
|
|
3'd7: idp2 = 3'd1;
|
|
endcase
|
|
endfunction
|
endfunction
|
|
|
function [`QBITS] idp3;
|
function [`QBITS] idp3;
|
input [`QBITS] id;
|
input [`QBITS] id;
|
case(id)
|
idp3 = (id + 3) % QENTRIES;
|
3'd0: idp3 = 3'd3;
|
|
3'd1: idp3 = 3'd4;
|
|
3'd2: idp3 = 3'd5;
|
|
3'd3: idp3 = 3'd6;
|
|
3'd4: idp3 = 3'd7;
|
|
3'd5: idp3 = 3'd0;
|
|
3'd6: idp3 = 3'd1;
|
|
3'd7: idp3 = 3'd2;
|
|
endcase
|
|
endfunction
|
endfunction
|
|
|
function [`QBITS] idp4;
|
function [`QBITS] idp4;
|
input [`QBITS] id;
|
input [`QBITS] id;
|
case(id)
|
idp4 = (id + 4) % QENTRIES;
|
3'd0: idp4 = 3'd4;
|
|
3'd1: idp4 = 3'd5;
|
|
3'd2: idp4 = 3'd6;
|
|
3'd3: idp4 = 3'd7;
|
|
3'd4: idp4 = 3'd0;
|
|
3'd5: idp4 = 3'd1;
|
|
3'd6: idp4 = 3'd2;
|
|
3'd7: idp4 = 3'd3;
|
|
endcase
|
|
endfunction
|
endfunction
|
|
|
function [`QBITS] idp5;
|
function [`QBITS] idp5;
|
input [`QBITS] id;
|
input [`QBITS] id;
|
case(id)
|
idp5 = (id + 5) % QENTRIES;
|
3'd0: idp5 = 3'd5;
|
|
3'd1: idp5 = 3'd6;
|
|
3'd2: idp5 = 3'd7;
|
|
3'd3: idp5 = 3'd0;
|
|
3'd4: idp5 = 3'd1;
|
|
3'd5: idp5 = 3'd2;
|
|
3'd6: idp5 = 3'd3;
|
|
3'd7: idp5 = 3'd4;
|
|
endcase
|
|
endfunction
|
endfunction
|
|
|
function [`QBITS] idp6;
|
function [`QBITS] idp6;
|
input [`QBITS] id;
|
input [`QBITS] id;
|
case(id)
|
idp6 = (id + 6) % QENTRIES;
|
3'd0: idp6 = 3'd6;
|
|
3'd1: idp6 = 3'd7;
|
|
3'd2: idp6 = 3'd0;
|
|
3'd3: idp6 = 3'd1;
|
|
3'd4: idp6 = 3'd2;
|
|
3'd5: idp6 = 3'd3;
|
|
3'd6: idp6 = 3'd4;
|
|
3'd7: idp6 = 3'd5;
|
|
endcase
|
|
endfunction
|
endfunction
|
|
|
function [`QBITS] idp7;
|
function [`QBITS] idp7;
|
input [`QBITS] id;
|
input [`QBITS] id;
|
case(id)
|
idp7 = (id + 7) % QENTRIES;
|
3'd0: idp7 = 3'd7;
|
endfunction
|
3'd1: idp7 = 3'd0;
|
|
3'd2: idp7 = 3'd1;
|
function [`QBITS] idp8;
|
3'd3: idp7 = 3'd2;
|
input [`QBITS] id;
|
3'd4: idp7 = 3'd3;
|
idp8 = (id + 8) % QENTRIES;
|
3'd5: idp7 = 3'd4;
|
endfunction
|
3'd6: idp7 = 3'd5;
|
|
3'd7: idp7 = 3'd6;
|
function [`QBITS] idp9;
|
endcase
|
input [`QBITS] id;
|
|
idp9 = (id + 9) % QENTRIES;
|
endfunction
|
endfunction
|
|
|
function [`QBITS] idm1;
|
function [`QBITS] idm1;
|
input [`QBITS] id;
|
input [`QBITS] id;
|
case(id)
|
idm1 = (id - 1) % QENTRIES;
|
3'd0: idm1 = 3'd7;
|
|
3'd1: idm1 = 3'd0;
|
|
3'd2: idm1 = 3'd1;
|
|
3'd3: idm1 = 3'd2;
|
|
3'd4: idm1 = 3'd3;
|
|
3'd5: idm1 = 3'd4;
|
|
3'd6: idm1 = 3'd5;
|
|
3'd7: idm1 = 3'd6;
|
|
endcase
|
|
endfunction
|
endfunction
|
|
|
`ifdef SUPPORT_SMT
|
`ifdef SUPPORT_SMT
|
function [RBIT:0] fnRa;
|
function [RBIT:0] fnRa;
|
input [47:0] isn;
|
input [47:0] isn;
|
| Line 3206... |
Line 3163... |
decoder8 iq3(.num({iqentry_tgt[3][8:7],iqentry_tgt[3][5:0]}), .out(iq3_out));
|
decoder8 iq3(.num({iqentry_tgt[3][8:7],iqentry_tgt[3][5:0]}), .out(iq3_out));
|
decoder8 iq4(.num({iqentry_tgt[4][8:7],iqentry_tgt[4][5:0]}), .out(iq4_out));
|
decoder8 iq4(.num({iqentry_tgt[4][8:7],iqentry_tgt[4][5:0]}), .out(iq4_out));
|
decoder8 iq5(.num({iqentry_tgt[5][8:7],iqentry_tgt[5][5:0]}), .out(iq5_out));
|
decoder8 iq5(.num({iqentry_tgt[5][8:7],iqentry_tgt[5][5:0]}), .out(iq5_out));
|
decoder8 iq6(.num({iqentry_tgt[6][8:7],iqentry_tgt[6][5:0]}), .out(iq6_out));
|
decoder8 iq6(.num({iqentry_tgt[6][8:7],iqentry_tgt[6][5:0]}), .out(iq6_out));
|
decoder8 iq7(.num({iqentry_tgt[7][8:7],iqentry_tgt[7][5:0]}), .out(iq7_out));
|
decoder8 iq7(.num({iqentry_tgt[7][8:7],iqentry_tgt[7][5:0]}), .out(iq7_out));
|
|
decoder8 iq8(.num({iqentry_tgt[8][8:7],iqentry_tgt[8][5:0]}), .out(iq8_out));
|
|
decoder8 iq9(.num({iqentry_tgt[9][8:7],iqentry_tgt[9][5:0]}), .out(iq9_out));
|
`else
|
`else
|
decoder7 iq0(.num({iqentry_tgt[0][7],iqentry_tgt[0][5:0]}), .out(iq0_out));
|
decoder7 iq0(.num({iqentry_tgt[0][7],iqentry_tgt[0][5:0]}), .out(iq0_out));
|
decoder7 iq1(.num({iqentry_tgt[1][7],iqentry_tgt[1][5:0]}), .out(iq1_out));
|
decoder7 iq1(.num({iqentry_tgt[1][7],iqentry_tgt[1][5:0]}), .out(iq1_out));
|
decoder7 iq2(.num({iqentry_tgt[2][7],iqentry_tgt[2][5:0]}), .out(iq2_out));
|
decoder7 iq2(.num({iqentry_tgt[2][7],iqentry_tgt[2][5:0]}), .out(iq2_out));
|
decoder7 iq3(.num({iqentry_tgt[3][7],iqentry_tgt[3][5:0]}), .out(iq3_out));
|
decoder7 iq3(.num({iqentry_tgt[3][7],iqentry_tgt[3][5:0]}), .out(iq3_out));
|
decoder7 iq4(.num({iqentry_tgt[4][7],iqentry_tgt[4][5:0]}), .out(iq4_out));
|
decoder7 iq4(.num({iqentry_tgt[4][7],iqentry_tgt[4][5:0]}), .out(iq4_out));
|
decoder7 iq5(.num({iqentry_tgt[5][7],iqentry_tgt[5][5:0]}), .out(iq5_out));
|
decoder7 iq5(.num({iqentry_tgt[5][7],iqentry_tgt[5][5:0]}), .out(iq5_out));
|
decoder7 iq6(.num({iqentry_tgt[6][7],iqentry_tgt[6][5:0]}), .out(iq6_out));
|
decoder7 iq6(.num({iqentry_tgt[6][7],iqentry_tgt[6][5:0]}), .out(iq6_out));
|
decoder7 iq7(.num({iqentry_tgt[7][7],iqentry_tgt[7][5:0]}), .out(iq7_out));
|
decoder7 iq7(.num({iqentry_tgt[7][7],iqentry_tgt[7][5:0]}), .out(iq7_out));
|
|
decoder7 iq8(.num({iqentry_tgt[8][7],iqentry_tgt[8][5:0]}), .out(iq8_out));
|
|
decoder7 iq9(.num({iqentry_tgt[9][7],iqentry_tgt[9][5:0]}), .out(iq9_out));
|
/*
|
/*
|
decoder6 iq0(.num({iqentry_tgt[0][5:0]}), .out(iq0_out));
|
decoder6 iq0(.num({iqentry_tgt[0][5:0]}), .out(iq0_out));
|
decoder6 iq1(.num({iqentry_tgt[1][5:0]}), .out(iq1_out));
|
decoder6 iq1(.num({iqentry_tgt[1][5:0]}), .out(iq1_out));
|
decoder6 iq2(.num({iqentry_tgt[2][5:0]}), .out(iq2_out));
|
decoder6 iq2(.num({iqentry_tgt[2][5:0]}), .out(iq2_out));
|
decoder6 iq3(.num({iqentry_tgt[3][5:0]}), .out(iq3_out));
|
decoder6 iq3(.num({iqentry_tgt[3][5:0]}), .out(iq3_out));
|
| Line 3273... |
Line 3234... |
.stb_i(stb_o),
|
.stb_i(stb_o),
|
.ack_o(dc_ack),
|
.ack_o(dc_ack),
|
.we_i(we_o),
|
.we_i(we_o),
|
.adr_i(adr_o[15:0]),
|
.adr_i(adr_o[15:0]),
|
.dat_i(dat_o[31:0]),
|
.dat_i(dat_o[31:0]),
|
.hirq(hirq),
|
.freezePC(freezePC),
|
.regLR(regLR),
|
.regLR(regLR),
|
.thread_en(thread_en),
|
.thread_en(thread_en),
|
.insn0(insn0),
|
.insn0(insn0),
|
.insn1(insn1),
|
.insn1(insn1),
|
.phit(phit),
|
.phit(phit),
|
| Line 3352... |
Line 3313... |
iqentry_2_livetarget[g] |
|
iqentry_2_livetarget[g] |
|
iqentry_3_livetarget[g] |
|
iqentry_3_livetarget[g] |
|
iqentry_4_livetarget[g] |
|
iqentry_4_livetarget[g] |
|
iqentry_5_livetarget[g] |
|
iqentry_5_livetarget[g] |
|
iqentry_6_livetarget[g] |
|
iqentry_6_livetarget[g] |
|
iqentry_7_livetarget[g];
|
iqentry_7_livetarget[g] |
|
|
iqentry_8_livetarget[g] |
|
|
iqentry_9_livetarget[g]
|
|
;
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
assign iqentry_0_livetarget = {PREGS {iqentry_v[0]}} & {PREGS {~iqentry_stomp[0] && iqentry_thrd[0]==branchmiss_thrd}} & iq0_out,
|
assign iqentry_0_livetarget = {PREGS {iqentry_v[0]}} & {PREGS {~iqentry_stomp[0] && iqentry_thrd[0]==branchmiss_thrd}} & iq0_out,
|
| Line 3364... |
Line 3328... |
iqentry_2_livetarget = {PREGS {iqentry_v[2]}} & {PREGS {~iqentry_stomp[2] && iqentry_thrd[2]==branchmiss_thrd}} & iq2_out,
|
iqentry_2_livetarget = {PREGS {iqentry_v[2]}} & {PREGS {~iqentry_stomp[2] && iqentry_thrd[2]==branchmiss_thrd}} & iq2_out,
|
iqentry_3_livetarget = {PREGS {iqentry_v[3]}} & {PREGS {~iqentry_stomp[3] && iqentry_thrd[3]==branchmiss_thrd}} & iq3_out,
|
iqentry_3_livetarget = {PREGS {iqentry_v[3]}} & {PREGS {~iqentry_stomp[3] && iqentry_thrd[3]==branchmiss_thrd}} & iq3_out,
|
iqentry_4_livetarget = {PREGS {iqentry_v[4]}} & {PREGS {~iqentry_stomp[4] && iqentry_thrd[4]==branchmiss_thrd}} & iq4_out,
|
iqentry_4_livetarget = {PREGS {iqentry_v[4]}} & {PREGS {~iqentry_stomp[4] && iqentry_thrd[4]==branchmiss_thrd}} & iq4_out,
|
iqentry_5_livetarget = {PREGS {iqentry_v[5]}} & {PREGS {~iqentry_stomp[5] && iqentry_thrd[5]==branchmiss_thrd}} & iq5_out,
|
iqentry_5_livetarget = {PREGS {iqentry_v[5]}} & {PREGS {~iqentry_stomp[5] && iqentry_thrd[5]==branchmiss_thrd}} & iq5_out,
|
iqentry_6_livetarget = {PREGS {iqentry_v[6]}} & {PREGS {~iqentry_stomp[6] && iqentry_thrd[6]==branchmiss_thrd}} & iq6_out,
|
iqentry_6_livetarget = {PREGS {iqentry_v[6]}} & {PREGS {~iqentry_stomp[6] && iqentry_thrd[6]==branchmiss_thrd}} & iq6_out,
|
iqentry_7_livetarget = {PREGS {iqentry_v[7]}} & {PREGS {~iqentry_stomp[7] && iqentry_thrd[7]==branchmiss_thrd}} & iq7_out;
|
iqentry_7_livetarget = {PREGS {iqentry_v[7]}} & {PREGS {~iqentry_stomp[7] && iqentry_thrd[7]==branchmiss_thrd}} & iq7_out,
|
|
iqentry_8_livetarget = {PREGS {iqentry_v[8]}} & {PREGS {~iqentry_stomp[8] && iqentry_thrd[8]==branchmiss_thrd}} & iq8_out,
|
|
iqentry_9_livetarget = {PREGS {iqentry_v[9]}} & {PREGS {~iqentry_stomp[9] && iqentry_thrd[9]==branchmiss_thrd}} & iq9_out
|
|
;
|
|
|
//
|
//
|
// BRANCH-MISS LOGIC: latestID
|
// BRANCH-MISS LOGIC: latestID
|
//
|
//
|
// latestID is the instruction queue ID of the newest instruction (latest) that targets
|
// latestID is the instruction queue ID of the newest instruction (latest) that targets
|
// a particular register. looks a lot like scheduling logic, but in reverse.
|
// a particular register. looks a lot like scheduling logic, but in reverse.
|
//
|
//
|
assign iqentry_0_cumulative = (missid==3'd0) ? iqentry_0_livetarget :
|
always @*
|
(missid==3'd1) ? iqentry_0_livetarget |
|
for (n = 0; n < QENTRIES; n = n + 1) begin
|
iqentry_1_livetarget :
|
iqentry_cumulative[n] = 0;
|
(missid==3'd2) ? iqentry_0_livetarget |
|
for (j = n; j < n + QENTRIES; j = j + 1) begin
|
iqentry_1_livetarget |
|
if (missid==(j % QENTRIES))
|
iqentry_2_livetarget :
|
for (k = n; k <= j; k = k + 1)
|
(missid==3'd3) ? iqentry_0_livetarget |
|
iqentry_cumulative[n] = iqentry_cumulative[n] | iqentry_livetarget[k % QENTRIES];
|
iqentry_1_livetarget |
|
end
|
iqentry_2_livetarget |
|
end
|
iqentry_3_livetarget :
|
/*
|
(missid==3'd4) ? iqentry_0_livetarget |
|
assign iqentry_0_cumulative = (missid==3'd0) ? iqentry_0_livetarget :
|
iqentry_1_livetarget |
|
(missid==3'd1) ? iqentry_0_livetarget |
|
iqentry_2_livetarget |
|
iqentry_1_livetarget :
|
iqentry_3_livetarget |
|
(missid==3'd2) ? iqentry_0_livetarget |
|
iqentry_4_livetarget :
|
iqentry_1_livetarget |
|
(missid==3'd5) ? iqentry_0_livetarget |
|
iqentry_2_livetarget :
|
iqentry_1_livetarget |
|
(missid==3'd3) ? iqentry_0_livetarget |
|
iqentry_2_livetarget |
|
iqentry_1_livetarget |
|
iqentry_3_livetarget |
|
iqentry_2_livetarget |
|
iqentry_4_livetarget |
|
iqentry_3_livetarget :
|
iqentry_5_livetarget :
|
(missid==3'd4) ? iqentry_0_livetarget |
|
(missid==3'd6) ? iqentry_0_livetarget |
|
iqentry_1_livetarget |
|
iqentry_1_livetarget |
|
iqentry_2_livetarget |
|
iqentry_2_livetarget |
|
iqentry_3_livetarget |
|
iqentry_3_livetarget |
|
iqentry_4_livetarget :
|
iqentry_4_livetarget |
|
(missid==3'd5) ? iqentry_0_livetarget |
|
iqentry_5_livetarget |
|
iqentry_1_livetarget |
|
iqentry_6_livetarget :
|
iqentry_2_livetarget |
|
(missid==3'd7) ? iqentry_0_livetarget |
|
iqentry_3_livetarget |
|
iqentry_1_livetarget |
|
iqentry_4_livetarget |
|
iqentry_2_livetarget |
|
iqentry_5_livetarget :
|
iqentry_3_livetarget |
|
(missid==3'd6) ? iqentry_0_livetarget |
|
iqentry_4_livetarget |
|
iqentry_1_livetarget |
|
iqentry_5_livetarget |
|
iqentry_2_livetarget |
|
iqentry_6_livetarget |
|
iqentry_3_livetarget |
|
iqentry_7_livetarget :
|
iqentry_4_livetarget |
|
{PREGS{1'b0}};
|
iqentry_5_livetarget |
|
|
iqentry_6_livetarget :
|
assign iqentry_1_cumulative = (missid==3'd1) ? iqentry_1_livetarget :
|
(missid==3'd7) ? iqentry_0_livetarget |
|
(missid==3'd2) ? iqentry_1_livetarget |
|
iqentry_1_livetarget |
|
iqentry_2_livetarget :
|
iqentry_2_livetarget |
|
(missid==3'd3) ? iqentry_1_livetarget |
|
iqentry_3_livetarget |
|
iqentry_2_livetarget |
|
iqentry_4_livetarget |
|
iqentry_3_livetarget :
|
iqentry_5_livetarget |
|
(missid==3'd4) ? iqentry_1_livetarget |
|
iqentry_6_livetarget |
|
iqentry_2_livetarget |
|
iqentry_7_livetarget :
|
iqentry_3_livetarget |
|
{PREGS{1'b0}};
|
iqentry_4_livetarget :
|
|
(missid==3'd5) ? iqentry_1_livetarget |
|
assign iqentry_1_cumulative = (missid==4'd1) ? iqentry_1_livetarget :
|
iqentry_2_livetarget |
|
(missid==4'd2) ? iqentry_1_livetarget |
|
iqentry_3_livetarget |
|
iqentry_2_livetarget :
|
iqentry_4_livetarget |
|
(missid==4'd3) ? iqentry_1_livetarget |
|
iqentry_5_livetarget :
|
iqentry_2_livetarget |
|
(missid==3'd6) ? iqentry_1_livetarget |
|
iqentry_3_livetarget :
|
iqentry_2_livetarget |
|
(missid==4'd4) ? iqentry_1_livetarget |
|
iqentry_3_livetarget |
|
iqentry_2_livetarget |
|
iqentry_4_livetarget |
|
iqentry_3_livetarget |
|
iqentry_5_livetarget |
|
iqentry_4_livetarget :
|
iqentry_6_livetarget :
|
(missid==4'd5) ? iqentry_1_livetarget |
|
(missid==3'd7) ? iqentry_1_livetarget |
|
iqentry_2_livetarget |
|
iqentry_2_livetarget |
|
iqentry_3_livetarget |
|
iqentry_3_livetarget |
|
iqentry_4_livetarget |
|
iqentry_4_livetarget |
|
iqentry_5_livetarget :
|
iqentry_5_livetarget |
|
(missid==4'd6) ? iqentry_1_livetarget |
|
iqentry_6_livetarget |
|
iqentry_2_livetarget |
|
iqentry_7_livetarget :
|
iqentry_3_livetarget |
|
(missid==3'd0) ? iqentry_1_livetarget |
|
iqentry_4_livetarget |
|
iqentry_2_livetarget |
|
iqentry_5_livetarget |
|
iqentry_3_livetarget |
|
iqentry_6_livetarget :
|
iqentry_4_livetarget |
|
(missid==4'd7) ? iqentry_1_livetarget |
|
iqentry_5_livetarget |
|
iqentry_2_livetarget |
|
iqentry_6_livetarget |
|
iqentry_3_livetarget |
|
iqentry_7_livetarget |
|
iqentry_4_livetarget |
|
iqentry_0_livetarget :
|
iqentry_5_livetarget |
|
{PREGS{1'b0}};
|
iqentry_6_livetarget |
|
|
iqentry_7_livetarget :
|
assign iqentry_2_cumulative = (missid==3'd2) ? iqentry_2_livetarget :
|
(missid==4'd0) ? iqentry_1_livetarget |
|
(missid==3'd3) ? iqentry_2_livetarget |
|
iqentry_2_livetarget |
|
iqentry_3_livetarget :
|
iqentry_3_livetarget |
|
(missid==3'd4) ? iqentry_2_livetarget |
|
iqentry_4_livetarget |
|
iqentry_3_livetarget |
|
iqentry_5_livetarget |
|
iqentry_4_livetarget :
|
iqentry_6_livetarget |
|
(missid==3'd5) ? iqentry_2_livetarget |
|
iqentry_7_livetarget |
|
iqentry_3_livetarget |
|
iqentry_0_livetarget :
|
iqentry_4_livetarget |
|
{PREGS{1'b0}};
|
iqentry_5_livetarget :
|
|
(missid==3'd6) ? iqentry_2_livetarget |
|
assign iqentry_2_cumulative = (missid==4'd2) ? iqentry_2_livetarget :
|
iqentry_3_livetarget |
|
(missid==4'd3) ? iqentry_2_livetarget |
|
iqentry_4_livetarget |
|
iqentry_3_livetarget :
|
iqentry_5_livetarget |
|
(missid==4'd4) ? iqentry_2_livetarget |
|
iqentry_6_livetarget :
|
iqentry_3_livetarget |
|
(missid==3'd7) ? iqentry_2_livetarget |
|
iqentry_4_livetarget :
|
iqentry_3_livetarget |
|
(missid==4'd5) ? iqentry_2_livetarget |
|
iqentry_4_livetarget |
|
iqentry_3_livetarget |
|
iqentry_5_livetarget |
|
iqentry_4_livetarget |
|
iqentry_6_livetarget |
|
iqentry_5_livetarget :
|
iqentry_7_livetarget :
|
(missid==4'd6) ? iqentry_2_livetarget |
|
(missid==3'd0) ? iqentry_2_livetarget |
|
iqentry_3_livetarget |
|
iqentry_3_livetarget |
|
iqentry_4_livetarget |
|
iqentry_4_livetarget |
|
iqentry_5_livetarget |
|
iqentry_5_livetarget |
|
iqentry_6_livetarget :
|
iqentry_6_livetarget |
|
(missid==4'd7) ? iqentry_2_livetarget |
|
iqentry_7_livetarget |
|
iqentry_3_livetarget |
|
iqentry_0_livetarget :
|
iqentry_4_livetarget |
|
(missid==3'd1) ? iqentry_2_livetarget |
|
iqentry_5_livetarget |
|
iqentry_3_livetarget |
|
iqentry_6_livetarget |
|
iqentry_4_livetarget |
|
iqentry_7_livetarget :
|
iqentry_5_livetarget |
|
(missid==4'd0) ? iqentry_2_livetarget |
|
iqentry_6_livetarget |
|
iqentry_3_livetarget |
|
iqentry_7_livetarget |
|
iqentry_4_livetarget |
|
iqentry_0_livetarget |
|
iqentry_5_livetarget |
|
iqentry_1_livetarget :
|
iqentry_6_livetarget |
|
{PREGS{1'b0}};
|
iqentry_7_livetarget |
|
|
iqentry_0_livetarget :
|
assign iqentry_3_cumulative = (missid==3'd3) ? iqentry_3_livetarget :
|
(missid==4'd1) ? iqentry_2_livetarget |
|
(missid==3'd4) ? iqentry_3_livetarget |
|
iqentry_3_livetarget |
|
iqentry_4_livetarget :
|
iqentry_4_livetarget |
|
(missid==3'd5) ? iqentry_3_livetarget |
|
iqentry_5_livetarget |
|
iqentry_4_livetarget |
|
iqentry_6_livetarget |
|
iqentry_5_livetarget :
|
iqentry_7_livetarget |
|
(missid==3'd6) ? iqentry_3_livetarget |
|
iqentry_0_livetarget |
|
iqentry_4_livetarget |
|
iqentry_1_livetarget :
|
iqentry_5_livetarget |
|
{PREGS{1'b0}};
|
iqentry_6_livetarget :
|
|
(missid==3'd7) ? iqentry_3_livetarget |
|
assign iqentry_3_cumulative = (missid==4'd3) ? iqentry_3_livetarget :
|
iqentry_4_livetarget |
|
(missid==4'd4) ? iqentry_3_livetarget |
|
iqentry_5_livetarget |
|
iqentry_4_livetarget :
|
iqentry_6_livetarget |
|
(missid==4'd5) ? iqentry_3_livetarget |
|
iqentry_7_livetarget :
|
iqentry_4_livetarget |
|
(missid==3'd0) ? iqentry_3_livetarget |
|
iqentry_5_livetarget :
|
iqentry_4_livetarget |
|
(missid==4'd6) ? iqentry_3_livetarget |
|
iqentry_5_livetarget |
|
iqentry_4_livetarget |
|
iqentry_6_livetarget |
|
iqentry_5_livetarget |
|
iqentry_7_livetarget |
|
iqentry_6_livetarget :
|
iqentry_0_livetarget :
|
(missid==4'd7) ? iqentry_3_livetarget |
|
(missid==3'd1) ? iqentry_3_livetarget |
|
iqentry_4_livetarget |
|
iqentry_4_livetarget |
|
iqentry_5_livetarget |
|
iqentry_5_livetarget |
|
iqentry_6_livetarget |
|
iqentry_6_livetarget |
|
iqentry_7_livetarget :
|
iqentry_7_livetarget |
|
(missid==4'd0) ? iqentry_3_livetarget |
|
iqentry_0_livetarget |
|
iqentry_4_livetarget |
|
iqentry_1_livetarget :
|
iqentry_5_livetarget |
|
(missid==3'd2) ? iqentry_3_livetarget |
|
iqentry_6_livetarget |
|
iqentry_4_livetarget |
|
iqentry_7_livetarget |
|
iqentry_5_livetarget |
|
iqentry_0_livetarget :
|
iqentry_6_livetarget |
|
(missid==4'd1) ? iqentry_3_livetarget |
|
iqentry_7_livetarget |
|
iqentry_4_livetarget |
|
iqentry_0_livetarget |
|
iqentry_5_livetarget |
|
iqentry_1_livetarget |
|
iqentry_6_livetarget |
|
iqentry_2_livetarget :
|
iqentry_7_livetarget |
|
{PREGS{1'b0}};
|
iqentry_0_livetarget |
|
|
iqentry_1_livetarget :
|
assign iqentry_4_cumulative = (missid==3'd4) ? iqentry_4_livetarget :
|
(missid==4'd2) ? iqentry_3_livetarget |
|
(missid==3'd5) ? iqentry_4_livetarget |
|
iqentry_4_livetarget |
|
iqentry_5_livetarget :
|
iqentry_5_livetarget |
|
(missid==3'd6) ? iqentry_4_livetarget |
|
iqentry_6_livetarget |
|
iqentry_5_livetarget |
|
iqentry_7_livetarget |
|
iqentry_6_livetarget :
|
iqentry_0_livetarget |
|
(missid==3'd7) ? iqentry_4_livetarget |
|
iqentry_1_livetarget |
|
iqentry_5_livetarget |
|
iqentry_2_livetarget :
|
iqentry_6_livetarget |
|
{PREGS{1'b0}};
|
iqentry_7_livetarget :
|
|
(missid==3'd0) ? iqentry_4_livetarget |
|
assign iqentry_4_cumulative = (missid==4'd4) ? iqentry_4_livetarget :
|
iqentry_5_livetarget |
|
(missid==4'd5) ? iqentry_4_livetarget |
|
iqentry_6_livetarget |
|
iqentry_5_livetarget :
|
iqentry_7_livetarget |
|
(missid==4'd6) ? iqentry_4_livetarget |
|
iqentry_0_livetarget :
|
iqentry_5_livetarget |
|
(missid==3'd1) ? iqentry_4_livetarget |
|
iqentry_6_livetarget :
|
iqentry_5_livetarget |
|
(missid==4'd7) ? iqentry_4_livetarget |
|
iqentry_6_livetarget |
|
iqentry_5_livetarget |
|
iqentry_7_livetarget |
|
iqentry_6_livetarget |
|
iqentry_0_livetarget |
|
iqentry_7_livetarget :
|
iqentry_1_livetarget :
|
(missid==4'd0) ? iqentry_4_livetarget |
|
(missid==3'd2) ? iqentry_4_livetarget |
|
iqentry_5_livetarget |
|
iqentry_5_livetarget |
|
iqentry_6_livetarget |
|
iqentry_6_livetarget |
|
iqentry_7_livetarget |
|
iqentry_7_livetarget |
|
iqentry_0_livetarget :
|
iqentry_0_livetarget |
|
(missid==4'd1) ? iqentry_4_livetarget |
|
iqentry_1_livetarget |
|
iqentry_5_livetarget |
|
iqentry_2_livetarget :
|
iqentry_6_livetarget |
|
(missid==3'd3) ? iqentry_4_livetarget |
|
iqentry_7_livetarget |
|
iqentry_5_livetarget |
|
iqentry_0_livetarget |
|
iqentry_6_livetarget |
|
iqentry_1_livetarget :
|
iqentry_7_livetarget |
|
(missid==4'd2) ? iqentry_4_livetarget |
|
iqentry_0_livetarget |
|
iqentry_5_livetarget |
|
iqentry_1_livetarget |
|
iqentry_6_livetarget |
|
iqentry_2_livetarget |
|
iqentry_7_livetarget |
|
iqentry_3_livetarget :
|
iqentry_0_livetarget |
|
{PREGS{1'b0}};
|
iqentry_1_livetarget |
|
|
iqentry_2_livetarget :
|
assign iqentry_5_cumulative = (missid==3'd5) ? iqentry_5_livetarget :
|
(missid==4'd3) ? iqentry_4_livetarget |
|
(missid==3'd6) ? iqentry_5_livetarget |
|
iqentry_5_livetarget |
|
iqentry_6_livetarget :
|
iqentry_6_livetarget |
|
(missid==3'd7) ? iqentry_5_livetarget |
|
iqentry_7_livetarget |
|
iqentry_6_livetarget |
|
iqentry_0_livetarget |
|
iqentry_7_livetarget :
|
iqentry_1_livetarget |
|
(missid==3'd0) ? iqentry_5_livetarget |
|
iqentry_2_livetarget |
|
iqentry_6_livetarget |
|
iqentry_3_livetarget :
|
iqentry_7_livetarget |
|
{PREGS{1'b0}};
|
iqentry_0_livetarget :
|
|
(missid==3'd1) ? iqentry_5_livetarget |
|
assign iqentry_5_cumulative = (missid==4'd5) ? iqentry_5_livetarget :
|
iqentry_6_livetarget |
|
(missid==4'd6) ? iqentry_5_livetarget |
|
iqentry_7_livetarget |
|
iqentry_6_livetarget :
|
iqentry_0_livetarget |
|
(missid==4'd7) ? iqentry_5_livetarget |
|
iqentry_1_livetarget :
|
iqentry_6_livetarget |
|
(missid==3'd2) ? iqentry_5_livetarget |
|
iqentry_7_livetarget :
|
iqentry_6_livetarget |
|
(missid==4'd0) ? iqentry_5_livetarget |
|
iqentry_7_livetarget |
|
iqentry_6_livetarget |
|
iqentry_0_livetarget |
|
iqentry_7_livetarget |
|
iqentry_1_livetarget |
|
iqentry_0_livetarget :
|
iqentry_2_livetarget :
|
(missid==4'd1) ? iqentry_5_livetarget |
|
(missid==3'd3) ? iqentry_5_livetarget |
|
iqentry_6_livetarget |
|
iqentry_6_livetarget |
|
iqentry_7_livetarget |
|
iqentry_7_livetarget |
|
iqentry_0_livetarget |
|
iqentry_0_livetarget |
|
iqentry_1_livetarget :
|
iqentry_1_livetarget |
|
(missid==4'd2) ? iqentry_5_livetarget |
|
iqentry_2_livetarget |
|
iqentry_6_livetarget |
|
iqentry_3_livetarget :
|
iqentry_7_livetarget |
|
(missid==3'd4) ? iqentry_5_livetarget |
|
iqentry_0_livetarget |
|
iqentry_6_livetarget |
|
iqentry_1_livetarget |
|
iqentry_7_livetarget |
|
iqentry_2_livetarget :
|
iqentry_0_livetarget |
|
(missid==4'd3) ? iqentry_5_livetarget |
|
iqentry_1_livetarget |
|
iqentry_6_livetarget |
|
iqentry_2_livetarget |
|
iqentry_7_livetarget |
|
iqentry_3_livetarget |
|
iqentry_0_livetarget |
|
iqentry_4_livetarget :
|
iqentry_1_livetarget |
|
{PREGS{1'b0}};
|
iqentry_2_livetarget |
|
assign iqentry_6_cumulative = (missid==3'd6) ? iqentry_6_livetarget :
|
iqentry_3_livetarget :
|
(missid==3'd7) ? iqentry_6_livetarget |
|
(missid==4'd4) ? iqentry_5_livetarget |
|
iqentry_7_livetarget :
|
iqentry_6_livetarget |
|
(missid==3'd0) ? iqentry_6_livetarget |
|
iqentry_7_livetarget |
|
iqentry_7_livetarget |
|
iqentry_0_livetarget |
|
iqentry_0_livetarget :
|
iqentry_1_livetarget |
|
(missid==3'd1) ? iqentry_6_livetarget |
|
iqentry_2_livetarget |
|
iqentry_7_livetarget |
|
iqentry_3_livetarget |
|
iqentry_0_livetarget |
|
iqentry_4_livetarget :
|
iqentry_1_livetarget :
|
{PREGS{1'b0}};
|
(missid==3'd2) ? iqentry_6_livetarget |
|
assign iqentry_6_cumulative = (missid==4'd6) ? iqentry_6_livetarget :
|
iqentry_7_livetarget |
|
(missid==4'd7) ? iqentry_6_livetarget |
|
iqentry_0_livetarget |
|
iqentry_7_livetarget :
|
iqentry_1_livetarget |
|
(missid==4'd0) ? iqentry_6_livetarget |
|
iqentry_2_livetarget :
|
iqentry_7_livetarget |
|
(missid==3'd3) ? iqentry_6_livetarget |
|
iqentry_0_livetarget :
|
iqentry_7_livetarget |
|
(missid==4'd1) ? iqentry_6_livetarget |
|
iqentry_0_livetarget |
|
iqentry_7_livetarget |
|
iqentry_1_livetarget |
|
iqentry_0_livetarget |
|
iqentry_2_livetarget |
|
iqentry_1_livetarget :
|
iqentry_3_livetarget :
|
(missid==4'd2) ? iqentry_6_livetarget |
|
(missid==3'd4) ? iqentry_6_livetarget |
|
iqentry_7_livetarget |
|
iqentry_7_livetarget |
|
iqentry_0_livetarget |
|
iqentry_0_livetarget |
|
iqentry_1_livetarget |
|
iqentry_1_livetarget |
|
iqentry_2_livetarget :
|
iqentry_2_livetarget |
|
(missid==4'd3) ? iqentry_6_livetarget |
|
iqentry_3_livetarget |
|
iqentry_7_livetarget |
|
iqentry_4_livetarget :
|
iqentry_0_livetarget |
|
(missid==3'd5) ? iqentry_6_livetarget |
|
iqentry_1_livetarget |
|
iqentry_7_livetarget |
|
iqentry_2_livetarget |
|
iqentry_0_livetarget |
|
iqentry_3_livetarget :
|
iqentry_1_livetarget |
|
(missid==4'd4) ? iqentry_6_livetarget |
|
iqentry_2_livetarget |
|
iqentry_7_livetarget |
|
iqentry_3_livetarget |
|
iqentry_0_livetarget |
|
iqentry_4_livetarget |
|
iqentry_1_livetarget |
|
iqentry_5_livetarget :
|
iqentry_2_livetarget |
|
{PREGS{1'b0}};
|
iqentry_3_livetarget |
|
|
iqentry_4_livetarget :
|
assign iqentry_7_cumulative = (missid==3'd7) ? iqentry_7_livetarget :
|
(missid==4'd5) ? iqentry_6_livetarget |
|
(missid==3'd0) ? iqentry_7_livetarget |
|
iqentry_7_livetarget |
|
iqentry_0_livetarget :
|
iqentry_0_livetarget |
|
(missid==3'd1) ? iqentry_7_livetarget |
|
iqentry_1_livetarget |
|
iqentry_0_livetarget |
|
iqentry_2_livetarget |
|
iqentry_1_livetarget :
|
iqentry_3_livetarget |
|
(missid==3'd2) ? iqentry_7_livetarget |
|
iqentry_4_livetarget |
|
iqentry_0_livetarget |
|
iqentry_5_livetarget :
|
iqentry_1_livetarget |
|
{PREGS{1'b0}};
|
iqentry_2_livetarget :
|
|
(missid==3'd3) ? iqentry_7_livetarget |
|
assign iqentry_7_cumulative = (missid==4'd7) ? iqentry_7_livetarget :
|
iqentry_0_livetarget |
|
(missid==4'd0) ? iqentry_7_livetarget |
|
iqentry_1_livetarget |
|
iqentry_0_livetarget :
|
iqentry_2_livetarget |
|
(missid==4'd1) ? iqentry_7_livetarget |
|
iqentry_3_livetarget :
|
iqentry_0_livetarget |
|
(missid==3'd4) ? iqentry_7_livetarget |
|
iqentry_1_livetarget :
|
iqentry_0_livetarget |
|
(missid==4'd2) ? iqentry_7_livetarget |
|
iqentry_1_livetarget |
|
iqentry_0_livetarget |
|
iqentry_2_livetarget |
|
iqentry_1_livetarget |
|
iqentry_3_livetarget |
|
iqentry_2_livetarget :
|
iqentry_4_livetarget :
|
(missid==4'd3) ? iqentry_7_livetarget |
|
(missid==3'd5) ? iqentry_7_livetarget |
|
iqentry_0_livetarget |
|
iqentry_0_livetarget |
|
iqentry_1_livetarget |
|
iqentry_1_livetarget |
|
iqentry_2_livetarget |
|
iqentry_2_livetarget |
|
iqentry_3_livetarget :
|
iqentry_3_livetarget |
|
(missid==4'd4) ? iqentry_7_livetarget |
|
iqentry_4_livetarget |
|
iqentry_0_livetarget |
|
iqentry_5_livetarget :
|
iqentry_1_livetarget |
|
(missid==3'd6) ? iqentry_7_livetarget |
|
iqentry_2_livetarget |
|
iqentry_0_livetarget |
|
iqentry_3_livetarget |
|
iqentry_1_livetarget |
|
iqentry_4_livetarget :
|
iqentry_2_livetarget |
|
(missid==4'd5) ? iqentry_7_livetarget |
|
iqentry_3_livetarget |
|
iqentry_0_livetarget |
|
iqentry_4_livetarget |
|
iqentry_1_livetarget |
|
iqentry_5_livetarget |
|
iqentry_2_livetarget |
|
iqentry_6_livetarget :
|
iqentry_3_livetarget |
|
{PREGS{1'b0}};
|
iqentry_4_livetarget |
|
|
iqentry_5_livetarget :
|
|
(missid==4'd6) ? iqentry_7_livetarget |
|
|
iqentry_0_livetarget |
|
|
iqentry_1_livetarget |
|
|
iqentry_2_livetarget |
|
|
iqentry_3_livetarget |
|
|
iqentry_4_livetarget |
|
|
iqentry_5_livetarget |
|
|
iqentry_6_livetarget :
|
|
{PREGS{1'b0}};
|
|
*/
|
|
assign iqentry_0_latestID = (missid == 4'd0 || ((iqentry_livetarget[0] & iqentry_cumulative[1]) == {PREGS{1'b0}}))
|
|
? iqentry_livetarget[0]
|
|
: {PREGS{1'b0}};
|
|
|
|
assign iqentry_1_latestID = (missid == 4'd1 || ((iqentry_livetarget[1] & iqentry_cumulative[2]) == {PREGS{1'b0}}))
|
|
? iqentry_livetarget[1]
|
|
: {PREGS{1'b0}};
|
|
|
assign iqentry_0_latestID = (missid == 3'd0 || ((iqentry_0_livetarget & iqentry_1_cumulative) == {PREGS{1'b0}}))
|
assign iqentry_2_latestID = (missid == 4'd2 || ((iqentry_livetarget[2] & iqentry_cumulative[3]) == {PREGS{1'b0}}))
|
? iqentry_0_livetarget
|
? iqentry_livetarget[2]
|
: {PREGS{1'b0}};
|
: {PREGS{1'b0}};
|
|
|
assign iqentry_1_latestID = (missid == 3'd1 || ((iqentry_1_livetarget & iqentry_2_cumulative) == {PREGS{1'b0}}))
|
assign iqentry_3_latestID = (missid == 4'd3 || ((iqentry_livetarget[3] & iqentry_cumulative[4]) == {PREGS{1'b0}}))
|
? iqentry_1_livetarget
|
? iqentry_livetarget[3]
|
: {PREGS{1'b0}};
|
: {PREGS{1'b0}};
|
|
|
assign iqentry_2_latestID = (missid == 3'd2 || ((iqentry_2_livetarget & iqentry_3_cumulative) == {PREGS{1'b0}}))
|
assign iqentry_4_latestID = (missid == 4'd4 || ((iqentry_livetarget[4] & iqentry_cumulative[5]) == {PREGS{1'b0}}))
|
? iqentry_2_livetarget
|
? iqentry_livetarget[4]
|
: {PREGS{1'b0}};
|
: {PREGS{1'b0}};
|
|
|
assign iqentry_3_latestID = (missid == 3'd3 || ((iqentry_3_livetarget & iqentry_4_cumulative) == {PREGS{1'b0}}))
|
assign iqentry_5_latestID = (missid == 4'd5 || ((iqentry_livetarget[5] & iqentry_cumulative[6]) == {PREGS{1'b0}}))
|
? iqentry_3_livetarget
|
? iqentry_livetarget[5]
|
: {PREGS{1'b0}};
|
: {PREGS{1'b0}};
|
|
|
assign iqentry_4_latestID = (missid == 3'd4 || ((iqentry_4_livetarget & iqentry_5_cumulative) == {PREGS{1'b0}}))
|
assign iqentry_6_latestID = (missid == 4'd6 || ((iqentry_livetarget[6] & iqentry_cumulative[7]) == {PREGS{1'b0}}))
|
? iqentry_4_livetarget
|
? iqentry_livetarget[6]
|
: {PREGS{1'b0}};
|
: {PREGS{1'b0}};
|
|
|
assign iqentry_5_latestID = (missid == 3'd5 || ((iqentry_5_livetarget & iqentry_6_cumulative) == {PREGS{1'b0}}))
|
assign iqentry_7_latestID = (missid == 4'd7 || ((iqentry_livetarget[7] & iqentry_cumulative[8]) == {PREGS{1'b0}}))
|
? iqentry_5_livetarget
|
? iqentry_livetarget[7]
|
: {PREGS{1'b0}};
|
: {PREGS{1'b0}};
|
|
|
assign iqentry_6_latestID = (missid == 3'd6 || ((iqentry_6_livetarget & iqentry_7_cumulative) == {PREGS{1'b0}}))
|
assign iqentry_8_latestID = (missid == 4'd8 || ((iqentry_livetarget[8] & iqentry_cumulative[9]) == {PREGS{1'b0}}))
|
? iqentry_6_livetarget
|
? iqentry_livetarget[8]
|
: {PREGS{1'b0}};
|
: {PREGS{1'b0}};
|
|
|
assign iqentry_7_latestID = (missid == 3'd7 || ((iqentry_7_livetarget & iqentry_0_cumulative) == {PREGS{1'b0}}))
|
assign iqentry_9_latestID = (missid == 4'd9 || ((iqentry_livetarget[9] & iqentry_cumulative[0]) == {PREGS{1'b0}}))
|
? iqentry_7_livetarget
|
? iqentry_livetarget[9]
|
: {PREGS{1'b0}};
|
: {PREGS{1'b0}};
|
|
|
assign iqentry_source[0] = | iqentry_0_latestID,
|
assign
|
|
iqentry_source[0] = | iqentry_0_latestID,
|
iqentry_source[1] = | iqentry_1_latestID,
|
iqentry_source[1] = | iqentry_1_latestID,
|
iqentry_source[2] = | iqentry_2_latestID,
|
iqentry_source[2] = | iqentry_2_latestID,
|
iqentry_source[3] = | iqentry_3_latestID,
|
iqentry_source[3] = | iqentry_3_latestID,
|
iqentry_source[4] = | iqentry_4_latestID,
|
iqentry_source[4] = | iqentry_4_latestID,
|
iqentry_source[5] = | iqentry_5_latestID,
|
iqentry_source[5] = | iqentry_5_latestID,
|
iqentry_source[6] = | iqentry_6_latestID,
|
iqentry_source[6] = | iqentry_6_latestID,
|
iqentry_source[7] = | iqentry_7_latestID;
|
iqentry_source[7] = | iqentry_7_latestID,
|
|
iqentry_source[8] = | iqentry_8_latestID,
|
|
iqentry_source[9] = | iqentry_9_latestID
|
|
;
|
|
|
|
|
reg vqueued2;
|
reg vqueued2;
|
assign Ra0 = fnRa(fetchbuf0_instr,vqe0,vl,fetchbuf0_thrd) | {fetchbuf0_thrd,7'b0};
|
assign Ra0 = fnRa(fetchbuf0_instr,vqe0,vl,fetchbuf0_thrd) | {fetchbuf0_thrd,7'b0};
|
assign Rb0 = fnRb(fetchbuf0_instr,1'b0,vqe0,rfoa0[5:0],rfoa1[5:0],fetchbuf0_thrd) | {fetchbuf0_thrd,7'b0};
|
assign Rb0 = fnRb(fetchbuf0_instr,1'b0,vqe0,rfoa0[5:0],rfoa1[5:0],fetchbuf0_thrd) | {fetchbuf0_thrd,7'b0};
|
| Line 3775... |
Line 3764... |
assign could_issue[g] = iqentry_v[g] && !iqentry_done[g] && !iqentry_out[g]
|
assign could_issue[g] = iqentry_v[g] && !iqentry_done[g] && !iqentry_out[g]
|
&& args_valid[g]
|
&& args_valid[g]
|
&& iqentry_iv[g]
|
&& iqentry_iv[g]
|
&& (iqentry_mem[g] ? !iqentry_agen[g] : 1'b1);
|
&& (iqentry_mem[g] ? !iqentry_agen[g] : 1'b1);
|
|
|
assign could_issueid[g] = iqentry_v[g] && !iqentry_iv[g];
|
assign could_issueid[g] = (iqentry_v[g])// || (g==tail0 && canq1))// || (g==tail1 && canq2))
|
|
&& !iqentry_iv[g];
|
// && (iqentry_a1_v[g]
|
// && (iqentry_a1_v[g]
|
// || (iqentry_a1_s[g] == alu0_sourceid && alu0_dataready)
|
// || (iqentry_a1_s[g] == alu0_sourceid && alu0_dataready)
|
// || (iqentry_a1_s[g] == alu1_sourceid && alu1_dataready));
|
// || (iqentry_a1_s[g] == alu1_sourceid && alu1_dataready));
|
|
|
end
|
end
|
| Line 3800... |
Line 3790... |
assign heads[3] = head3;
|
assign heads[3] = head3;
|
assign heads[4] = head4;
|
assign heads[4] = head4;
|
assign heads[5] = head5;
|
assign heads[5] = head5;
|
assign heads[6] = head6;
|
assign heads[6] = head6;
|
assign heads[7] = head7;
|
assign heads[7] = head7;
|
|
assign heads[8] = head8;
|
|
assign heads[9] = head9;
|
|
|
always @*
|
always @*
|
begin
|
begin
|
iqentry_id1issue = {QENTRIES{1'b0}};
|
iqentry_id1issue = {QENTRIES{1'b0}};
|
if (id1_available) begin
|
if (id1_available) begin
|
| Line 4366... |
Line 4358... |
// Next queue id
|
// Next queue id
|
|
|
reg [`QBITS] nid0;
|
reg [`QBITS] nid0;
|
always @*
|
always @*
|
if (iqentry_thrd[1]==iqentry_thrd[0])
|
if (iqentry_thrd[1]==iqentry_thrd[0])
|
nid0 = 3'd1;
|
nid0 = 4'd1;
|
else if (iqentry_thrd[2]==iqentry_thrd[0])
|
else if (iqentry_thrd[2]==iqentry_thrd[0])
|
nid0 = 3'd2;
|
nid0 = 4'd2;
|
else if (iqentry_thrd[3]==iqentry_thrd[0])
|
else if (iqentry_thrd[3]==iqentry_thrd[0])
|
nid0 = 3'd3;
|
nid0 = 4'd3;
|
else if (iqentry_thrd[4]==iqentry_thrd[0])
|
else if (iqentry_thrd[4]==iqentry_thrd[0])
|
nid0 = 3'd4;
|
nid0 = 4'd4;
|
else if (iqentry_thrd[5]==iqentry_thrd[0])
|
else if (iqentry_thrd[5]==iqentry_thrd[0])
|
nid0 = 3'd5;
|
nid0 = 4'd5;
|
else if (iqentry_thrd[6]==iqentry_thrd[0])
|
else if (iqentry_thrd[6]==iqentry_thrd[0])
|
nid0 = 3'd6;
|
nid0 = 4'd6;
|
else if (iqentry_thrd[7]==iqentry_thrd[0])
|
else if (iqentry_thrd[7]==iqentry_thrd[0])
|
nid0 = 3'd7;
|
nid0 = 4'd7;
|
|
else if (iqentry_thrd[8]==iqentry_thrd[0])
|
|
nid0 = 4'd8;
|
|
else if (iqentry_thrd[9]==iqentry_thrd[0])
|
|
nid0 = 4'd9;
|
else
|
else
|
nid0 = 3'd0;
|
nid0 = 3'd0;
|
|
|
reg [`QBITS] nid1;
|
reg [`QBITS] nid1;
|
always @*
|
always @*
|
if (iqentry_thrd[2]==iqentry_thrd[1])
|
if (iqentry_thrd[2]==iqentry_thrd[1])
|
nid1 = 3'd2;
|
nid1 = 4'd2;
|
else if (iqentry_thrd[3]==iqentry_thrd[1])
|
else if (iqentry_thrd[3]==iqentry_thrd[1])
|
nid1 = 3'd3;
|
nid1 = 4'd3;
|
else if (iqentry_thrd[4]==iqentry_thrd[1])
|
else if (iqentry_thrd[4]==iqentry_thrd[1])
|
nid1 = 3'd4;
|
nid1 = 4'd4;
|
else if (iqentry_thrd[5]==iqentry_thrd[1])
|
else if (iqentry_thrd[5]==iqentry_thrd[1])
|
nid1 = 3'd5;
|
nid1 = 4'd5;
|
else if (iqentry_thrd[6]==iqentry_thrd[1])
|
else if (iqentry_thrd[6]==iqentry_thrd[1])
|
nid1 = 3'd6;
|
nid1 = 4'd6;
|
else if (iqentry_thrd[7]==iqentry_thrd[1])
|
else if (iqentry_thrd[7]==iqentry_thrd[1])
|
nid1 = 3'd7;
|
nid1 = 4'd7;
|
|
else if (iqentry_thrd[8]==iqentry_thrd[1])
|
|
nid1 = 4'd8;
|
|
else if (iqentry_thrd[9]==iqentry_thrd[1])
|
|
nid1 = 4'd9;
|
else if (iqentry_thrd[0]==iqentry_thrd[1])
|
else if (iqentry_thrd[0]==iqentry_thrd[1])
|
nid1 = 3'd0;
|
nid1 = 4'd0;
|
else
|
else
|
nid1 = 3'd1;
|
nid1 = 4'd1;
|
|
|
reg [`QBITS] nid2;
|
reg [`QBITS] nid2;
|
always @*
|
always @*
|
if (iqentry_thrd[3]==iqentry_thrd[2])
|
if (iqentry_thrd[3]==iqentry_thrd[2])
|
nid2 = 3'd3;
|
nid2 = 4'd3;
|
else if (iqentry_thrd[4]==iqentry_thrd[2])
|
else if (iqentry_thrd[4]==iqentry_thrd[2])
|
nid2 = 3'd4;
|
nid2 = 4'd4;
|
else if (iqentry_thrd[5]==iqentry_thrd[2])
|
else if (iqentry_thrd[5]==iqentry_thrd[2])
|
nid2 = 3'd5;
|
nid2 = 4'd5;
|
else if (iqentry_thrd[6]==iqentry_thrd[2])
|
else if (iqentry_thrd[6]==iqentry_thrd[2])
|
nid2 = 3'd6;
|
nid2 = 4'd6;
|
else if (iqentry_thrd[7]==iqentry_thrd[2])
|
else if (iqentry_thrd[7]==iqentry_thrd[2])
|
nid2 = 3'd7;
|
nid2 = 4'd7;
|
|
else if (iqentry_thrd[8]==iqentry_thrd[2])
|
|
nid2 = 4'd8;
|
|
else if (iqentry_thrd[9]==iqentry_thrd[2])
|
|
nid2 = 4'd9;
|
else if (iqentry_thrd[0]==iqentry_thrd[2])
|
else if (iqentry_thrd[0]==iqentry_thrd[2])
|
nid2 = 3'd0;
|
nid2 = 4'd0;
|
else if (iqentry_thrd[1]==iqentry_thrd[2])
|
else if (iqentry_thrd[1]==iqentry_thrd[2])
|
nid2 = 3'd1;
|
nid2 = 4'd1;
|
else
|
else
|
nid2 = 3'd2;
|
nid2 = 4'd2;
|
|
|
reg [`QBITS] nid3;
|
reg [`QBITS] nid3;
|
always @*
|
always @*
|
if (iqentry_thrd[4]==iqentry_thrd[3])
|
if (iqentry_thrd[4]==iqentry_thrd[3])
|
nid3 = 3'd4;
|
nid3 = 4'd4;
|
else if (iqentry_thrd[5]==iqentry_thrd[3])
|
else if (iqentry_thrd[5]==iqentry_thrd[3])
|
nid3 = 3'd5;
|
nid3 = 4'd5;
|
else if (iqentry_thrd[6]==iqentry_thrd[3])
|
else if (iqentry_thrd[6]==iqentry_thrd[3])
|
nid3 = 3'd6;
|
nid3 = 4'd6;
|
else if (iqentry_thrd[7]==iqentry_thrd[3])
|
else if (iqentry_thrd[7]==iqentry_thrd[3])
|
nid3 = 3'd7;
|
nid3 = 4'd7;
|
|
else if (iqentry_thrd[8]==iqentry_thrd[3])
|
|
nid3 = 4'd8;
|
|
else if (iqentry_thrd[9]==iqentry_thrd[3])
|
|
nid3 = 4'd9;
|
else if (iqentry_thrd[0]==iqentry_thrd[3])
|
else if (iqentry_thrd[0]==iqentry_thrd[3])
|
nid3 = 3'd0;
|
nid3 = 4'd0;
|
else if (iqentry_thrd[1]==iqentry_thrd[3])
|
else if (iqentry_thrd[1]==iqentry_thrd[3])
|
nid3 = 3'd1;
|
nid3 = 4'd1;
|
else if (iqentry_thrd[2]==iqentry_thrd[3])
|
else if (iqentry_thrd[2]==iqentry_thrd[3])
|
nid3 = 3'd2;
|
nid3 = 4'd2;
|
else
|
else
|
nid3 = 3'd3;
|
nid3 = 4'd3;
|
|
|
reg [`QBITS] nid4;
|
reg [`QBITS] nid4;
|
always @*
|
always @*
|
if (iqentry_thrd[5]==iqentry_thrd[4])
|
if (iqentry_thrd[5]==iqentry_thrd[4])
|
nid4 = 3'd5;
|
nid4 = 4'd5;
|
else if (iqentry_thrd[6]==iqentry_thrd[4])
|
else if (iqentry_thrd[6]==iqentry_thrd[4])
|
nid4 = 3'd6;
|
nid4 = 4'd6;
|
else if (iqentry_thrd[7]==iqentry_thrd[4])
|
else if (iqentry_thrd[7]==iqentry_thrd[4])
|
nid4 = 3'd7;
|
nid4 = 4'd7;
|
|
else if (iqentry_thrd[8]==iqentry_thrd[4])
|
|
nid4 = 4'd8;
|
|
else if (iqentry_thrd[9]==iqentry_thrd[4])
|
|
nid4 = 4'd9;
|
else if (iqentry_thrd[0]==iqentry_thrd[4])
|
else if (iqentry_thrd[0]==iqentry_thrd[4])
|
nid4 = 3'd0;
|
nid4 = 4'd0;
|
else if (iqentry_thrd[1]==iqentry_thrd[4])
|
else if (iqentry_thrd[1]==iqentry_thrd[4])
|
nid4 = 3'd1;
|
nid4 = 4'd1;
|
else if (iqentry_thrd[2]==iqentry_thrd[4])
|
else if (iqentry_thrd[2]==iqentry_thrd[4])
|
nid4 = 3'd2;
|
nid4 = 4'd2;
|
else if (iqentry_thrd[3]==iqentry_thrd[4])
|
else if (iqentry_thrd[3]==iqentry_thrd[4])
|
nid4 = 3'd3;
|
nid4 = 4'd3;
|
else
|
else
|
nid4 = 3'd4;
|
nid4 = 4'd4;
|
|
|
reg [`QBITS] nid5;
|
reg [`QBITS] nid5;
|
always @*
|
always @*
|
if (iqentry_thrd[6]==iqentry_thrd[5])
|
if (iqentry_thrd[6]==iqentry_thrd[5])
|
nid5 = 3'd6;
|
nid5 = 4'd6;
|
else if (iqentry_thrd[7]==iqentry_thrd[5])
|
else if (iqentry_thrd[7]==iqentry_thrd[5])
|
nid5 = 3'd7;
|
nid5 = 4'd7;
|
|
else if (iqentry_thrd[8]==iqentry_thrd[5])
|
|
nid5 = 4'd8;
|
|
else if (iqentry_thrd[9]==iqentry_thrd[5])
|
|
nid5 = 4'd9;
|
else if (iqentry_thrd[0]==iqentry_thrd[5])
|
else if (iqentry_thrd[0]==iqentry_thrd[5])
|
nid5 = 3'd0;
|
nid5 = 4'd0;
|
else if (iqentry_thrd[1]==iqentry_thrd[5])
|
else if (iqentry_thrd[1]==iqentry_thrd[5])
|
nid5 = 3'd1;
|
nid5 = 4'd1;
|
else if (iqentry_thrd[2]==iqentry_thrd[5])
|
else if (iqentry_thrd[2]==iqentry_thrd[5])
|
nid5 = 3'd2;
|
nid5 = 4'd2;
|
else if (iqentry_thrd[3]==iqentry_thrd[5])
|
else if (iqentry_thrd[3]==iqentry_thrd[5])
|
nid5 = 3'd3;
|
nid5 = 4'd3;
|
else if (iqentry_thrd[4]==iqentry_thrd[5])
|
else if (iqentry_thrd[4]==iqentry_thrd[5])
|
nid5 = 3'd4;
|
nid5 = 4'd4;
|
else
|
else
|
nid5 = 3'd5;
|
nid5 = 4'd5;
|
|
|
reg [`QBITS] nid6;
|
reg [`QBITS] nid6;
|
always @*
|
always @*
|
if (iqentry_thrd[7]==iqentry_thrd[6])
|
if (iqentry_thrd[7]==iqentry_thrd[6])
|
nid6 = 3'd7;
|
nid6 = 4'd7;
|
|
else if (iqentry_thrd[8]==iqentry_thrd[6])
|
|
nid6 = 4'd8;
|
|
else if (iqentry_thrd[9]==iqentry_thrd[6])
|
|
nid6 = 4'd9;
|
else if (iqentry_thrd[0]==iqentry_thrd[6])
|
else if (iqentry_thrd[0]==iqentry_thrd[6])
|
nid6 = 3'd0;
|
nid6 = 4'd0;
|
else if (iqentry_thrd[1]==iqentry_thrd[6])
|
else if (iqentry_thrd[1]==iqentry_thrd[6])
|
nid6 = 3'd1;
|
nid6 = 4'd1;
|
else if (iqentry_thrd[2]==iqentry_thrd[6])
|
else if (iqentry_thrd[2]==iqentry_thrd[6])
|
nid6 = 3'd2;
|
nid6 = 4'd2;
|
else if (iqentry_thrd[3]==iqentry_thrd[6])
|
else if (iqentry_thrd[3]==iqentry_thrd[6])
|
nid6 = 3'd3;
|
nid6 = 4'd3;
|
else if (iqentry_thrd[4]==iqentry_thrd[6])
|
else if (iqentry_thrd[4]==iqentry_thrd[6])
|
nid6 = 3'd4;
|
nid6 = 4'd4;
|
else if (iqentry_thrd[5]==iqentry_thrd[6])
|
else if (iqentry_thrd[5]==iqentry_thrd[6])
|
nid6 = 3'd5;
|
nid6 = 4'd5;
|
else
|
else
|
nid6 = 3'd6;
|
nid6 = 4'd6;
|
|
|
reg [`QBITS] nid7;
|
reg [`QBITS] nid7;
|
always @*
|
always @*
|
if (iqentry_thrd[0]==iqentry_thrd[7])
|
if (iqentry_thrd[8]==iqentry_thrd[7])
|
nid7 = 3'd0;
|
nid7 = 4'd8;
|
|
else if (iqentry_thrd[9]==iqentry_thrd[7])
|
|
nid7 = 4'd9;
|
|
else if (iqentry_thrd[0]==iqentry_thrd[7])
|
|
nid7 = 4'd0;
|
else if (iqentry_thrd[1]==iqentry_thrd[7])
|
else if (iqentry_thrd[1]==iqentry_thrd[7])
|
nid7 = 3'd1;
|
nid7 = 4'd1;
|
else if (iqentry_thrd[2]==iqentry_thrd[7])
|
else if (iqentry_thrd[2]==iqentry_thrd[7])
|
nid7 = 3'd2;
|
nid7 = 4'd2;
|
else if (iqentry_thrd[3]==iqentry_thrd[7])
|
else if (iqentry_thrd[3]==iqentry_thrd[7])
|
nid7 = 3'd3;
|
nid7 = 4'd3;
|
else if (iqentry_thrd[4]==iqentry_thrd[7])
|
else if (iqentry_thrd[4]==iqentry_thrd[7])
|
nid7 = 3'd4;
|
nid7 = 4'd4;
|
else if (iqentry_thrd[5]==iqentry_thrd[7])
|
else if (iqentry_thrd[5]==iqentry_thrd[7])
|
nid7 = 3'd5;
|
nid7 = 4'd5;
|
else if (iqentry_thrd[6]==iqentry_thrd[7])
|
else if (iqentry_thrd[6]==iqentry_thrd[7])
|
nid7 = 3'd6;
|
nid7 = 4'd6;
|
|
else
|
|
nid7 = 4'd7;
|
|
|
|
reg [`QBITS] nid8;
|
|
always @*
|
|
if (iqentry_thrd[9]==iqentry_thrd[8])
|
|
nid8 = 4'd9;
|
|
else if (iqentry_thrd[0]==iqentry_thrd[8])
|
|
nid8 = 4'd0;
|
|
else if (iqentry_thrd[1]==iqentry_thrd[8])
|
|
nid8 = 4'd1;
|
|
else if (iqentry_thrd[2]==iqentry_thrd[8])
|
|
nid8 = 4'd2;
|
|
else if (iqentry_thrd[3]==iqentry_thrd[8])
|
|
nid8 = 4'd3;
|
|
else if (iqentry_thrd[4]==iqentry_thrd[8])
|
|
nid8 = 4'd4;
|
|
else if (iqentry_thrd[5]==iqentry_thrd[8])
|
|
nid8 = 4'd5;
|
|
else if (iqentry_thrd[6]==iqentry_thrd[8])
|
|
nid8 = 4'd6;
|
|
else if (iqentry_thrd[7]==iqentry_thrd[8])
|
|
nid8 = 4'd7;
|
else
|
else
|
nid7 = 3'd7;
|
nid8 = 4'd8;
|
|
|
|
reg [`QBITS] nid9;
|
|
always @*
|
|
if (iqentry_thrd[0]==iqentry_thrd[9])
|
|
nid9 = 4'd0;
|
|
else if (iqentry_thrd[1]==iqentry_thrd[9])
|
|
nid9 = 4'd1;
|
|
else if (iqentry_thrd[2]==iqentry_thrd[9])
|
|
nid9 = 4'd2;
|
|
else if (iqentry_thrd[3]==iqentry_thrd[9])
|
|
nid9 = 4'd3;
|
|
else if (iqentry_thrd[4]==iqentry_thrd[9])
|
|
nid9 = 4'd4;
|
|
else if (iqentry_thrd[5]==iqentry_thrd[9])
|
|
nid9 = 4'd5;
|
|
else if (iqentry_thrd[6]==iqentry_thrd[9])
|
|
nid9 = 4'd6;
|
|
else if (iqentry_thrd[7]==iqentry_thrd[9])
|
|
nid9 = 4'd7;
|
|
else if (iqentry_thrd[8]==iqentry_thrd[9])
|
|
nid9 = 4'd8;
|
|
else
|
|
nid9 = 4'd9;
|
|
|
// Search the queue for the next entry on the same thread.
|
// Search the queue for the next entry on the same thread.
|
reg [`QBITS] nid;
|
reg [`QBITS] nid;
|
always @*
|
always @*
|
if (iqentry_thrd[idp1(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
|
if (iqentry_thrd[idp1(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
|
| Line 4532... |
Line 4602... |
nid = idp5(fcu_id);
|
nid = idp5(fcu_id);
|
else if (iqentry_thrd[idp6(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
|
else if (iqentry_thrd[idp6(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
|
nid = idp6(fcu_id);
|
nid = idp6(fcu_id);
|
else if (iqentry_thrd[idp7(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
|
else if (iqentry_thrd[idp7(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
|
nid = idp7(fcu_id);
|
nid = idp7(fcu_id);
|
|
else if (iqentry_thrd[idp8(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
|
|
nid = idp8(fcu_id);
|
|
else if (iqentry_thrd[idp9(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
|
|
nid = idp9(fcu_id);
|
else
|
else
|
nid = fcu_id;
|
nid = fcu_id;
|
|
|
|
|
assign nextqd[0] = iqentry_sn[nid0] > iqentry_sn[0] || iqentry_v[0];
|
assign nextqd[0] = iqentry_sn[nid0] > iqentry_sn[0] || iqentry_v[0];
|
| Line 4544... |
Line 4618... |
assign nextqd[3] = iqentry_sn[nid3] > iqentry_sn[3] || iqentry_v[3];
|
assign nextqd[3] = iqentry_sn[nid3] > iqentry_sn[3] || iqentry_v[3];
|
assign nextqd[4] = iqentry_sn[nid4] > iqentry_sn[4] || iqentry_v[4];
|
assign nextqd[4] = iqentry_sn[nid4] > iqentry_sn[4] || iqentry_v[4];
|
assign nextqd[5] = iqentry_sn[nid5] > iqentry_sn[5] || iqentry_v[5];
|
assign nextqd[5] = iqentry_sn[nid5] > iqentry_sn[5] || iqentry_v[5];
|
assign nextqd[6] = iqentry_sn[nid6] > iqentry_sn[6] || iqentry_v[6];
|
assign nextqd[6] = iqentry_sn[nid6] > iqentry_sn[6] || iqentry_v[6];
|
assign nextqd[7] = iqentry_sn[nid7] > iqentry_sn[7] || iqentry_v[7];
|
assign nextqd[7] = iqentry_sn[nid7] > iqentry_sn[7] || iqentry_v[7];
|
|
assign nextqd[8] = iqentry_sn[nid8] > iqentry_sn[8] || iqentry_v[8];
|
|
assign nextqd[9] = iqentry_sn[nid9] > iqentry_sn[9] || iqentry_v[9];
|
|
|
//assign nextqd = 8'hFF;
|
//assign nextqd = 8'hFF;
|
|
|
// Don't issue to the fcu until the following instruction is enqueued.
|
// Don't issue to the fcu until the following instruction is enqueued.
|
// However, if the queue is full then issue anyway. A branch miss will likely occur.
|
// However, if the queue is full then issue anyway. A branch miss will likely occur.
|
| Line 4693... |
Line 4769... |
memissue[ head1 ] = ~iqentry_stomp[head1] && iqentry_memready[ head1 ] // addr and data are valid
|
memissue[ head1 ] = ~iqentry_stomp[head1] && iqentry_memready[ head1 ] // addr and data are valid
|
&& issue_count < `NUM_MEM
|
&& issue_count < `NUM_MEM
|
// ... and no preceding instruction is ready to go
|
// ... and no preceding instruction is ready to go
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head0]
|
// ... and there is no address-overlap with any preceding instruction
|
// ... and there is no address-overlap with any preceding instruction
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0]
|
|| (iqentry_a1_v[head0] && iqentry_a1[head1][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
|| (iqentry_a1_v[head0] && (iqentry_a1[head1][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0])))
|
// ... if a release, any prior memory ops must be done before this one
|
// ... if a release, any prior memory ops must be done before this one
|
&& (iqentry_rl[head1] ? iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0] : 1'b1)
|
&& (iqentry_rl[head1] ? iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0] : 1'b1)
|
// ... if a preivous op has the aquire bit set
|
// ... if a preivous op has the aquire bit set
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
// ... and, if it is a SW, there is no chance of it being undone
|
// ... and, if it is a SW, there is no chance of it being undone
|
| Line 4711... |
Line 4787... |
// ... and no preceding instruction is ready to go
|
// ... and no preceding instruction is ready to go
|
&& issue_count < `NUM_MEM
|
&& issue_count < `NUM_MEM
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head1]
|
// ... and there is no address-overlap with any preceding instruction
|
// ... and there is no address-overlap with any preceding instruction
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0]
|
|| (iqentry_a1_v[head0] && iqentry_a1[head2][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
|| (iqentry_a1_v[head0] && (iqentry_a1[head2][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0])))
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1]) || iqentry_done[head1]
|
|| (iqentry_a1_v[head1] && iqentry_a1[head2][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
|| (iqentry_a1_v[head1] && (iqentry_a1[head2][AMSB:3] != iqentry_a1[head1][AMSB:3] || iqentry_out[head1] || iqentry_done[head1])))
|
// ... if a release, any prior memory ops must be done before this one
|
// ... if a release, any prior memory ops must be done before this one
|
&& (iqentry_rl[head2] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_rl[head2] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
: 1'b1)
|
: 1'b1)
|
// ... if a preivous op has the aquire bit set
|
// ... if a preivous op has the aquire bit set
|
| Line 4739... |
Line 4815... |
&& issue_count < `NUM_MEM
|
&& issue_count < `NUM_MEM
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head2]
|
//&& ~iqentry_memready[head2]
|
// ... and there is no address-overlap with any preceding instruction
|
// ... and there is no address-overlap with any preceding instruction
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0]
|
|| (iqentry_a1_v[head0] && iqentry_a1[head3][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
|| (iqentry_a1_v[head0] && (iqentry_a1[head3][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0])))
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1]) || iqentry_done[head1]
|
|| (iqentry_a1_v[head1] && iqentry_a1[head3][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
|| (iqentry_a1_v[head1] && (iqentry_a1[head3][AMSB:3] != iqentry_a1[head1][AMSB:3] || iqentry_out[head1] || iqentry_done[head1])))
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2]) || iqentry_done[head2]
|
|| (iqentry_a1_v[head2] && iqentry_a1[head3][AMSB:3] != iqentry_a1[head2][AMSB:3]))
|
|| (iqentry_a1_v[head2] && (iqentry_a1[head3][AMSB:3] != iqentry_a1[head2][AMSB:3] || iqentry_out[head2] || iqentry_done[head2])))
|
// ... if a release, any prior memory ops must be done before this one
|
// ... if a release, any prior memory ops must be done before this one
|
&& (iqentry_rl[head3] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_rl[head3] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
: 1'b1)
|
: 1'b1)
|
| Line 4781... |
Line 4857... |
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head0]
|
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head2]
|
//&& ~iqentry_memready[head2]
|
//&& ~iqentry_memready[head3]
|
//&& ~iqentry_memready[head3]
|
// ... and there is no address-overlap with any preceding instruction
|
// ... and there is no address-overlap with any preceding instruction
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0]
|
|| (iqentry_a1_v[head0] && iqentry_a1[head4][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
|| (iqentry_a1_v[head0] && (iqentry_a1[head4][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0])))
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1]) || iqentry_done[head1]
|
|| (iqentry_a1_v[head1] && iqentry_a1[head4][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
|| (iqentry_a1_v[head1] && (iqentry_a1[head4][AMSB:3] != iqentry_a1[head1][AMSB:3] || iqentry_out[head1] || iqentry_done[head1])))
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2]) || iqentry_done[head2]
|
|| (iqentry_a1_v[head2] && iqentry_a1[head4][AMSB:3] != iqentry_a1[head2][AMSB:3]))
|
|| (iqentry_a1_v[head2] && (iqentry_a1[head4][AMSB:3] != iqentry_a1[head2][AMSB:3] || iqentry_out[head2] || iqentry_done[head2])))
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3]) || iqentry_done[head3]
|
|| (iqentry_a1_v[head3] && iqentry_a1[head4][AMSB:3] != iqentry_a1[head3][AMSB:3]))
|
|| (iqentry_a1_v[head3] && (iqentry_a1[head4][AMSB:3] != iqentry_a1[head3][AMSB:3] || iqentry_out[head3] || iqentry_done[head3])))
|
// ... if a release, any prior memory ops must be done before this one
|
// ... if a release, any prior memory ops must be done before this one
|
&& (iqentry_rl[head4] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_rl[head4] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
| Line 4839... |
Line 4915... |
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head1]
|
//&& ~iqentry_memready[head2]
|
//&& ~iqentry_memready[head2]
|
//&& ~iqentry_memready[head3]
|
//&& ~iqentry_memready[head3]
|
//&& ~iqentry_memready[head4]
|
//&& ~iqentry_memready[head4]
|
// ... and there is no address-overlap with any preceding instruction
|
// ... and there is no address-overlap with any preceding instruction
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0]
|
|| (iqentry_a1_v[head0] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
|| (iqentry_a1_v[head0] && (iqentry_a1[head5][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0])))
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1]) || iqentry_done[head1]
|
|| (iqentry_a1_v[head1] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
|| (iqentry_a1_v[head1] && (iqentry_a1[head5][AMSB:3] != iqentry_a1[head1][AMSB:3] || iqentry_out[head1] || iqentry_done[head1])))
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2]) || iqentry_done[head2]
|
|| (iqentry_a1_v[head2] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head2][AMSB:3]))
|
|| (iqentry_a1_v[head2] && (iqentry_a1[head5][AMSB:3] != iqentry_a1[head2][AMSB:3] || iqentry_out[head2] || iqentry_done[head2])))
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3]) || iqentry_done[head3]
|
|| (iqentry_a1_v[head3] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head3][AMSB:3]))
|
|| (iqentry_a1_v[head3] && (iqentry_a1[head5][AMSB:3] != iqentry_a1[head3][AMSB:3] || iqentry_out[head3] || iqentry_done[head3])))
|
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4])
|
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4]) || iqentry_done[head4]
|
|| (iqentry_a1_v[head4] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head4][AMSB:3]))
|
|| (iqentry_a1_v[head4] && (iqentry_a1[head5][AMSB:3] != iqentry_a1[head4][AMSB:3] || iqentry_out[head4] || iqentry_done[head4])))
|
// ... if a release, any prior memory ops must be done before this one
|
// ... if a release, any prior memory ops must be done before this one
|
&& (iqentry_rl[head5] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_rl[head5] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
| Line 4916... |
Line 4992... |
//&& ~iqentry_memready[head2]
|
//&& ~iqentry_memready[head2]
|
//&& ~iqentry_memready[head3]
|
//&& ~iqentry_memready[head3]
|
//&& ~iqentry_memready[head4]
|
//&& ~iqentry_memready[head4]
|
//&& ~iqentry_memready[head5]
|
//&& ~iqentry_memready[head5]
|
// ... and there is no address-overlap with any preceding instruction
|
// ... and there is no address-overlap with any preceding instruction
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0]
|
|| (iqentry_a1_v[head0] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
|| (iqentry_a1_v[head0] && (iqentry_a1[head6][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0])))
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1]) || iqentry_done[head1]
|
|| (iqentry_a1_v[head1] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
|| (iqentry_a1_v[head1] && (iqentry_a1[head6][AMSB:3] != iqentry_a1[head1][AMSB:3] || iqentry_out[head1] || iqentry_done[head1])))
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2]) || iqentry_done[head2]
|
|| (iqentry_a1_v[head2] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head2][AMSB:3]))
|
|| (iqentry_a1_v[head2] && (iqentry_a1[head6][AMSB:3] != iqentry_a1[head2][AMSB:3] || iqentry_out[head2] || iqentry_done[head2])))
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3]) || iqentry_done[head3]
|
|| (iqentry_a1_v[head3] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head3][AMSB:3]))
|
|| (iqentry_a1_v[head3] && (iqentry_a1[head6][AMSB:3] != iqentry_a1[head3][AMSB:3] || iqentry_out[head3] || iqentry_done[head3])))
|
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4])
|
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4]) || iqentry_done[head4]
|
|| (iqentry_a1_v[head4] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head4][AMSB:3]))
|
|| (iqentry_a1_v[head4] && (iqentry_a1[head6][AMSB:3] != iqentry_a1[head4][AMSB:3] || iqentry_out[head4] || iqentry_done[head4])))
|
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5])
|
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5]) || iqentry_done[head5]
|
|| (iqentry_a1_v[head5] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head5][AMSB:3]))
|
|| (iqentry_a1_v[head5] && (iqentry_a1[head6][AMSB:3] != iqentry_a1[head5][AMSB:3] || iqentry_out[head5] || iqentry_done[head5])))
|
&& (iqentry_rl[head6] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_rl[head6] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
&& (iqentry_done[head4] || !iqentry_v[head4] || !iqentry_mem[head4])
|
&& (iqentry_done[head4] || !iqentry_v[head4] || !iqentry_mem[head4])
|
| Line 5011... |
Line 5087... |
//&& ~iqentry_memready[head3]
|
//&& ~iqentry_memready[head3]
|
//&& ~iqentry_memready[head4]
|
//&& ~iqentry_memready[head4]
|
//&& ~iqentry_memready[head5]
|
//&& ~iqentry_memready[head5]
|
//&& ~iqentry_memready[head6]
|
//&& ~iqentry_memready[head6]
|
// ... and there is no address-overlap with any preceding instruction
|
// ... and there is no address-overlap with any preceding instruction
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0]
|
|| (iqentry_a1_v[head0] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
|| (iqentry_a1_v[head0] && (iqentry_a1[head7][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0])))
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1]) || iqentry_done[head1]
|
|| (iqentry_a1_v[head1] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
|| (iqentry_a1_v[head1] && (iqentry_a1[head7][AMSB:3] != iqentry_a1[head1][AMSB:3] || iqentry_out[head1] || iqentry_done[head1])))
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2]) || iqentry_done[head2]
|
|| (iqentry_a1_v[head2] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head2][AMSB:3]))
|
|| (iqentry_a1_v[head2] && (iqentry_a1[head7][AMSB:3] != iqentry_a1[head2][AMSB:3] || iqentry_out[head2] || iqentry_done[head2])))
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3]) || iqentry_done[head3]
|
|| (iqentry_a1_v[head3] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head3][AMSB:3]))
|
|| (iqentry_a1_v[head3] && (iqentry_a1[head7][AMSB:3] != iqentry_a1[head3][AMSB:3] || iqentry_out[head3] || iqentry_done[head3])))
|
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4])
|
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4]) || iqentry_done[head4]
|
|| (iqentry_a1_v[head4] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head4][AMSB:3]))
|
|| (iqentry_a1_v[head4] && (iqentry_a1[head7][AMSB:3] != iqentry_a1[head4][AMSB:3] || iqentry_out[head4] || iqentry_done[head4])))
|
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5])
|
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5]) || iqentry_done[head5]
|
|| (iqentry_a1_v[head5] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head5][AMSB:3]))
|
|| (iqentry_a1_v[head5] && (iqentry_a1[head7][AMSB:3] != iqentry_a1[head5][AMSB:3] || iqentry_out[head5] || iqentry_done[head5])))
|
&& (!iqentry_mem[head6] || (iqentry_agen[head6] & iqentry_out[head6])
|
&& (!iqentry_mem[head6] || (iqentry_agen[head6] & iqentry_out[head6]) || iqentry_done[head6]
|
|| (iqentry_a1_v[head6] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head6][AMSB:3]))
|
|| (iqentry_a1_v[head6] && (iqentry_a1[head7][AMSB:3] != iqentry_a1[head6][AMSB:3] || iqentry_out[head6] || iqentry_done[head6])))
|
&& (iqentry_rl[head7] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_rl[head7] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
&& (iqentry_done[head4] || !iqentry_v[head4] || !iqentry_mem[head4])
|
&& (iqentry_done[head4] || !iqentry_v[head4] || !iqentry_mem[head4])
|
| Line 5178... |
Line 5254... |
stompedOnRets = stompedOnRets + 4'd1;
|
stompedOnRets = stompedOnRets + 4'd1;
|
if (iqentry_stomp[6] && iqentry_ret[6])
|
if (iqentry_stomp[6] && iqentry_ret[6])
|
stompedOnRets = stompedOnRets + 4'd1;
|
stompedOnRets = stompedOnRets + 4'd1;
|
if (iqentry_stomp[7] && iqentry_ret[7])
|
if (iqentry_stomp[7] && iqentry_ret[7])
|
stompedOnRets = stompedOnRets + 4'd1;
|
stompedOnRets = stompedOnRets + 4'd1;
|
|
if (iqentry_stomp[8] && iqentry_ret[8])
|
|
stompedOnRets = stompedOnRets + 4'd1;
|
|
if (iqentry_stomp[9] && iqentry_ret[9])
|
|
stompedOnRets = stompedOnRets + 4'd1;
|
end
|
end
|
|
|
reg id1_vi, id2_vi, id3_vi;
|
reg id1_vi, id2_vi, id3_vi;
|
wire [4:0] id1_ido, id2_ido, id3_ido;
|
wire [4:0] id1_ido, id2_ido, id3_ido;
|
wire id1_vo, id2_vo, id3_vo;
|
wire id1_vo, id2_vo, id3_vo;
|
| Line 5354... |
Line 5434... |
.a(fpu1_argA),
|
.a(fpu1_argA),
|
.b(fpu1_argB),
|
.b(fpu1_argB),
|
.imm(fpu1_argI),
|
.imm(fpu1_argI),
|
.o(fpu1_bus),
|
.o(fpu1_bus),
|
.csr_i(),
|
.csr_i(),
|
.status(fpu_status),
|
.status(fpu1_status),
|
.exception(),
|
.exception(),
|
.done(fpu1_done)
|
.done(fpu1_done)
|
);
|
);
|
end
|
end
|
if (`NUM_FPU > 1) begin
|
if (`NUM_FPU > 1) begin
|
| Line 5381... |
Line 5461... |
.a(fpu2_argA),
|
.a(fpu2_argA),
|
.b(fpu2_argB),
|
.b(fpu2_argB),
|
.imm(fpu2_argI),
|
.imm(fpu2_argI),
|
.o(fpu2_bus),
|
.o(fpu2_bus),
|
.csr_i(),
|
.csr_i(),
|
.status(fpu_status),
|
.status(fpu2_status),
|
.exception(),
|
.exception(),
|
.done(fpu2_done)
|
.done(fpu2_done)
|
);
|
);
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
assign fpu_exc = (fpu1_available|fpu2_available) ?
|
assign fpu1_exc = (fpu1_available) ?
|
((|fpu1_status[15:0] || |fpu2_status[15:0]) ? `FLT_FLT : `FLT_NONE) : `FLT_UNIMP;
|
((|fpu1_status[15:0]) ? `FLT_FLT : `FLT_NONE) : `FLT_UNIMP;
|
|
assign fpu2_exc = (fpu2_available) ?
|
|
((|fpu2_status[15:0]) ? `FLT_FLT : `FLT_NONE) : `FLT_UNIMP;
|
|
|
assign alu0_v = alu0_dataready,
|
assign alu0_v = alu0_dataready,
|
alu1_v = alu1_dataready;
|
alu1_v = alu1_dataready;
|
assign alu0_id = alu0_sourceid,
|
assign alu0_id = alu0_sourceid,
|
alu1_id = alu1_sourceid;
|
alu1_id = alu1_sourceid;
|
| Line 5499... |
Line 5581... |
if (fcu_instr[`INSTRUCTION_OP] == `REX && (im < ~ol) && fcu_v)
|
if (fcu_instr[`INSTRUCTION_OP] == `REX && (im < ~ol) && fcu_v)
|
`endif
|
`endif
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
else if (fcu_ret_miss)
|
else if (fcu_ret_miss)
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
else if (fcu_branch && fcu_v && (((fcu_takb && (~fcu_bt || (fcu_misspc != iqentry_pc[nid]))) ||
|
else if (fcu_branch && fcu_v && (((fcu_takb && (fcu_misspc != iqentry_pc[nid])) ||
|
(~fcu_takb && ( fcu_bt || (fcu_pc + 32'd4 != iqentry_pc[nid])))) || iqentry_v[nid]))
|
(~fcu_takb && (fcu_pc + fcu_insln != iqentry_pc[nid])))))// || iqentry_v[nid]))
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
else if (fcu_jal_miss)
|
else if (fcu_jal_miss)
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
else if (fcu_instr[`INSTRUCTION_OP] == `CHK && ~fcu_takb && fcu_v)
|
else if (fcu_instr[`INSTRUCTION_OP] == `CHK && ~fcu_takb && fcu_v)
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
| Line 5570... |
Line 5652... |
iqentry_memopsvalid[2] = (iqentry_mem[2] & iqentry_a2_v[2] & iqentry_agen[2]),
|
iqentry_memopsvalid[2] = (iqentry_mem[2] & iqentry_a2_v[2] & iqentry_agen[2]),
|
iqentry_memopsvalid[3] = (iqentry_mem[3] & iqentry_a2_v[3] & iqentry_agen[3]),
|
iqentry_memopsvalid[3] = (iqentry_mem[3] & iqentry_a2_v[3] & iqentry_agen[3]),
|
iqentry_memopsvalid[4] = (iqentry_mem[4] & iqentry_a2_v[4] & iqentry_agen[4]),
|
iqentry_memopsvalid[4] = (iqentry_mem[4] & iqentry_a2_v[4] & iqentry_agen[4]),
|
iqentry_memopsvalid[5] = (iqentry_mem[5] & iqentry_a2_v[5] & iqentry_agen[5]),
|
iqentry_memopsvalid[5] = (iqentry_mem[5] & iqentry_a2_v[5] & iqentry_agen[5]),
|
iqentry_memopsvalid[6] = (iqentry_mem[6] & iqentry_a2_v[6] & iqentry_agen[6]),
|
iqentry_memopsvalid[6] = (iqentry_mem[6] & iqentry_a2_v[6] & iqentry_agen[6]),
|
iqentry_memopsvalid[7] = (iqentry_mem[7] & iqentry_a2_v[7] & iqentry_agen[7]);
|
iqentry_memopsvalid[7] = (iqentry_mem[7] & iqentry_a2_v[7] & iqentry_agen[7]),
|
|
iqentry_memopsvalid[8] = (iqentry_mem[8] & iqentry_a2_v[8] & iqentry_agen[8]),
|
|
iqentry_memopsvalid[9] = (iqentry_mem[9] & iqentry_a2_v[9] & iqentry_agen[9])
|
|
;
|
|
|
assign iqentry_memready[0] = (iqentry_v[0] & iqentry_memopsvalid[0] & ~iqentry_memissue[0] & ~iqentry_done[0] & ~iqentry_out[0] & ~iqentry_stomp[0]),
|
assign iqentry_memready[0] = (iqentry_v[0] & iqentry_memopsvalid[0] & ~iqentry_memissue[0] & ~iqentry_done[0] & ~iqentry_out[0] & ~iqentry_stomp[0]),
|
iqentry_memready[1] = (iqentry_v[1] & iqentry_memopsvalid[1] & ~iqentry_memissue[1] & ~iqentry_done[1] & ~iqentry_out[1] & ~iqentry_stomp[1]),
|
iqentry_memready[1] = (iqentry_v[1] & iqentry_memopsvalid[1] & ~iqentry_memissue[1] & ~iqentry_done[1] & ~iqentry_out[1] & ~iqentry_stomp[1]),
|
iqentry_memready[2] = (iqentry_v[2] & iqentry_memopsvalid[2] & ~iqentry_memissue[2] & ~iqentry_done[2] & ~iqentry_out[2] & ~iqentry_stomp[2]),
|
iqentry_memready[2] = (iqentry_v[2] & iqentry_memopsvalid[2] & ~iqentry_memissue[2] & ~iqentry_done[2] & ~iqentry_out[2] & ~iqentry_stomp[2]),
|
iqentry_memready[3] = (iqentry_v[3] & iqentry_memopsvalid[3] & ~iqentry_memissue[3] & ~iqentry_done[3] & ~iqentry_out[3] & ~iqentry_stomp[3]),
|
iqentry_memready[3] = (iqentry_v[3] & iqentry_memopsvalid[3] & ~iqentry_memissue[3] & ~iqentry_done[3] & ~iqentry_out[3] & ~iqentry_stomp[3]),
|
iqentry_memready[4] = (iqentry_v[4] & iqentry_memopsvalid[4] & ~iqentry_memissue[4] & ~iqentry_done[4] & ~iqentry_out[4] & ~iqentry_stomp[4]),
|
iqentry_memready[4] = (iqentry_v[4] & iqentry_memopsvalid[4] & ~iqentry_memissue[4] & ~iqentry_done[4] & ~iqentry_out[4] & ~iqentry_stomp[4]),
|
iqentry_memready[5] = (iqentry_v[5] & iqentry_memopsvalid[5] & ~iqentry_memissue[5] & ~iqentry_done[5] & ~iqentry_out[5] & ~iqentry_stomp[5]),
|
iqentry_memready[5] = (iqentry_v[5] & iqentry_memopsvalid[5] & ~iqentry_memissue[5] & ~iqentry_done[5] & ~iqentry_out[5] & ~iqentry_stomp[5]),
|
iqentry_memready[6] = (iqentry_v[6] & iqentry_memopsvalid[6] & ~iqentry_memissue[6] & ~iqentry_done[6] & ~iqentry_out[6] & ~iqentry_stomp[6]),
|
iqentry_memready[6] = (iqentry_v[6] & iqentry_memopsvalid[6] & ~iqentry_memissue[6] & ~iqentry_done[6] & ~iqentry_out[6] & ~iqentry_stomp[6]),
|
iqentry_memready[7] = (iqentry_v[7] & iqentry_memopsvalid[7] & ~iqentry_memissue[7] & ~iqentry_done[7] & ~iqentry_out[7] & ~iqentry_stomp[7]);
|
iqentry_memready[7] = (iqentry_v[7] & iqentry_memopsvalid[7] & ~iqentry_memissue[7] & ~iqentry_done[7] & ~iqentry_out[7] & ~iqentry_stomp[7]),
|
|
iqentry_memready[8] = (iqentry_v[8] & iqentry_memopsvalid[8] & ~iqentry_memissue[8] & ~iqentry_done[8] & ~iqentry_out[8] & ~iqentry_stomp[8]),
|
|
iqentry_memready[9] = (iqentry_v[9] & iqentry_memopsvalid[9] & ~iqentry_memissue[9] & ~iqentry_done[9] & ~iqentry_out[9] & ~iqentry_stomp[9])
|
|
;
|
|
|
assign outstanding_stores = (dram0 && dram0_store) ||
|
assign outstanding_stores = (dram0 && dram0_store) ||
|
(dram1 && dram1_store) ||
|
(dram1 && dram1_store) ||
|
(dram2 && dram2_store);
|
(dram2 && dram2_store);
|
|
|
| Line 5710... |
Line 5798... |
end
|
end
|
end
|
end
|
// If an irq is active during a vector instruction fetch, claim the vector instruction
|
// If an irq is active during a vector instruction fetch, claim the vector instruction
|
// is finished queueing even though it may not be. It'll pick up where it left off after
|
// is finished queueing even though it may not be. It'll pick up where it left off after
|
// the exception is processed.
|
// the exception is processed.
|
if (hirq) begin
|
if (freezePC) begin
|
if (IsVector(fetchbuf0_instr) && IsVector(fetchbuf1_instr) && vechain) begin
|
if (IsVector(fetchbuf0_instr) && IsVector(fetchbuf1_instr) && vechain) begin
|
queued1 <= TRUE;
|
queued1 <= TRUE;
|
queued2 <= TRUE;
|
queued2 <= TRUE;
|
end
|
end
|
else if (IsVector(fetchbuf0_instr)) begin
|
else if (IsVector(fetchbuf0_instr)) begin
|
| Line 5738... |
Line 5826... |
end
|
end
|
if (iqentry_v[tail1]==`INV) begin
|
if (iqentry_v[tail1]==`INV) begin
|
canq2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && SUP_VECTOR;
|
canq2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && SUP_VECTOR;
|
vqueued2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && !vechain;
|
vqueued2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && !vechain;
|
end
|
end
|
if (hirq) begin
|
if (freezePC) begin
|
if (IsVector(fetchbuf0_instr)) begin
|
if (IsVector(fetchbuf0_instr)) begin
|
queued1 <= TRUE;
|
queued1 <= TRUE;
|
if (vqe0 < vl-2)
|
if (vqe0 < vl-2)
|
queued2 <= iqentry_v[tail1]==`INV;
|
queued2 <= iqentry_v[tail1]==`INV;
|
end
|
end
|
| Line 5760... |
Line 5848... |
end
|
end
|
if (iqentry_v[tail1]==`INV) begin
|
if (iqentry_v[tail1]==`INV) begin
|
canq2 <= IsVector(fetchbuf1_instr) && vqe1 < vl-2 && SUP_VECTOR;
|
canq2 <= IsVector(fetchbuf1_instr) && vqe1 < vl-2 && SUP_VECTOR;
|
vqueued2 <= IsVector(fetchbuf1_instr) && vqe1 < vl-2;
|
vqueued2 <= IsVector(fetchbuf1_instr) && vqe1 < vl-2;
|
end
|
end
|
if (hirq) begin
|
if (freezePC) begin
|
if (IsVector(fetchbuf1_instr)) begin
|
if (IsVector(fetchbuf1_instr)) begin
|
queued1 <= TRUE;
|
queued1 <= TRUE;
|
if (vqe1 < vl-2)
|
if (vqe1 < vl-2)
|
queued2 <= iqentry_v[tail1]==`INV;
|
queued2 <= iqentry_v[tail1]==`INV;
|
end
|
end
|
| Line 5881... |
Line 5969... |
iqentry_fpu1_issue[n] <= FALSE;
|
iqentry_fpu1_issue[n] <= FALSE;
|
iqentry_fpu2_issue[n] <= FALSE;
|
iqentry_fpu2_issue[n] <= FALSE;
|
iqentry_fsync[n] <= FALSE;
|
iqentry_fsync[n] <= FALSE;
|
iqentry_fc[n] <= FALSE;
|
iqentry_fc[n] <= FALSE;
|
iqentry_fcu_issue[n] <= FALSE;
|
iqentry_fcu_issue[n] <= FALSE;
|
|
iqentry_takb[n] <= FALSE;
|
iqentry_jmp[n] <= FALSE;
|
iqentry_jmp[n] <= FALSE;
|
iqentry_jal[n] <= FALSE;
|
iqentry_jal[n] <= FALSE;
|
iqentry_ret[n] <= FALSE;
|
iqentry_ret[n] <= FALSE;
|
iqentry_brk[n] <= FALSE;
|
iqentry_brk[n] <= FALSE;
|
iqentry_irq[n] <= FALSE;
|
iqentry_irq[n] <= FALSE;
|
| Line 5944... |
Line 6033... |
head3 <= 3;
|
head3 <= 3;
|
head4 <= 4;
|
head4 <= 4;
|
head5 <= 5;
|
head5 <= 5;
|
head6 <= 6;
|
head6 <= 6;
|
head7 <= 7;
|
head7 <= 7;
|
|
head8 <= 8;
|
|
head9 <= 9;
|
panic = `PANIC_NONE;
|
panic = `PANIC_NONE;
|
alu0_dataready <= 0;
|
alu0_dataready <= 0;
|
alu1_dataready <= 0;
|
alu1_dataready <= 0;
|
alu0_sourceid <= 5'd0;
|
alu0_sourceid <= 5'd0;
|
alu1_sourceid <= 5'd0;
|
alu1_sourceid <= 5'd0;
|
| Line 6000... |
Line 6091... |
cr0[13:8] <= 6'd0; // select register set #0
|
cr0[13:8] <= 6'd0; // select register set #0
|
cr0[30] <= TRUE; // enable data caching
|
cr0[30] <= TRUE; // enable data caching
|
cr0[32] <= TRUE; // enable branch predictor
|
cr0[32] <= TRUE; // enable branch predictor
|
cr0[16] <= 1'b0; // disable SMT
|
cr0[16] <= 1'b0; // disable SMT
|
cr0[17] <= 1'b0; // sequence number reset = 1
|
cr0[17] <= 1'b0; // sequence number reset = 1
|
|
cr0[34] <= FALSE; // write buffer merging enable
|
pcr <= 32'd0;
|
pcr <= 32'd0;
|
pcr2 <= 64'd0;
|
pcr2 <= 64'd0;
|
for (n = 0; n < PREGS; n = n + 1)
|
for (n = 0; n < PREGS; n = n + 1)
|
rf_v[n] <= `VAL;
|
rf_v[n] <= `VAL;
|
tgtq <= FALSE;
|
tgtq <= FALSE;
|
| Line 6070... |
Line 6162... |
id2_vi <= `INV;
|
id2_vi <= `INV;
|
if (`NUM_IDU > 2)
|
if (`NUM_IDU > 2)
|
id3_vi <= `INV;
|
id3_vi <= `INV;
|
if (iqentry_v[nid] && iqentry_sn[nid] > iqentry_sn[fcu_id[`QBITS]])
|
if (iqentry_v[nid] && iqentry_sn[nid] > iqentry_sn[fcu_id[`QBITS]])
|
fcu_dataready <= `INV;
|
fcu_dataready <= `INV;
|
|
wb_shift <= FALSE;
|
ld_time <= {ld_time[4:0],1'b0};
|
ld_time <= {ld_time[4:0],1'b0};
|
wc_times <= wc_time;
|
wc_times <= wc_time;
|
rf_vra0 <= regIsValid[Ra0s];
|
rf_vra0 <= regIsValid[Ra0s];
|
rf_vra1 <= regIsValid[Ra1s];
|
rf_vra1 <= regIsValid[Ra1s];
|
if (vqe0 >= vl) begin
|
if (vqe0 >= vl) begin
|
| Line 6123... |
Line 6216... |
if (n < 128)
|
if (n < 128)
|
rf_v[n] <= `VAL;
|
rf_v[n] <= `VAL;
|
end
|
end
|
end
|
end
|
|
|
if (|iqentry_0_latestID) if (iqentry_thrd[0]==branchmiss_thrd) rf_source[ {iqentry_tgt[0][7:0]} ] <= { 1'b0, iqentry_mem[0], 3'd0 };
|
if (|iqentry_0_latestID) if (iqentry_thrd[0]==branchmiss_thrd) rf_source[ {iqentry_tgt[0][7:0]} ] <= { 1'b0, iqentry_mem[0], 4'd0 };
|
if (|iqentry_1_latestID) if (iqentry_thrd[1]==branchmiss_thrd) rf_source[ {iqentry_tgt[1][7:0]} ] <= { 1'b0, iqentry_mem[1], 3'd1 };
|
if (|iqentry_1_latestID) if (iqentry_thrd[1]==branchmiss_thrd) rf_source[ {iqentry_tgt[1][7:0]} ] <= { 1'b0, iqentry_mem[1], 4'd1 };
|
if (|iqentry_2_latestID) if (iqentry_thrd[2]==branchmiss_thrd) rf_source[ {iqentry_tgt[2][7:0]} ] <= { 1'b0, iqentry_mem[2], 3'd2 };
|
if (|iqentry_2_latestID) if (iqentry_thrd[2]==branchmiss_thrd) rf_source[ {iqentry_tgt[2][7:0]} ] <= { 1'b0, iqentry_mem[2], 4'd2 };
|
if (|iqentry_3_latestID) if (iqentry_thrd[3]==branchmiss_thrd) rf_source[ {iqentry_tgt[3][7:0]} ] <= { 1'b0, iqentry_mem[3], 3'd3 };
|
if (|iqentry_3_latestID) if (iqentry_thrd[3]==branchmiss_thrd) rf_source[ {iqentry_tgt[3][7:0]} ] <= { 1'b0, iqentry_mem[3], 4'd3 };
|
if (|iqentry_4_latestID) if (iqentry_thrd[4]==branchmiss_thrd) rf_source[ {iqentry_tgt[4][7:0]} ] <= { 1'b0, iqentry_mem[4], 3'd4 };
|
if (|iqentry_4_latestID) if (iqentry_thrd[4]==branchmiss_thrd) rf_source[ {iqentry_tgt[4][7:0]} ] <= { 1'b0, iqentry_mem[4], 4'd4 };
|
if (|iqentry_5_latestID) if (iqentry_thrd[5]==branchmiss_thrd) rf_source[ {iqentry_tgt[5][7:0]} ] <= { 1'b0, iqentry_mem[5], 3'd5 };
|
if (|iqentry_5_latestID) if (iqentry_thrd[5]==branchmiss_thrd) rf_source[ {iqentry_tgt[5][7:0]} ] <= { 1'b0, iqentry_mem[5], 4'd5 };
|
if (|iqentry_6_latestID) if (iqentry_thrd[6]==branchmiss_thrd) rf_source[ {iqentry_tgt[6][7:0]} ] <= { 1'b0, iqentry_mem[6], 3'd6 };
|
if (|iqentry_6_latestID) if (iqentry_thrd[6]==branchmiss_thrd) rf_source[ {iqentry_tgt[6][7:0]} ] <= { 1'b0, iqentry_mem[6], 4'd6 };
|
if (|iqentry_7_latestID) if (iqentry_thrd[7]==branchmiss_thrd) rf_source[ {iqentry_tgt[7][7:0]} ] <= { 1'b0, iqentry_mem[7], 3'd7 };
|
if (|iqentry_7_latestID) if (iqentry_thrd[7]==branchmiss_thrd) rf_source[ {iqentry_tgt[7][7:0]} ] <= { 1'b0, iqentry_mem[7], 4'd7 };
|
|
if (|iqentry_8_latestID) if (iqentry_thrd[8]==branchmiss_thrd) rf_source[ {iqentry_tgt[8][7:0]} ] <= { 1'b0, iqentry_mem[8], 4'd8 };
|
|
if (|iqentry_9_latestID) if (iqentry_thrd[9]==branchmiss_thrd) rf_source[ {iqentry_tgt[9][7:0]} ] <= { 1'b0, iqentry_mem[9], 4'd9 };
|
|
|
end
|
end
|
|
|
// The source for the register file data might have changed since it was
|
// The source for the register file data might have changed since it was
|
// placed on the commit bus. So it's needed to check that the source is
|
// placed on the commit bus. So it's needed to check that the source is
|
| Line 6803... |
Line 6898... |
// Update branch taken indicator.
|
// Update branch taken indicator.
|
if (fcu_jal || fcu_ret || fcu_brk || fcu_rti) begin
|
if (fcu_jal || fcu_ret || fcu_brk || fcu_rti) begin
|
iqentry_bt[ fcu_id[`QBITS] ] <= `VAL;
|
iqentry_bt[ fcu_id[`QBITS] ] <= `VAL;
|
end
|
end
|
// Branch target is only updated for branch-to-register
|
// Branch target is only updated for branch-to-register
|
// else if (fcu_branch) begin
|
else if (fcu_branch) begin
|
// iqentry_bt[ fcu_id[`QBITS] ] <= fcu_takb;
|
iqentry_takb[ fcu_id[`QBITS] ] <= fcu_takb;
|
// end
|
end
|
iqentry_out [ fcu_id[`QBITS] ] <= `INV;
|
iqentry_out [ fcu_id[`QBITS] ] <= `INV;
|
//iqentry_agen[ fcu_id[`QBITS] ] <= `VAL;//!IsRet(fcu_instr);
|
//iqentry_agen[ fcu_id[`QBITS] ] <= `VAL;//!IsRet(fcu_instr);
|
fcu_dataready <= `VAL;
|
fcu_dataready <= `VAL;
|
//fcu_dataready <= fcu_branchmiss || !iqentry_agen[ fcu_id[`QBITS] ] || !(iqentry_mem[ fcu_id[`QBITS] ] && IsLoad(iqentry_instr[fcu_id[`QBITS]]));
|
//fcu_dataready <= fcu_branchmiss || !iqentry_agen[ fcu_id[`QBITS] ] || !(iqentry_mem[ fcu_id[`QBITS] ] && IsLoad(iqentry_instr[fcu_id[`QBITS]]));
|
//fcu_instr[`INSTRUCTION_OP] <= fcu_branchmiss|| (!IsMem(fcu_instr) && !IsWait(fcu_instr))? `NOP : fcu_instr[`INSTRUCTION_OP]; // to clear branchmiss
|
//fcu_instr[`INSTRUCTION_OP] <= fcu_branchmiss|| (!IsMem(fcu_instr) && !IsWait(fcu_instr))? `NOP : fcu_instr[`INSTRUCTION_OP]; // to clear branchmiss
|
| Line 7741... |
Line 7836... |
end
|
end
|
wb_v[`WB_DEPTH-1] <= `INV;
|
wb_v[`WB_DEPTH-1] <= `INV;
|
wb_rmw[`WB_DEPTH-1] <= `FALSE;
|
wb_rmw[`WB_DEPTH-1] <= `FALSE;
|
end
|
end
|
|
|
// if (|wb_v)
|
|
// ;
|
|
// else
|
|
`endif
|
`endif
|
if (~|wb_v && mem1_available && dram0==`DRAMSLOT_BUSY && dram0_rmw) begin
|
if (~|wb_v && mem1_available && dram0==`DRAMSLOT_BUSY && dram0_rmw) begin
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
if (dbg_smatch0|dbg_lmatch0) begin
|
if (dbg_smatch0|dbg_lmatch0) begin
|
dramA_v <= `TRUE;
|
dramA_v <= `TRUE;
|
| Line 8427... |
Line 8519... |
end
|
end
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
`ifndef SUPPORT_SMT
|
else if (!thread_en) begin // if branchmiss
|
else begin // if branchmiss
|
|
if (iqentry_stomp[0] & ~iqentry_stomp[7]) begin
|
if (iqentry_stomp[0] & ~iqentry_stomp[7]) begin
|
tail0 <= 3'd0;
|
tail0 <= 4'd0;
|
tail1 <= 3'd1;
|
tail1 <= 4'd1;
|
end
|
end
|
else if (iqentry_stomp[1] & ~iqentry_stomp[0]) begin
|
else if (iqentry_stomp[1] & ~iqentry_stomp[0]) begin
|
tail0 <= 3'd1;
|
tail0 <= 4'd1;
|
tail1 <= 3'd2;
|
tail1 <= 4'd2;
|
end
|
end
|
else if (iqentry_stomp[2] & ~iqentry_stomp[1]) begin
|
else if (iqentry_stomp[2] & ~iqentry_stomp[1]) begin
|
tail0 <= 3'd2;
|
tail0 <= 4'd2;
|
tail1 <= 3'd3;
|
tail1 <= 4'd3;
|
end
|
end
|
else if (iqentry_stomp[3] & ~iqentry_stomp[2]) begin
|
else if (iqentry_stomp[3] & ~iqentry_stomp[2]) begin
|
tail0 <= 3'd3;
|
tail0 <= 4'd3;
|
tail1 <= 3'd4;
|
tail1 <= 4'd4;
|
end
|
end
|
else if (iqentry_stomp[4] & ~iqentry_stomp[3]) begin
|
else if (iqentry_stomp[4] & ~iqentry_stomp[3]) begin
|
tail0 <= 3'd4;
|
tail0 <= 4'd4;
|
tail1 <= 3'd5;
|
tail1 <= 4'd5;
|
end
|
end
|
else if (iqentry_stomp[5] & ~iqentry_stomp[4]) begin
|
else if (iqentry_stomp[5] & ~iqentry_stomp[4]) begin
|
tail0 <= 3'd5;
|
tail0 <= 4'd5;
|
tail1 <= 3'd6;
|
tail1 <= 4'd6;
|
end
|
end
|
else if (iqentry_stomp[6] & ~iqentry_stomp[5]) begin
|
else if (iqentry_stomp[6] & ~iqentry_stomp[5]) begin
|
tail0 <= 3'd6;
|
tail0 <= 4'd6;
|
tail1 <= 3'd7;
|
tail1 <= 4'd7;
|
end
|
end
|
else if (iqentry_stomp[7] & ~iqentry_stomp[6]) begin
|
else if (iqentry_stomp[7] & ~iqentry_stomp[6]) begin
|
tail0 <= 3'd7;
|
tail0 <= 4'd7;
|
tail1 <= 3'd0;
|
tail1 <= 4'd8;
|
|
end
|
|
else if (iqentry_stomp[8] & ~iqentry_stomp[7]) begin
|
|
tail0 <= 4'd8;
|
|
tail1 <= 4'd9;
|
|
end
|
|
else if (iqentry_stomp[9] & ~iqentry_stomp[8]) begin
|
|
tail0 <= 4'd9;
|
|
tail1 <= 4'd0;
|
end
|
end
|
// otherwise, it is the last instruction in the queue that has been mispredicted ... do nothing
|
// otherwise, it is the last instruction in the queue that has been mispredicted ... do nothing
|
end
|
end
|
`endif
|
|
|
|
/*
|
/*
|
if (pebm)
|
if (pebm)
|
seq_num <= seq_num + 5'd3;
|
seq_num <= seq_num + 5'd3;
|
else if (queued2)
|
else if (queued2)
|
| Line 8814... |
Line 8912... |
input [7:0] sel;
|
input [7:0] sel;
|
input [1:0] ol;
|
input [1:0] ol;
|
input [`ABITS] addr;
|
input [`ABITS] addr;
|
input [63:0] data;
|
input [63:0] data;
|
begin
|
begin
|
if (wbptr > 0 && wb_addr[wbptr-1][AMSB:3]==addr[AMSB:3] && wb_ol[wbptr-1]==ol && wb_rmw[wbptr-1]==rmw) begin
|
if (wbm && wbptr > 1 && wb_addr[wbptr-1][AMSB:3]==addr[AMSB:3]
|
|
&& wb_ol[wbptr-1]==ol && wb_rmw[wbptr-1]==rmw && wb_v[wbptr-1]) begin
|
|
// The write buffer is always shifted during the bus IDLE state. That means
|
|
// the data is out of place by a slot. The slot the data is moved from is
|
|
// invalidated.
|
|
wb_v[wbptr-2] <= `INV;
|
|
wb_v[wbptr-1] <= wb_en;
|
|
wb_id[wbptr-1] <= wb_id[wbptr-1] | (16'd1 << id);
|
|
wb_rmw[wbptr-1] <= rmw;
|
|
wb_ol[wbptr-1] <= ol;
|
wb_sel[wbptr-1] <= wb_sel[wbptr-1] | sel;
|
wb_sel[wbptr-1] <= wb_sel[wbptr-1] | sel;
|
|
wb_addr[wbptr-1] <= wb_addr[wbptr-1];
|
|
wb_data[wbptr-1] <= wb_data[wbptr-1];
|
if (sel[0]) wb_data[wbptr-1][ 7: 0] <= data[ 7: 0];
|
if (sel[0]) wb_data[wbptr-1][ 7: 0] <= data[ 7: 0];
|
if (sel[1]) wb_data[wbptr-1][15: 8] <= data[15: 8];
|
if (sel[1]) wb_data[wbptr-1][15: 8] <= data[15: 8];
|
if (sel[2]) wb_data[wbptr-1][23:16] <= data[23:16];
|
if (sel[2]) wb_data[wbptr-1][23:16] <= data[23:16];
|
if (sel[3]) wb_data[wbptr-1][31:24] <= data[31:24];
|
if (sel[3]) wb_data[wbptr-1][31:24] <= data[31:24];
|
if (sel[4]) wb_data[wbptr-1][39:32] <= data[39:32];
|
if (sel[4]) wb_data[wbptr-1][39:32] <= data[39:32];
|
if (sel[5]) wb_data[wbptr-1][47:40] <= data[47:40];
|
if (sel[5]) wb_data[wbptr-1][47:40] <= data[47:40];
|
if (sel[6]) wb_data[wbptr-1][55:48] <= data[55:48];
|
if (sel[6]) wb_data[wbptr-1][55:48] <= data[55:48];
|
if (sel[7]) wb_data[wbptr-1][63:56] <= data[63:56];
|
if (sel[7]) wb_data[wbptr-1][63:56] <= data[63:56];
|
wb_id[wbptr-1] <= wb_id[wbptr-1] | (16'd1 << id);
|
|
wb_merges <= wb_merges + 32'd1;
|
wb_merges <= wb_merges + 32'd1;
|
end
|
end
|
else begin
|
else begin
|
wb_v[wbptr] <= wb_en;
|
wb_v[wbptr] <= wb_en;
|
wb_id[wbptr] <= (16'd1 << id);
|
wb_id[wbptr] <= (16'd1 << id);
|
| Line 8838... |
Line 8946... |
wb_addr[wbptr] <= {addr[AMSB:3],3'b0};
|
wb_addr[wbptr] <= {addr[AMSB:3],3'b0};
|
wb_data[wbptr] <= data;
|
wb_data[wbptr] <= data;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
// Increment the head pointers
|
// Increment the head pointers
|
// Also increments the instruction counter
|
// Also increments the instruction counter
|
// Used when instructions are committed.
|
// Used when instructions are committed.
|
// Also clear any outstanding state bits that foul things up.
|
// Also clear any outstanding state bits that foul things up.
|
//
|
//
|
task head_inc;
|
task head_inc;
|
input [`QBITS] amt;
|
input [`QBITS] amt;
|
begin
|
begin
|
head0 <= head0 + amt;
|
head0 <= (head0 + amt) % QENTRIES;
|
head1 <= head1 + amt;
|
head1 <= (head1 + amt) % QENTRIES;
|
head2 <= head2 + amt;
|
head2 <= (head2 + amt) % QENTRIES;
|
head3 <= head3 + amt;
|
head3 <= (head3 + amt) % QENTRIES;
|
head4 <= head4 + amt;
|
head4 <= (head4 + amt) % QENTRIES;
|
head5 <= head5 + amt;
|
head5 <= (head5 + amt) % QENTRIES;
|
head6 <= head6 + amt;
|
head6 <= (head6 + amt) % QENTRIES;
|
head7 <= head7 + amt;
|
head7 <= (head7 + amt) % QENTRIES;
|
|
head8 <= (head8 + amt) % QENTRIES;
|
|
head9 <= (head9 + amt) % QENTRIES;
|
I <= I + amt;
|
I <= I + amt;
|
if (amt==3'd3) begin
|
if (amt==3'd3) begin
|
iqentry_agen[head0] <= `INV;
|
iqentry_agen[head0] <= `INV;
|
iqentry_agen[head1] <= `INV;
|
iqentry_agen[head1] <= `INV;
|
iqentry_agen[head2] <= `INV;
|
iqentry_agen[head2] <= `INV;
|
| Line 9442... |
Line 9553... |
`CSR_DBCTRL: dat <= dbg_ctrl;
|
`CSR_DBCTRL: dat <= dbg_ctrl;
|
`CSR_DBSTAT: dat <= dbg_stat;
|
`CSR_DBSTAT: dat <= dbg_stat;
|
`endif
|
`endif
|
`CSR_CAS: dat <= cas;
|
`CSR_CAS: dat <= cas;
|
`CSR_TVEC: dat <= tvec[csrno[2:0]];
|
`CSR_TVEC: dat <= tvec[csrno[2:0]];
|
`CSR_BADADR: dat <= badaddr[{thread,csrno[13:11]}];
|
`CSR_BADADR: dat <= badaddr[{thread,csrno[11:10]}];
|
`CSR_CAUSE: dat <= {48'd0,cause[{thread,csrno[13:11]}]};
|
`CSR_CAUSE: dat <= {48'd0,cause[{thread,csrno[11:10]}]};
|
`ifdef SUPPORT_SMT
|
`ifdef SUPPORT_SMT
|
`CSR_IM_STACK: dat <= im_stack[thread];
|
`CSR_IM_STACK: dat <= im_stack[thread];
|
`CSR_OL_STACK: dat <= ol_stack[thread];
|
`CSR_OL_STACK: dat <= ol_stack[thread];
|
`CSR_PL_STACK: dat <= pl_stack[thread];
|
`CSR_PL_STACK: dat <= pl_stack[thread];
|
`CSR_RS_STACK: dat <= rs_stack[thread];
|
`CSR_RS_STACK: dat <= rs_stack[thread];
|
| Line 9541... |
Line 9652... |
`CSR_SEMA: sema <= dat;
|
`CSR_SEMA: sema <= dat;
|
`CSR_SBL: sbl <= dat[31:0];
|
`CSR_SBL: sbl <= dat[31:0];
|
`CSR_SBU: sbu <= dat[31:0];
|
`CSR_SBU: sbu <= dat[31:0];
|
`CSR_TCB: tcb <= dat;
|
`CSR_TCB: tcb <= dat;
|
`CSR_FSTAT: fpu_csr[37:32] <= dat[37:32];
|
`CSR_FSTAT: fpu_csr[37:32] <= dat[37:32];
|
`CSR_BADADR: badaddr[{thread,csrno[13:11]}] <= dat;
|
`CSR_BADADR: badaddr[{thread,csrno[11:10]}] <= dat;
|
`CSR_CAUSE: cause[{thread,csrno[13:11]}] <= dat[15:0];
|
`CSR_CAUSE: cause[{thread,csrno[11:10]}] <= dat[15:0];
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
`CSR_DBAD0: dbg_adr0 <= dat[AMSB:0];
|
`CSR_DBAD0: dbg_adr0 <= dat[AMSB:0];
|
`CSR_DBAD1: dbg_adr1 <= dat[AMSB:0];
|
`CSR_DBAD1: dbg_adr1 <= dat[AMSB:0];
|
`CSR_DBAD2: dbg_adr2 <= dat[AMSB:0];
|
`CSR_DBAD2: dbg_adr2 <= dat[AMSB:0];
|
`CSR_DBAD3: dbg_adr3 <= dat[AMSB:0];
|
`CSR_DBAD3: dbg_adr3 <= dat[AMSB:0];
|
