| Line 35... |
Line 35... |
// GNU General Public License for more details.
|
// GNU General Public License for more details.
|
//
|
//
|
// You should have received a copy of the GNU General Public License
|
// You should have received a copy of the GNU General Public License
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
//
|
//
|
// Approx. 100,000 LUTs. 160,000 LC's.
|
// Approx 41,000 LUTs. 66,000 LC's.
|
// 38,000LUTs???
|
|
// ============================================================================
|
// ============================================================================
|
//
|
//
|
`include "FT64_config.vh"
|
`include "FT64_config.vh"
|
`include "FT64_defines.vh"
|
`include "FT64_defines.vh"
|
|
|
| Line 90... |
Line 89... |
parameter RBIT = 11;
|
parameter RBIT = 11;
|
parameter DEBUG = 1'b0;
|
parameter DEBUG = 1'b0;
|
parameter NMAP = QENTRIES;
|
parameter NMAP = QENTRIES;
|
parameter BRANCH_PRED = 1'b0;
|
parameter BRANCH_PRED = 1'b0;
|
parameter SUP_TXE = 1'b0;
|
parameter SUP_TXE = 1'b0;
|
parameter SUP_VECTOR = 1;
|
parameter SUP_VECTOR = `SUPPORT_VECTOR;
|
parameter DBW = 64;
|
parameter DBW = 64;
|
parameter ABW = 32;
|
parameter ABW = 32;
|
parameter AMSB = ABW-1;
|
parameter AMSB = ABW-1;
|
parameter NTHREAD = 1;
|
parameter NTHREAD = 1;
|
reg [3:0] i;
|
reg [3:0] i;
|
| Line 387... |
Line 386... |
wire int_commit;
|
wire int_commit;
|
reg StatusHWI;
|
reg StatusHWI;
|
reg [47:0] insn0, insn1, insn2;
|
reg [47:0] insn0, insn1, insn2;
|
wire [47:0] insn0a, insn1b, insn2b;
|
wire [47:0] insn0a, insn1b, insn2b;
|
reg [47:0] insn1a, insn2a;
|
reg [47:0] insn1a, insn2a;
|
reg tgtq;
|
|
// Only need enough bits in the seqnence number to cover the instructions in
|
// Only need enough bits in the seqnence number to cover the instructions in
|
// the queue plus an extra count for skipping on branch misses. In this case
|
// the queue plus an extra count for skipping on branch misses. In this case
|
// that would be four bits minimum (count 0 to 8).
|
// that would be four bits minimum (count 0 to 8).
|
reg [31:0] seq_num;
|
reg [31:0] seq_num;
|
reg [31:0] seq_num1;
|
reg [31:0] seq_num1;
|
| Line 920... |
Line 918... |
.o5(rfoc1a)
|
.o5(rfoc1a)
|
);
|
);
|
assign rfoc0 = Rc0[11:6]==6'h3F ? vm[Rc0[2:0]] : rfoc0a;
|
assign rfoc0 = Rc0[11:6]==6'h3F ? vm[Rc0[2:0]] : rfoc0a;
|
assign rfoc1 = Rc1[11:6]==6'h3F ? vm[Rc1[2:0]] : rfoc1a;
|
assign rfoc1 = Rc1[11:6]==6'h3F ? vm[Rc1[2:0]] : rfoc1a;
|
|
|
function [2:0] fnInsLength;
|
function [3:0] fnInsLength;
|
input [47:0] ins;
|
input [47:0] ins;
|
|
if (ins[`INSTRUCTION_OP]==`CMPRSSD)
|
|
fnInsLength = 4'd2;
|
|
else
|
case(ins[7:6])
|
case(ins[7:6])
|
2'b00: fnInsLength = 3'd4;
|
2'd0: fnInsLength = 4'd4;
|
2'b01: fnInsLength = 3'd6;
|
2'd1: fnInsLength = 4'd6;
|
2'b10: fnInsLength = 3'd2;
|
default: fnInsLength = 4'd2;
|
2'b11: fnInsLength = 3'd2;
|
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
wire [`ABITS] pc0plus6 = pc0 + 32'd6;
|
wire [`ABITS] pc0plus6 = pc0 + 32'd6;
|
wire [`ABITS] pc0plus12 = pc0 + 32'd12;
|
wire [`ABITS] pc0plus12 = pc0 + 32'd12;
|
| Line 1725... |
Line 1725... |
`JMP: fnRt = 12'd0;
|
`JMP: fnRt = 12'd0;
|
`CALL: fnRt = {rgs[thrd],1'b0,regLR}; // regLR
|
`CALL: fnRt = {rgs[thrd],1'b0,regLR}; // regLR
|
`RET: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
`RET: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
`LV: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
`LV: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
`AMO: fnRt = isn[31] ? {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]} : {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
`AMO: fnRt = isn[31] ? {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]} : {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
|
`LUI: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
default: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
default: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
`else
|
`else
|
function [RBIT:0] fnRa;
|
function [RBIT:0] fnRa;
|
| Line 1948... |
Line 1949... |
`JMP: fnRt = 12'd0;
|
`JMP: fnRt = 12'd0;
|
`CALL: fnRt = {rgs,1'b0,regLR}; // regLR
|
`CALL: fnRt = {rgs,1'b0,regLR}; // regLR
|
`RET: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
`RET: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
`LV: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
`LV: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
`AMO: fnRt = isn[31] ? {rgs,1'b0,isn[`INSTRUCTION_RB]} : {rgs,1'b0,isn[`INSTRUCTION_RC]};
|
`AMO: fnRt = isn[31] ? {rgs,1'b0,isn[`INSTRUCTION_RB]} : {rgs,1'b0,isn[`INSTRUCTION_RC]};
|
|
`LUI: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
default: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
default: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
`endif
|
`endif
|
|
|
| Line 2615... |
Line 2617... |
`LV: IsRFW = TRUE;
|
`LV: IsRFW = TRUE;
|
`LVx: IsRFW = TRUE;
|
`LVx: IsRFW = TRUE;
|
`CAS: IsRFW = TRUE;
|
`CAS: IsRFW = TRUE;
|
`AMO: IsRFW = TRUE;
|
`AMO: IsRFW = TRUE;
|
`CSRRW: IsRFW = TRUE;
|
`CSRRW: IsRFW = TRUE;
|
|
`LUI: IsRFW = TRUE;
|
default: IsRFW = FALSE;
|
default: IsRFW = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function IsShifti;
|
function IsShifti;
|
| Line 3025... |
Line 3028... |
.stb_i(stb_o),
|
.stb_i(stb_o),
|
.ack_o(dc_ack),
|
.ack_o(dc_ack),
|
.we_i(we_o),
|
.we_i(we_o),
|
.adr_i(adr_o[15:0]),
|
.adr_i(adr_o[15:0]),
|
.dat_i(dat_o[31:0]),
|
.dat_i(dat_o[31:0]),
|
|
.cmpgrp(cr0[10:8]),
|
.freezePC(freezePC),
|
.freezePC(freezePC),
|
.regLR(regLR),
|
.regLR(regLR),
|
.thread_en(thread_en),
|
.thread_en(thread_en),
|
.insn0(insn0),
|
.insn0(insn0),
|
.insn1(insn1),
|
.insn1(insn1),
|
| Line 5159... |
Line 5163... |
if (commit1_v && n=={commit1_tgt[7:0]} && `NUM_CMT > 1)
|
if (commit1_v && n=={commit1_tgt[7:0]} && `NUM_CMT > 1)
|
regIsValid[n] = regIsValid[n] | (rf_source[ {commit1_tgt[7:0]} ] == commit1_id
|
regIsValid[n] = regIsValid[n] | (rf_source[ {commit1_tgt[7:0]} ] == commit1_id
|
|| (branchmiss && branchmiss_thrd == iqentry_thrd[commit0_id[`QBITS]] && iqentry_source[ commit1_id[`QBITS] ]));
|
|| (branchmiss && branchmiss_thrd == iqentry_thrd[commit0_id[`QBITS]] && iqentry_source[ commit1_id[`QBITS] ]));
|
end
|
end
|
regIsValid[0] = `VAL;
|
regIsValid[0] = `VAL;
|
|
regIsValid[32] = `VAL;
|
|
regIsValid[64] = `VAL;
|
|
regIsValid[128] = `VAL;
|
|
`ifdef SMT
|
|
regIsValid[144] = `VAL;
|
|
regIsValid[160] = `VAL;
|
|
regIsValid[192] = `VAL;
|
|
regIsValid[224] = `VAL;
|
|
`endif
|
end
|
end
|
|
|
// Wait until the cycle after Ra becomes valid to give time to read
|
// Wait until the cycle after Ra becomes valid to give time to read
|
// the vector element from the register file.
|
// the vector element from the register file.
|
reg rf_vra0, rf_vra1;
|
reg rf_vra0, rf_vra1;
|
| Line 5367... |
Line 5380... |
//end
|
//end
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (rst) begin
|
if (rst) begin
|
`ifdef SUPPORT_SMT
|
`ifdef SUPPORT_SMT
|
mstatus[0] <= 64'h0007; // select register set #0 for thread 0
|
mstatus[0] <= 64'h000F; // select register set #0 for thread 0
|
mstatus[1] <= 64'h8007; // select register set #2 for thread 1
|
mstatus[1] <= 64'h800F; // select register set #2 for thread 1
|
`else
|
`else
|
mstatus <= 64'h0007; // select register set #0 for thread 0
|
mstatus <= 64'h000F; // select register set #0 for thread 0
|
`endif
|
`endif
|
for (n = 0; n < QENTRIES; n = n + 1) begin
|
for (n = 0; n < QENTRIES; n = n + 1) begin
|
iqentry_v[n] <= `INV;
|
iqentry_v[n] <= `INV;
|
iqentry_iv[n] <= `INV;
|
iqentry_iv[n] <= `INV;
|
iqentry_is[n] <= 3'b00;
|
iqentry_is[n] <= 3'b00;
|
| Line 5513... |
Line 5526... |
sr_o <= `LOW;
|
sr_o <= `LOW;
|
cr_o <= `LOW;
|
cr_o <= `LOW;
|
adr_o <= RSTPC;
|
adr_o <= RSTPC;
|
icl_o <= `LOW; // instruction cache load
|
icl_o <= `LOW; // instruction cache load
|
cr0 <= 64'd0;
|
cr0 <= 64'd0;
|
cr0[13:8] <= 6'd0; // select register set #0
|
cr0[13:8] <= 6'd0; // select compressed instruction group #0
|
cr0[30] <= TRUE; // enable data caching
|
cr0[30] <= TRUE; // enable data caching
|
cr0[32] <= TRUE; // enable branch predictor
|
cr0[32] <= TRUE; // enable branch predictor
|
cr0[16] <= 1'b0; // disable SMT
|
cr0[16] <= 1'b0; // disable SMT
|
cr0[17] <= 1'b0; // sequence number reset = 1
|
cr0[17] <= 1'b0; // sequence number reset = 1
|
cr0[34] <= FALSE; // write buffer merging enable
|
cr0[34] <= FALSE; // write buffer merging enable
|
pcr <= 32'd0;
|
pcr <= 32'd0;
|
pcr2 <= 64'd0;
|
pcr2 <= 64'd0;
|
for (n = 0; n < PREGS; n = n + 1)
|
for (n = 0; n < PREGS; n = n + 1)
|
rf_v[n] <= `VAL;
|
rf_v[n] <= `VAL;
|
tgtq <= FALSE;
|
|
fp_rm <= 3'd0; // round nearest even - default rounding mode
|
fp_rm <= 3'd0; // round nearest even - default rounding mode
|
fpu_csr[37:32] <= 5'd31; // register set #31
|
fpu_csr[37:32] <= 5'd31; // register set #31
|
waitctr <= 64'd0;
|
waitctr <= 64'd0;
|
for (n = 0; n < 16; n = n + 1)
|
for (n = 0; n < 16; n = n + 1)
|
badaddr[n] <= 64'd0;
|
badaddr[n] <= 64'd0;
|
| Line 5719... |
Line 5731... |
enque1(tail0, fetchbuf1_thrd ? seq_num1 : seq_num, vqe1);
|
enque1(tail0, fetchbuf1_thrd ? seq_num1 : seq_num, vqe1);
|
if (fetchbuf1_thrd)
|
if (fetchbuf1_thrd)
|
seq_num1 <= seq_num1 + 5'd1;
|
seq_num1 <= seq_num1 + 5'd1;
|
else
|
else
|
seq_num <= seq_num + 5'd1;
|
seq_num <= seq_num + 5'd1;
|
tgtq <= FALSE;
|
|
if (fetchbuf1_rfw) begin
|
if (fetchbuf1_rfw) begin
|
rf_source[ Rt1s ] <= { 1'b0, fetchbuf1_memld, tail0 }; // top bit indicates ALU/MEM bus
|
rf_source[ Rt1s ] <= { 1'b0, fetchbuf1_memld, tail0 }; // top bit indicates ALU/MEM bus
|
rf_v [Rt1s] <= `INV;
|
rf_v [Rt1s] <= `INV;
|
end
|
end
|
if (canq2 && vqe1 < vl-2) begin
|
if (canq2 && vqe1 < vl-2) begin
|
| Line 5737... |
Line 5748... |
enque1(tail1, fetchbuf1_thrd ? seq_num1 + 5'd1 : seq_num + 5'd1, vqe1 + 6'd1);
|
enque1(tail1, fetchbuf1_thrd ? seq_num1 + 5'd1 : seq_num + 5'd1, vqe1 + 6'd1);
|
if (fetchbuf1_thrd)
|
if (fetchbuf1_thrd)
|
seq_num1 <= seq_num1 + 5'd2;
|
seq_num1 <= seq_num1 + 5'd2;
|
else
|
else
|
seq_num <= seq_num + 5'd2;
|
seq_num <= seq_num + 5'd2;
|
tgtq <= FALSE;
|
|
if (fetchbuf1_rfw) begin
|
if (fetchbuf1_rfw) begin
|
rf_source[ Rt1s ] <= { 1'b0, fetchbuf1_memld, tail1 }; // top bit indicates ALU/MEM bus
|
rf_source[ Rt1s ] <= { 1'b0, fetchbuf1_memld, tail1 }; // top bit indicates ALU/MEM bus
|
rf_v [Rt1s] <= `INV;
|
rf_v [Rt1s] <= `INV;
|
end
|
end
|
end
|
end
|
| Line 5750... |
Line 5760... |
enque1(tail0, fetchbuf1_thrd ? seq_num1 : seq_num, 6'd0);
|
enque1(tail0, fetchbuf1_thrd ? seq_num1 : seq_num, 6'd0);
|
if (fetchbuf1_thrd)
|
if (fetchbuf1_thrd)
|
seq_num1 <= seq_num1 + 5'd1;
|
seq_num1 <= seq_num1 + 5'd1;
|
else
|
else
|
seq_num <= seq_num + 5'd1;
|
seq_num <= seq_num + 5'd1;
|
tgtq <= FALSE;
|
|
if (fetchbuf1_rfw) begin
|
if (fetchbuf1_rfw) begin
|
rf_source[ Rt1s ] <= { 1'b0, fetchbuf1_memld, tail0 }; // top bit indicates ALU/MEM bus
|
rf_source[ Rt1s ] <= { 1'b0, fetchbuf1_memld, tail0 }; // top bit indicates ALU/MEM bus
|
rf_v [Rt1s] <= `INV;
|
rf_v [Rt1s] <= `INV;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
2'b10:
|
2'b10:
|
if (canq1) begin
|
if (canq1) begin
|
// $display("queued1: %d", queued1);
|
enque0x();
|
// if (!IsBranch(fetchbuf0_instr)) panic <= `PANIC_FETCHBUFBEQ;
|
|
// if (!predict_taken0) panic <= `PANIC_FETCHBUFBEQ;
|
|
//
|
|
// this should only happen when the first instruction is a BEQ-backwards and the IQ
|
|
// happened to be full on the previous cycle (thus we deleted fetchbuf1 but did not
|
|
// enqueue fetchbuf0) ... probably no need to check for LW -- sanity check, just in case
|
|
//
|
|
if (IsVector(fetchbuf0_instr) && SUP_VECTOR) begin
|
|
vqe0 <= vqe0 + 4'd1;
|
|
if (IsVCmprss(fetchbuf0_instr)) begin
|
|
if (vm[fetchbuf0_instr[25:23]][vqe0])
|
|
vqet0 <= vqet0 + 4'd1;
|
|
end
|
|
else
|
|
vqet0 <= vqet0 + 4'd1;
|
|
if (vqe0 >= vl-2)
|
|
nop_fetchbuf <= fetchbuf ? 4'b1000 : 4'b0010;
|
|
enque0(tail0, fetchbuf0_thrd ? seq_num1 : seq_num, vqe0);
|
|
if (fetchbuf0_thrd)
|
|
seq_num1 <= seq_num1 + 5'd1;
|
|
else
|
|
seq_num <= seq_num + 5'd1;
|
|
tgtq <= FALSE;
|
|
if (fetchbuf0_rfw) begin
|
|
rf_source[ Rt0s ] <= { 1'b0, fetchbuf0_memld, tail0 }; // top bit indicates ALU/MEM bus
|
|
rf_v[Rt0s] <= `INV;
|
|
end
|
|
if (canq2) begin
|
|
if (vqe0 < vl-2) begin
|
|
vqe0 <= vqe0 + 4'd2;
|
|
if (IsVCmprss(fetchbuf0_instr)) begin
|
|
if (vm[fetchbuf0_instr[25:23]][vqe0+6'd1])
|
|
vqet0 <= vqet0 + 4'd2;
|
|
end
|
|
else
|
|
vqet0 <= vqet0 + 4'd2;
|
|
enque0(tail1, fetchbuf0_thrd ? seq_num1 + 5'd1 : seq_num+5'd1, vqe0 + 6'd1);
|
|
if (fetchbuf0_thrd)
|
|
seq_num1 <= seq_num1 + 5'd2;
|
|
else
|
|
seq_num <= seq_num + 5'd2;
|
|
tgtq <= FALSE;
|
|
if (fetchbuf0_rfw) begin
|
|
rf_source[ Rt0s ] <= { 1'b0, fetchbuf0_memld, tail1 }; // top bit indicates ALU/MEM bus
|
|
rf_v[Rt0s] <= `INV;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
else begin
|
|
enque0(tail0, fetchbuf0_thrd ? seq_num1 : seq_num, 6'd0);
|
|
if (fetchbuf0_thrd)
|
|
seq_num1 <= seq_num1 + 5'd1;
|
|
else
|
|
seq_num <= seq_num + 5'd1;
|
|
tgtq <= FALSE;
|
|
if (fetchbuf0_rfw) begin
|
|
rf_source[ Rt0s ] <= { 1'b0, fetchbuf0_memld, tail0 }; // top bit indicates ALU/MEM bus
|
|
rf_v[Rt0s] <= `INV;
|
|
end
|
|
end
|
|
end
|
end
|
|
|
2'b11:
|
2'b11:
|
if (canq1) begin
|
if (canq1) begin
|
//
|
//
|
// if the first instruction is a predicted branch, enqueue it & stomp on all following instructions
|
// if the first instruction is a predicted branch, enqueue it & stomp on all following instructions
|
// but only if the following instruction is in the same thread. Otherwise we want to queue two.
|
// but only if the following instruction is in the same thread. Otherwise we want to queue two.
|
//
|
//
|
if (take_branch0 && fetchbuf1_thrd==fetchbuf0_thrd) begin
|
if (take_branch0 && fetchbuf1_thrd==fetchbuf0_thrd) begin
|
tgtq <= FALSE;
|
enque0x();
|
enque0(tail0,fetchbuf0_thrd ? seq_num1 : seq_num,6'd0);
|
|
if (fetchbuf0_thrd)
|
|
seq_num1 <= seq_num1 + 5'd1;
|
|
else
|
|
seq_num <= seq_num + 5'd1;
|
|
if (fetchbuf0_rfw) begin
|
|
rf_source[ Rt0s ] <= {1'b0,fetchbuf0_memld, tail0};
|
|
rf_v [ Rt0s ] <= `INV;
|
|
end
|
|
end
|
end
|
|
|
else begin // fetchbuf0 doesn't contain a predicted branch
|
else begin // fetchbuf0 doesn't contain a predicted branch
|
//
|
//
|
// so -- we can enqueue 1 or 2 instructions, depending on space in the IQ
|
// so -- we can enqueue 1 or 2 instructions, depending on space in the IQ
|
| Line 5864... |
Line 5803... |
else
|
else
|
vqet0 <= vqet0 + 4'd1;
|
vqet0 <= vqet0 + 4'd1;
|
if (vqe0 >= vl-2)
|
if (vqe0 >= vl-2)
|
nop_fetchbuf <= fetchbuf ? 4'b1000 : 4'b0010;
|
nop_fetchbuf <= fetchbuf ? 4'b1000 : 4'b0010;
|
end
|
end
|
tgtq <= FALSE;
|
|
if (vqe0 < vl || !IsVector(fetchbuf0_instr)) begin
|
if (vqe0 < vl || !IsVector(fetchbuf0_instr)) begin
|
enque0(tail0, fetchbuf0_thrd ? seq_num1 : seq_num, vqe0);
|
enque0(tail0, fetchbuf0_thrd ? seq_num1 : seq_num, vqe0);
|
if (fetchbuf0_thrd)
|
if (fetchbuf0_thrd)
|
seq_num1 <= seq_num1 + 5'd1;
|
seq_num1 <= seq_num1 + 5'd1;
|
else
|
else
|
| Line 5912... |
Line 5850... |
else
|
else
|
seq_num <= seq_num + 5'd1;
|
seq_num <= seq_num + 5'd1;
|
end
|
end
|
|
|
// SOURCE 1 ...
|
// SOURCE 1 ...
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
a1_vs();
|
if (~fetchbuf0_rfw) begin
|
|
iqentry_a1_v [tail1] <= regIsValid[Ra1s];
|
|
iqentry_a1_s [tail1] <= rf_source [Ra1s];
|
|
end
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
|
else if (Ra1 == Rt0) begin
|
|
// if the previous instruction is a LW, then grab result from memq, not the iq
|
|
iqentry_a1_v [tail1] <= `INV;
|
|
iqentry_a1_s [tail1] <= { 1'b0, fetchbuf0_mem &IsLoad(fetchbuf0_instr), tail0 };
|
|
end
|
|
// if no overlap, get info from rf_v and rf_source
|
|
else begin
|
|
iqentry_a1_v [tail1] <= regIsValid[Ra1s];
|
|
iqentry_a1_s [tail1] <= rf_source [Ra1s];
|
|
end
|
|
|
|
// SOURCE 2 ...
|
// SOURCE 2 ...
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
a2_vs();
|
if (~fetchbuf0_rfw) begin
|
|
iqentry_a2_v [tail1] <= regIsValid[Rb1s];
|
|
iqentry_a2_s [tail1] <= rf_source[ Rb1s ];
|
|
end
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
|
else if (Rb1s == Rt0s) begin
|
|
// if the previous instruction is a LW, then grab result from memq, not the iq
|
|
iqentry_a2_v [tail1] <= `INV;
|
|
iqentry_a2_s [tail1] <= { 1'b0, fetchbuf0_mem &IsLoad(fetchbuf0_instr), tail0 };
|
|
end
|
|
// if no overlap, get info from rf_v and rf_source
|
|
else begin
|
|
iqentry_a2_v [tail1] <= regIsValid[Rb1s];
|
|
iqentry_a2_s [tail1] <= rf_source[ Rb1s ];
|
|
end
|
|
|
|
// SOURCE 3 ...
|
// SOURCE 3 ...
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
a3_vs();
|
if (~fetchbuf0_rfw) begin
|
|
iqentry_a3_v [tail1] <= regIsValid[Rc1s];
|
|
iqentry_a3_s [tail1] <= rf_source[ Rc1s ];
|
|
end
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
|
else if (Rc1 == Rt0) begin
|
|
// if the previous instruction is a LW, then grab result from memq, not the iq
|
|
iqentry_a3_v [tail1] <= `INV;
|
|
iqentry_a3_s [tail1] <= { 1'b0, fetchbuf0_mem &IsLoad(fetchbuf0_instr), tail0 };
|
|
end
|
|
// if no overlap, get info from rf_v and rf_source
|
|
else begin
|
|
iqentry_a3_v [tail1] <= regIsValid[Rc1s];
|
|
iqentry_a3_s [tail1] <= rf_source[ Rc1s ];
|
|
end
|
|
|
|
// if the two instructions enqueued target the same register,
|
// if the two instructions enqueued target the same register,
|
// make sure only the second writes to rf_v and rf_source.
|
// make sure only the second writes to rf_v and rf_source.
|
// first is allowed to update rf_v and rf_source only if the
|
// first is allowed to update rf_v and rf_source only if the
|
// second has no target
|
// second has no target
|
| Line 6052... |
Line 5945... |
else
|
else
|
seq_num <= seq_num + 5'd1;
|
seq_num <= seq_num + 5'd1;
|
end
|
end
|
|
|
// SOURCE 1 ...
|
// SOURCE 1 ...
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
a1_vs();
|
if (~fetchbuf0_rfw) begin
|
|
iqentry_a1_v [tail1] <= regIsValid[Ra1s];
|
|
iqentry_a1_s [tail1] <= rf_source [Ra1s];
|
|
end
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
|
else if (Ra1 == Rt0) begin
|
|
// if the previous instruction is a LW, then grab result from memq, not the iq
|
|
iqentry_a1_v [tail1] <= `INV;
|
|
iqentry_a1_s [tail1] <= { 1'b0, fetchbuf0_mem &IsLoad(fetchbuf0_instr), tail0 };
|
|
end
|
|
// if no overlap, get info from rf_v and rf_source
|
|
else begin
|
|
iqentry_a1_v [tail1] <= regIsValid[Ra1s];
|
|
iqentry_a1_s [tail1] <= rf_source [Ra1s];
|
|
end
|
|
|
|
// SOURCE 2 ...
|
// SOURCE 2 ..
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
a2_vs();
|
if (~fetchbuf0_rfw) begin
|
|
iqentry_a2_v [tail1] <= regIsValid[Rb1s];
|
|
iqentry_a2_s [tail1] <= rf_source[ Rb1s ];
|
|
end
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
|
else if (Rb1s == Rt0s) begin
|
|
// if the previous instruction is a LW, then grab result from memq, not the iq
|
|
iqentry_a2_v [tail1] <= `INV;
|
|
iqentry_a2_s [tail1] <= { 1'b0, fetchbuf0_mem &IsLoad(fetchbuf0_instr), tail0 };
|
|
end
|
|
// if no overlap, get info from rf_v and rf_source
|
|
else begin
|
|
iqentry_a2_v [tail1] <= regIsValid[Rb1s];
|
|
iqentry_a2_s [tail1] <= rf_source[ Rb1s ];
|
|
end
|
|
|
|
// SOURCE 3 ...
|
// SOURCE 3 ...
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
a3_vs();
|
if (~fetchbuf0_rfw) begin
|
|
iqentry_a3_v [tail1] <= regIsValid[Rc1s];
|
|
iqentry_a3_s [tail1] <= rf_source[ Rc1s ];
|
|
end
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
|
else if (Rc1 == Rt0) begin
|
|
// if the previous instruction is a LW, then grab result from memq, not the iq
|
|
iqentry_a3_v [tail1] <= `INV;
|
|
iqentry_a3_s [tail1] <= { 1'b0, fetchbuf0_mem &IsLoad(fetchbuf0_instr), tail0 };
|
|
end
|
|
// if no overlap, get info from rf_v and rf_source
|
|
else begin
|
|
iqentry_a3_v [tail1] <= regIsValid[Rc1s];
|
|
iqentry_a3_s [tail1] <= rf_source[ Rc1s ];
|
|
end
|
|
|
|
// if the two instructions enqueued target the same register,
|
// if the two instructions enqueued target the same register,
|
// make sure only the second writes to rf_v and rf_source.
|
// make sure only the second writes to rf_v and rf_source.
|
// first is allowed to update rf_v and rf_source only if the
|
// first is allowed to update rf_v and rf_source only if the
|
// second has no target
|
// second has no target
|
| Line 6137... |
Line 5985... |
seq_num1 <= seq_num1 + 5'd1;
|
seq_num1 <= seq_num1 + 5'd1;
|
seq_num <= seq_num + 5'd1;
|
seq_num <= seq_num + 5'd1;
|
end
|
end
|
|
|
// SOURCE 1 ...
|
// SOURCE 1 ...
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
a1_vs();
|
if (~fetchbuf0_rfw) begin
|
|
iqentry_a1_v [tail1] <= regIsValid[Ra1s];
|
|
iqentry_a1_s [tail1] <= rf_source [Ra1s];
|
|
end
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
|
else if (Ra1s == Rt0s) begin
|
|
iqentry_a1_v [tail1] <= `INV;
|
|
iqentry_a1_s [tail1] <= { 1'b0, fetchbuf0_memld, tail0 };
|
|
end
|
|
// if no overlap, get info from regIsValid and rf_source
|
|
else begin
|
|
iqentry_a1_v [tail1] <= regIsValid[Ra1s];
|
|
iqentry_a1_s [tail1] <= rf_source [Ra1s];
|
|
end
|
|
|
|
// SOURCE 2 ...
|
// SOURCE 2 ...
|
// if the argument is an immediate or not needed, we're done
|
a2_vs();
|
$display("Rb1s=%h, Rt0s=%h", Rb1s, Rt0s);
|
|
$display("instr=%h", fetchbuf1_instr);
|
|
// if previous instruction writes nothing to RF, then get info from regIsValid and rf_source
|
|
if (~fetchbuf0_rfw) begin
|
|
$display("fetchbuf0_rfw=0");
|
|
iqentry_a2_v [tail1] <= regIsValid[Rb1s];
|
|
iqentry_a2_s [tail1] <= rf_source[ Rb1s ];
|
|
end
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
|
else if (Rb1s == Rt0s) begin
|
|
// if the previous instruction is a LW, then grab result from memq, not the iq
|
|
iqentry_a2_v [tail1] <= `INV;
|
|
iqentry_a2_s [tail1] <= { 1'b0, fetchbuf0_memld, tail0 };
|
|
end
|
|
// if no overlap, get info from regIsValid and rf_source
|
|
else begin
|
|
$display("No overlap");
|
|
iqentry_a2_v [tail1] <= regIsValid[Rb1s];
|
|
iqentry_a2_s [tail1] <= rf_source[ Rb1s ];
|
|
end
|
|
|
|
// SOURCE 3 ...
|
// SOURCE 3 ...
|
// if previous instruction writes nothing to RF, then get info from regIsValid and rf_source
|
a3_vs();
|
if (~fetchbuf0_rfw) begin
|
|
iqentry_a3_v [tail1] <= regIsValid[Rc1s];
|
|
iqentry_a3_s [tail1] <= rf_source[ Rc1s ];
|
|
end
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
|
else if (Rc1s == Rt0s) begin
|
|
// if the previous instruction is a LW, then grab result from memq, not the iq
|
|
iqentry_a3_v [tail1] <= `INV;
|
|
iqentry_a3_s [tail1] <= { 1'b0, fetchbuf0_memld, tail0 };
|
|
end
|
|
// if no overlap, get info from regIsValid and rf_source
|
|
else begin
|
|
iqentry_a3_v [tail1] <= regIsValid[Rc1s];
|
|
iqentry_a3_s [tail1] <= rf_source[ Rc1s ];
|
|
end
|
|
|
|
// if the two instructions enqueued target the same register,
|
// if the two instructions enqueued target the same register,
|
// make sure only the second writes to regIsValid and rf_source.
|
// make sure only the second writes to regIsValid and rf_source.
|
// first is allowed to update regIsValid and rf_source only if the
|
// first is allowed to update regIsValid and rf_source only if the
|
// second has no target (BEQ or SW)
|
// second has no target (BEQ or SW)
|
| Line 6313... |
Line 6112... |
iqentry_done[ fcu_id[`QBITS] ] <= `TRUE;
|
iqentry_done[ fcu_id[`QBITS] ] <= `TRUE;
|
iqentry_cmt[ fcu_id[`QBITS] ] <= `TRUE;
|
iqentry_cmt[ fcu_id[`QBITS] ] <= `TRUE;
|
end
|
end
|
// Only safe place to propagate the miss pc is a0.
|
// Only safe place to propagate the miss pc is a0.
|
iqentry_a0[ fcu_id[`QBITS] ] <= fcu_misspc;
|
iqentry_a0[ fcu_id[`QBITS] ] <= fcu_misspc;
|
// Update branch taken indicator.
|
// Update branch target update indicator.
|
if (fcu_jal || fcu_ret || fcu_brk || fcu_rti) begin
|
if (fcu_jal || fcu_ret || fcu_brk || fcu_rti) begin
|
iqentry_bt[ fcu_id[`QBITS] ] <= `VAL;
|
iqentry_bt[ fcu_id[`QBITS] ] <= `VAL;
|
end
|
end
|
// Branch target is only updated for branch-to-register
|
// Branch target is only updated for branch-to-register
|
else if (fcu_branch) begin
|
else if (fcu_branch) begin
|
| Line 7086... |
Line 6885... |
|
|
|
|
rf_source[0] <= 0;
|
rf_source[0] <= 0;
|
L1_wr0 <= FALSE;
|
L1_wr0 <= FALSE;
|
L1_wr1 <= FALSE;
|
L1_wr1 <= FALSE;
|
|
L1_wr2 <= FALSE;
|
L1_invline <= FALSE;
|
L1_invline <= FALSE;
|
icnxt <= FALSE;
|
icnxt <= FALSE;
|
L2_nxt <= FALSE;
|
L2_nxt <= FALSE;
|
// Instruction cache state machine.
|
// Instruction cache state machine.
|
// On a miss first see if the instruction is in the L2 cache. No need to go to
|
// On a miss first see if the instruction is in the L2 cache. No need to go to
|
| Line 7103... |
Line 6903... |
IDLE:
|
IDLE:
|
// If the bus unit is busy doing an update involving L1_adr or L2_adr
|
// If the bus unit is busy doing an update involving L1_adr or L2_adr
|
// we have to wait.
|
// we have to wait.
|
if (bstate != B7 && bstate != B9) begin
|
if (bstate != B7 && bstate != B9) begin
|
if (!ihit0) begin
|
if (!ihit0) begin
|
L1_adr <= {pcr[5:0],pc0[31:3],3'h0};
|
L1_adr <= {pcr[5:0],pc0[31:5],5'h0};
|
L2_adr <= {pcr[5:0],pc0[31:3],3'h0};
|
L2_adr <= {pcr[5:0],pc0[31:5],5'h0};
|
L1_invline <= TRUE;
|
L1_invline <= TRUE;
|
icwhich <= 2'b00;
|
icwhich <= 2'b00;
|
iccnt <= 3'b00;
|
iccnt <= 3'b00;
|
icstate <= IC2;
|
icstate <= IC2;
|
end
|
end
|
else if (!ihit1 && `WAYS > 1) begin
|
else if (!ihit1 && `WAYS > 1) begin
|
`ifdef SUPPORT_SMT
|
if (thread_en) begin
|
L1_adr <= {pcr[5:0],pc1[31:3],3'h0};
|
L1_adr <= {pcr[5:0],pc1[31:5],5'h0};
|
L2_adr <= {pcr[5:0],pc1[31:3],3'h0};
|
L2_adr <= {pcr[5:0],pc1[31:5],5'h0};
|
`else
|
end
|
L1_adr <= {pcr[5:0],pc0plus6[31:3],3'h0};
|
else begin
|
L2_adr <= {pcr[5:0],pc0plus6[31:3],3'h0};
|
L1_adr <= {pcr[5:0],pc0plus6[31:5],5'h0};
|
`endif
|
L2_adr <= {pcr[5:0],pc0plus6[31:5],5'h0};
|
|
end
|
L1_invline <= TRUE;
|
L1_invline <= TRUE;
|
icwhich <= 2'b01;
|
icwhich <= 2'b01;
|
iccnt <= 3'b00;
|
iccnt <= 3'b00;
|
icstate <= IC2;
|
icstate <= IC2;
|
end
|
end
|
else if (!ihit2 && `WAYS > 2) begin
|
else if (!ihit2 && `WAYS > 2) begin
|
`ifdef SUPPORT_SMT
|
if (thread_en) begin
|
L1_adr <= {pcr[5:0],pc2[31:3],3'h0};
|
L1_adr <= {pcr[5:0],pc2[31:5],5'h0};
|
L2_adr <= {pcr[5:0],pc2[31:3],3'h0};
|
L2_adr <= {pcr[5:0],pc2[31:5],5'h0};
|
`else
|
end
|
L1_adr <= {pcr[5:0],pc0plus12[31:3],3'h0};
|
else begin
|
L2_adr <= {pcr[5:0],pc0plus12[31:3],3'h0};
|
L1_adr <= {pcr[5:0],pc0plus12[31:5],5'h0};
|
`endif
|
L2_adr <= {pcr[5:0],pc0plus12[31:5],5'h0};
|
|
end
|
L1_invline <= TRUE;
|
L1_invline <= TRUE;
|
icwhich <= 2'b10;
|
icwhich <= 2'b10;
|
iccnt <= 3'b00;
|
iccnt <= 3'b00;
|
icstate <= IC2;
|
icstate <= IC2;
|
end
|
end
|
| Line 8462... |
Line 8264... |
// iqentry_Rt [nn] <= bus[`IB_RT];
|
// iqentry_Rt [nn] <= bus[`IB_RT];
|
// iqentry_Rc [nn] <= bus[`IB_RC];
|
// iqentry_Rc [nn] <= bus[`IB_RC];
|
// iqentry_Ra [nn] <= bus[`IB_RA];
|
// iqentry_Ra [nn] <= bus[`IB_RA];
|
iqentry_a0 [nn] <= bus[`IB_CONST];
|
iqentry_a0 [nn] <= bus[`IB_CONST];
|
iqentry_imm [nn] <= bus[`IB_IMM];
|
iqentry_imm [nn] <= bus[`IB_IMM];
|
iqentry_insln[nn] <= bus[`IB_LN];
|
// iqentry_insln[nn] <= bus[`IB_LN];
|
iqentry_jal [nn] <= bus[`IB_JAL];
|
iqentry_jal [nn] <= bus[`IB_JAL];
|
iqentry_ret [nn] <= bus[`IB_RET];
|
iqentry_ret [nn] <= bus[`IB_RET];
|
iqentry_irq [nn] <= bus[`IB_IRQ];
|
iqentry_irq [nn] <= bus[`IB_IRQ];
|
iqentry_brk [nn] <= bus[`IB_BRK];
|
iqentry_brk [nn] <= bus[`IB_BRK];
|
iqentry_rti [nn] <= bus[`IB_RTI];
|
iqentry_rti [nn] <= bus[`IB_RTI];
|
| Line 8499... |
Line 8301... |
iqentry_we [nn] <= bus[`IB_WE];
|
iqentry_we [nn] <= bus[`IB_WE];
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
|
task a1_vs;
|
|
begin
|
|
// if there is not an overlapping write to the register file.
|
|
if (Ra1s != Rt0s || !fetchbuf0_rfw) begin
|
|
iqentry_a1_v [tail1] <= regIsValid[Ra1s];
|
|
iqentry_a1_s [tail1] <= rf_source [Ra1s];
|
|
end
|
|
else begin
|
|
iqentry_a1_v [tail1] <= `INV;
|
|
iqentry_a1_s [tail1] <= { 1'b0, fetchbuf0_memld, tail0 };
|
|
end
|
|
end
|
|
endtask
|
|
|
|
task a2_vs;
|
|
begin
|
|
// if there is not an overlapping write to the register file.
|
|
if (Rb1s != Rt0s || !fetchbuf0_rfw) begin
|
|
iqentry_a2_v [tail1] <= regIsValid[Rb1s];
|
|
iqentry_a2_s [tail1] <= rf_source [Rb1s];
|
|
end
|
|
else begin
|
|
iqentry_a2_v [tail1] <= `INV;
|
|
iqentry_a2_s [tail1] <= { 1'b0, fetchbuf0_memld, tail0 };
|
|
end
|
|
end
|
|
endtask
|
|
|
|
task a3_vs;
|
|
begin
|
|
// if there is not an overlapping write to the register file.
|
|
if (Rc1s != Rt0s || !fetchbuf0_rfw) begin
|
|
iqentry_a3_v [tail1] <= regIsValid[Rc1s];
|
|
iqentry_a3_s [tail1] <= rf_source [Rc1s];
|
|
end
|
|
else begin
|
|
iqentry_a3_v [tail1] <= `INV;
|
|
iqentry_a3_s [tail1] <= { 1'b0, fetchbuf0_memld, tail0 };
|
|
end
|
|
end
|
|
endtask
|
|
|
|
task enque0x;
|
|
begin
|
|
if (IsVector(fetchbuf0_instr) && SUP_VECTOR) begin
|
|
vqe0 <= vqe0 + 4'd1;
|
|
if (IsVCmprss(fetchbuf0_instr)) begin
|
|
if (vm[fetchbuf0_instr[25:23]][vqe0])
|
|
vqet0 <= vqet0 + 4'd1;
|
|
end
|
|
else
|
|
vqet0 <= vqet0 + 4'd1;
|
|
if (vqe0 >= vl-2)
|
|
nop_fetchbuf <= fetchbuf ? 4'b1000 : 4'b0010;
|
|
enque0(tail0, fetchbuf0_thrd ? seq_num1 : seq_num, vqe0);
|
|
if (fetchbuf0_thrd)
|
|
seq_num1 <= seq_num1 + 5'd1;
|
|
else
|
|
seq_num <= seq_num + 5'd1;
|
|
if (fetchbuf0_rfw) begin
|
|
rf_source[ Rt0s ] <= { 1'b0, fetchbuf0_memld, tail0 }; // top bit indicates ALU/MEM bus
|
|
rf_v[Rt0s] <= `INV;
|
|
end
|
|
if (canq2) begin
|
|
if (vqe0 < vl-2) begin
|
|
vqe0 <= vqe0 + 4'd2;
|
|
if (IsVCmprss(fetchbuf0_instr)) begin
|
|
if (vm[fetchbuf0_instr[25:23]][vqe0+6'd1])
|
|
vqet0 <= vqet0 + 4'd2;
|
|
end
|
|
else
|
|
vqet0 <= vqet0 + 4'd2;
|
|
enque0(tail1, fetchbuf0_thrd ? seq_num1 + 5'd1 : seq_num+5'd1, vqe0 + 6'd1);
|
|
if (fetchbuf0_thrd)
|
|
seq_num1 <= seq_num1 + 5'd2;
|
|
else
|
|
seq_num <= seq_num + 5'd2;
|
|
if (fetchbuf0_rfw) begin
|
|
rf_source[ Rt0s ] <= { 1'b0, fetchbuf0_memld, tail1 }; // top bit indicates ALU/MEM bus
|
|
rf_v[Rt0s] <= `INV;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
else begin
|
|
enque0(tail0, fetchbuf0_thrd ? seq_num1 : seq_num, 6'd0);
|
|
if (fetchbuf0_thrd)
|
|
seq_num1 <= seq_num1 + 5'd1;
|
|
else
|
|
seq_num <= seq_num + 5'd1;
|
|
if (fetchbuf0_rfw) begin
|
|
rf_source[ Rt0s ] <= { 1'b0, fetchbuf0_memld, tail0 }; // top bit indicates ALU/MEM bus
|
|
rf_v[Rt0s] <= `INV;
|
|
end
|
|
end
|
|
end
|
|
endtask
|
|
|
// Enqueue fetchbuf0 onto the tail of the instruction queue
|
// Enqueue fetchbuf0 onto the tail of the instruction queue
|
task enque0;
|
task enque0;
|
input [`QBITS] tail;
|
input [`QBITS] tail;
|
input [63:0] seqnum;
|
input [63:0] seqnum;
|
input [5:0] venno;
|
input [5:0] venno;
|
| Line 8522... |
Line 8422... |
iqentry_done [tail] <= `INV;
|
iqentry_done [tail] <= `INV;
|
iqentry_cmt [tail] <= `INV;
|
iqentry_cmt [tail] <= `INV;
|
iqentry_out [tail] <= `INV;
|
iqentry_out [tail] <= `INV;
|
iqentry_res [tail] <= `ZERO;
|
iqentry_res [tail] <= `ZERO;
|
iqentry_instr[tail] <= IsVLS(fetchbuf0_instr) ? (vm[fnM2(fetchbuf0_instr)] ? fetchbuf0_instr : `NOP_INSN) : fetchbuf0_instr;
|
iqentry_instr[tail] <= IsVLS(fetchbuf0_instr) ? (vm[fnM2(fetchbuf0_instr)] ? fetchbuf0_instr : `NOP_INSN) : fetchbuf0_instr;
|
|
iqentry_insln[tail] <= fetchbuf0_insln;
|
iqentry_pt [tail] <= predict_taken0;
|
iqentry_pt [tail] <= predict_taken0;
|
iqentry_agen [tail] <= `INV;
|
iqentry_agen [tail] <= `INV;
|
iqentry_state[tail] <= IQS_IDLE;
|
iqentry_state[tail] <= IQS_IDLE;
|
// If the previous instruction was a hardware interrupt and this instruction is a hardware interrupt
|
// If the previous instruction was a hardware interrupt and this instruction is a hardware interrupt
|
// inherit the previous pc.
|
// inherit the previous pc.
|
| Line 8576... |
Line 8477... |
iqentry_done [tail] <= `INV;
|
iqentry_done [tail] <= `INV;
|
iqentry_cmt [tail] <= `INV;
|
iqentry_cmt [tail] <= `INV;
|
iqentry_out [tail] <= `INV;
|
iqentry_out [tail] <= `INV;
|
iqentry_res [tail] <= `ZERO;
|
iqentry_res [tail] <= `ZERO;
|
iqentry_instr[tail] <= IsVLS(fetchbuf1_instr) ? (vm[fnM2(fetchbuf1_instr)] ? fetchbuf1_instr : `NOP_INSN) : fetchbuf1_instr;
|
iqentry_instr[tail] <= IsVLS(fetchbuf1_instr) ? (vm[fnM2(fetchbuf1_instr)] ? fetchbuf1_instr : `NOP_INSN) : fetchbuf1_instr;
|
|
iqentry_insln[tail] <= fetchbuf1_insln;
|
iqentry_pt [tail] <= predict_taken1;
|
iqentry_pt [tail] <= predict_taken1;
|
iqentry_agen [tail] <= `INV;
|
iqentry_agen [tail] <= `INV;
|
iqentry_state[tail] <= IQS_IDLE;
|
iqentry_state[tail] <= IQS_IDLE;
|
// If queing 2nd instruction must read from first
|
// If queing 2nd instruction must read from first
|
if (tail==tail1) begin
|
if (tail==tail1) begin
|
