| Line 1725... |
Line 1725... |
`JMP: fnRt = 12'd0;
|
`JMP: fnRt = 12'd0;
|
`CALL: fnRt = {rgs[thrd],1'b0,regLR}; // regLR
|
`CALL: fnRt = {rgs[thrd],1'b0,regLR}; // regLR
|
`RET: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
`RET: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
`LV: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
`LV: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
`AMO: fnRt = isn[31] ? {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]} : {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
`AMO: fnRt = isn[31] ? {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]} : {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
`LUI: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
`AUIPC,`LUI: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
default: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
default: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
`else
|
`else
|
function [RBIT:0] fnRa;
|
function [RBIT:0] fnRa;
|
| Line 1949... |
Line 1949... |
`JMP: fnRt = 12'd0;
|
`JMP: fnRt = 12'd0;
|
`CALL: fnRt = {rgs,1'b0,regLR}; // regLR
|
`CALL: fnRt = {rgs,1'b0,regLR}; // regLR
|
`RET: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
`RET: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
`LV: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
`LV: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
`AMO: fnRt = isn[31] ? {rgs,1'b0,isn[`INSTRUCTION_RB]} : {rgs,1'b0,isn[`INSTRUCTION_RC]};
|
`AMO: fnRt = isn[31] ? {rgs,1'b0,isn[`INSTRUCTION_RB]} : {rgs,1'b0,isn[`INSTRUCTION_RC]};
|
`LUI: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
`AUIPC,`LUI: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
default: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
default: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
`endif
|
`endif
|
|
|
| Line 2617... |
Line 2617... |
`LV: IsRFW = TRUE;
|
`LV: IsRFW = TRUE;
|
`LVx: IsRFW = TRUE;
|
`LVx: IsRFW = TRUE;
|
`CAS: IsRFW = TRUE;
|
`CAS: IsRFW = TRUE;
|
`AMO: IsRFW = TRUE;
|
`AMO: IsRFW = TRUE;
|
`CSRRW: IsRFW = TRUE;
|
`CSRRW: IsRFW = TRUE;
|
|
`AUIPC: IsRFW = TRUE;
|
`LUI: IsRFW = TRUE;
|
`LUI: IsRFW = TRUE;
|
default: IsRFW = FALSE;
|
default: IsRFW = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
| Line 3027... |
Line 3028... |
.cyc_i(cyc_o),
|
.cyc_i(cyc_o),
|
.stb_i(stb_o),
|
.stb_i(stb_o),
|
.ack_o(dc_ack),
|
.ack_o(dc_ack),
|
.we_i(we_o),
|
.we_i(we_o),
|
.adr_i(adr_o[15:0]),
|
.adr_i(adr_o[15:0]),
|
.dat_i(dat_o[31:0]),
|
.dat_i(dat_o[47:0]),
|
.cmpgrp(cr0[10:8]),
|
.cmpgrp(cr0[10:8]),
|
.freezePC(freezePC),
|
.freezePC(freezePC),
|
.regLR(regLR),
|
.regLR(regLR),
|
.thread_en(thread_en),
|
.thread_en(thread_en),
|
.insn0(insn0),
|
.insn0(insn0),
|
| Line 5429... |
Line 5430... |
iqentry_we[n] <= 8'h00;
|
iqentry_we[n] <= 8'h00;
|
iqentry_rfw[n] <= FALSE;
|
iqentry_rfw[n] <= FALSE;
|
iqentry_rmw[n] <= FALSE;
|
iqentry_rmw[n] <= FALSE;
|
iqentry_pc[n] <= RSTPC;
|
iqentry_pc[n] <= RSTPC;
|
iqentry_instr[n] <= `NOP_INSN;
|
iqentry_instr[n] <= `NOP_INSN;
|
iqentry_insln[n] <= 4'd4;
|
iqentry_insln[n] <= 3'd4;
|
iqentry_preload[n] <= FALSE;
|
iqentry_preload[n] <= FALSE;
|
iqentry_mem[n] <= FALSE;
|
iqentry_mem[n] <= FALSE;
|
iqentry_memndx[n] <= FALSE;
|
iqentry_memndx[n] <= FALSE;
|
iqentry_memissue[n] <= FALSE;
|
iqentry_memissue[n] <= FALSE;
|
iqentry_mem_islot[n] <= 3'd0;
|
iqentry_mem_islot[n] <= 3'd0;
|
| Line 5716... |
Line 5717... |
|
|
2'b00: ; // do nothing
|
2'b00: ; // do nothing
|
|
|
2'b01:
|
2'b01:
|
if (canq1) begin
|
if (canq1) begin
|
|
if (fetchbuf1_thrd)
|
|
seq_num1 <= seq_num1 + 5'd1;
|
|
else
|
|
seq_num <= seq_num + 5'd1;
|
|
if (fetchbuf1_rfw) begin
|
|
rf_source[ Rt1s ] <= { 1'b0, fetchbuf1_memld, tail0 }; // top bit indicates ALU/MEM bus
|
|
rf_v [Rt1s] <= `INV;
|
|
end
|
if (IsVector(fetchbuf1_instr) && SUP_VECTOR) begin
|
if (IsVector(fetchbuf1_instr) && SUP_VECTOR) begin
|
vqe1 <= vqe1 + 4'd1;
|
vqe1 <= vqe1 + 4'd1;
|
if (IsVCmprss(fetchbuf1_instr)) begin
|
if (IsVCmprss(fetchbuf1_instr)) begin
|
if (vm[fetchbuf1_instr[25:23]][vqe1])
|
if (vm[fetchbuf1_instr[25:23]][vqe1])
|
vqet1 <= vqet1 + 4'd1;
|
vqet1 <= vqet1 + 4'd1;
|
| Line 5727... |
Line 5736... |
else
|
else
|
vqet1 <= vqet1 + 4'd1;
|
vqet1 <= vqet1 + 4'd1;
|
if (vqe1 >= vl-2)
|
if (vqe1 >= vl-2)
|
nop_fetchbuf <= fetchbuf ? 4'b0100 : 4'b0001;
|
nop_fetchbuf <= fetchbuf ? 4'b0100 : 4'b0001;
|
enque1(tail0, fetchbuf1_thrd ? seq_num1 : seq_num, vqe1);
|
enque1(tail0, fetchbuf1_thrd ? seq_num1 : seq_num, vqe1);
|
if (fetchbuf1_thrd)
|
|
seq_num1 <= seq_num1 + 5'd1;
|
|
else
|
|
seq_num <= seq_num + 5'd1;
|
|
if (fetchbuf1_rfw) begin
|
|
rf_source[ Rt1s ] <= { 1'b0, fetchbuf1_memld, tail0 }; // top bit indicates ALU/MEM bus
|
|
rf_v [Rt1s] <= `INV;
|
|
end
|
|
if (canq2 && vqe1 < vl-2) begin
|
if (canq2 && vqe1 < vl-2) begin
|
vqe1 <= vqe1 + 4'd2;
|
vqe1 <= vqe1 + 4'd2;
|
if (IsVCmprss(fetchbuf1_instr)) begin
|
if (IsVCmprss(fetchbuf1_instr)) begin
|
if (vm[fetchbuf1_instr[25:23]][vqe1+6'd1])
|
if (vm[fetchbuf1_instr[25:23]][vqe1+6'd1])
|
vqet1 <= vqet1 + 4'd2;
|
vqet1 <= vqet1 + 4'd2;
|
end
|
end
|
else
|
else
|
vqet1 <= vqet1 + 4'd2;
|
vqet1 <= vqet1 + 4'd2;
|
enque1(tail1, fetchbuf1_thrd ? seq_num1 + 5'd1 : seq_num + 5'd1, vqe1 + 6'd1);
|
enque1(tail1, fetchbuf1_thrd ? seq_num1 + 5'd1 : seq_num + 5'd1, vqe1 + 6'd1);
|
|
// Override the earlier udpate
|
if (fetchbuf1_thrd)
|
if (fetchbuf1_thrd)
|
seq_num1 <= seq_num1 + 5'd2;
|
seq_num1 <= seq_num1 + 5'd2;
|
else
|
else
|
seq_num <= seq_num + 5'd2;
|
seq_num <= seq_num + 5'd2;
|
if (fetchbuf1_rfw) begin
|
|
rf_source[ Rt1s ] <= { 1'b0, fetchbuf1_memld, tail1 }; // top bit indicates ALU/MEM bus
|
|
rf_v [Rt1s] <= `INV;
|
|
end
|
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
enque1(tail0, fetchbuf1_thrd ? seq_num1 : seq_num, 6'd0);
|
enque1(tail0, fetchbuf1_thrd ? seq_num1 : seq_num, 6'd0);
|
if (fetchbuf1_thrd)
|
|
seq_num1 <= seq_num1 + 5'd1;
|
|
else
|
|
seq_num <= seq_num + 5'd1;
|
|
if (fetchbuf1_rfw) begin
|
|
rf_source[ Rt1s ] <= { 1'b0, fetchbuf1_memld, tail0 }; // top bit indicates ALU/MEM bus
|
|
rf_v [Rt1s] <= `INV;
|
|
end
|
|
end
|
end
|
end
|
end
|
|
|
2'b10:
|
2'b10:
|
if (canq1) begin
|
if (canq1) begin
|
| Line 7921... |
Line 7911... |
alu1_instr, alu1_bt, alu1_sourceid, alu1_pc);
|
alu1_instr, alu1_bt, alu1_sourceid, alu1_pc);
|
$display("%d %h %o 0 #", alu1_v, alu1_bus, alu1_id);
|
$display("%d %h %o 0 #", alu1_v, alu1_bus, alu1_id);
|
end
|
end
|
$display("FCU");
|
$display("FCU");
|
$display("%d %h %h %h %h #", fcu_v, fcu_bus, fcu_argI, fcu_argA, fcu_argB);
|
$display("%d %h %h %h %h #", fcu_v, fcu_bus, fcu_argI, fcu_argA, fcu_argB);
|
$display("%c %h %h #", fcu_branchmiss?"m":" ", fcu_sourceid, fcu_misspc);
|
$display("%c %h %h %h %h #", fcu_branchmiss?"m":" ", fcu_sourceid, fcu_misspc, fcu_nextpc, fcu_brdisp);
|
$display("Commit");
|
$display("Commit");
|
$display("0: %c %h %o %d #", commit0_v?"v":" ", commit0_bus, commit0_id, commit0_tgt[4:0]);
|
$display("0: %c %h %o %d #", commit0_v?"v":" ", commit0_bus, commit0_id, commit0_tgt[4:0]);
|
$display("1: %c %h %o %d #", commit1_v?"v":" ", commit1_bus, commit1_id, commit1_tgt[4:0]);
|
$display("1: %c %h %o %d #", commit1_v?"v":" ", commit1_bus, commit1_id, commit1_tgt[4:0]);
|
$display("instructions committed: %d ticks: %d ", I, tick);
|
$display("instructions committed: %d ticks: %d ", I, tick);
|
$display("Write merges: %d", wb_merges);
|
$display("Write merges: %d", wb_merges);
|
| Line 8265... |
Line 8255... |
// iqentry_Rc [nn] <= bus[`IB_RC];
|
// iqentry_Rc [nn] <= bus[`IB_RC];
|
// iqentry_Ra [nn] <= bus[`IB_RA];
|
// iqentry_Ra [nn] <= bus[`IB_RA];
|
iqentry_a0 [nn] <= bus[`IB_CONST];
|
iqentry_a0 [nn] <= bus[`IB_CONST];
|
iqentry_imm [nn] <= bus[`IB_IMM];
|
iqentry_imm [nn] <= bus[`IB_IMM];
|
// iqentry_insln[nn] <= bus[`IB_LN];
|
// iqentry_insln[nn] <= bus[`IB_LN];
|
|
if (iqentry_insln[nn] != bus[`IB_LN]) begin
|
|
$display("Insn length mismatch.");
|
|
$stop;
|
|
end
|
iqentry_jal [nn] <= bus[`IB_JAL];
|
iqentry_jal [nn] <= bus[`IB_JAL];
|
iqentry_ret [nn] <= bus[`IB_RET];
|
iqentry_ret [nn] <= bus[`IB_RET];
|
iqentry_irq [nn] <= bus[`IB_IRQ];
|
iqentry_irq [nn] <= bus[`IB_IRQ];
|
iqentry_brk [nn] <= bus[`IB_BRK];
|
iqentry_brk [nn] <= bus[`IB_BRK];
|
iqentry_rti [nn] <= bus[`IB_RTI];
|
iqentry_rti [nn] <= bus[`IB_RTI];
|
| Line 8297... |
Line 8291... |
iqentry_br [nn] <= bus[`IB_BR];
|
iqentry_br [nn] <= bus[`IB_BR];
|
iqentry_sync [nn] <= bus[`IB_SYNC];
|
iqentry_sync [nn] <= bus[`IB_SYNC];
|
iqentry_fsync[nn] <= bus[`IB_FSYNC];
|
iqentry_fsync[nn] <= bus[`IB_FSYNC];
|
iqentry_rfw [nn] <= bus[`IB_RFW];
|
iqentry_rfw [nn] <= bus[`IB_RFW];
|
iqentry_we [nn] <= bus[`IB_WE];
|
iqentry_we [nn] <= bus[`IB_WE];
|
|
/*
|
|
if (iqentry_vector[nn]) begin
|
|
iqentry_tgt[nn][RBIT:6] <= iqentry_Ra[nn][RBIT:6];
|
|
if (iqentry_Ra[nn][RBIT:6]==6'd0)
|
|
iqentry_tgt[nn][RBIT:6] = 6'd0;
|
|
else begin
|
|
if (iqentry_vcmprss[nn]) begin
|
|
if (vm[iqentry_instr[nn][25:23]][iqentry_Ra[nn][RBIT:6]])
|
|
if (qcnt==2'd2 && iqentry_vector[(nn-1)%QENTRIES] && iqentry_Ra[(nn-1)%QENTRIES][RBIT:6] >= 6'd1)
|
|
iqentry_tgt[nn][RBIT:6] <= iqentry_tgt[(nn-2)%QENTRIES][RBIT:6] + 6'd2;
|
|
else
|
|
iqentry_tgt[nn][RBIT:6] <= iqentry_tgt[(nn-1)%QENTRIES][RBIT:6] + 6'd1;
|
|
end
|
|
end
|
|
end
|
|
*/
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
task a1_vs;
|
task a1_vs;
|
