| Line 121... |
Line 121... |
//);
|
//);
|
assign clk = clk_i;
|
assign clk = clk_i;
|
|
|
wire dc_ack;
|
wire dc_ack;
|
wire acki = ack_i|dc_ack;
|
wire acki = ack_i|dc_ack;
|
wire [RBIT:0] Ra0, Ra1;
|
wire [RBIT:0] Ra0, Ra1, Ra2;
|
wire [RBIT:0] Rb0, Rb1;
|
wire [RBIT:0] Rb0, Rb1, Rb2;
|
wire [RBIT:0] Rc0, Rc1;
|
wire [RBIT:0] Rc0, Rc1, Rc2;
|
wire [RBIT:0] Rt0, Rt1;
|
wire [RBIT:0] Rt0, Rt1, Rt2;
|
wire [63:0] rfoa0,rfob0,rfoc0,rfoc0a;
|
wire [63:0] rfoa0,rfob0,rfoc0,rfoc0a;
|
wire [63:0] rfoa1,rfob1,rfoc1,rfoc1a;
|
wire [63:0] rfoa1,rfob1,rfoc1,rfoc1a;
|
|
wire [63:0] rfoa2,rfob2,rfoc2,rfoc2a;
|
`ifdef SUPPORT_SMT
|
`ifdef SUPPORT_SMT
|
wire [7:0] Ra0s = {Ra0[7:0]};
|
wire [7:0] Ra0s = {Ra0[7:0]};
|
wire [7:0] Ra1s = {Ra1[7:0]};
|
wire [7:0] Ra1s = {Ra1[7:0]};
|
|
wire [7:0] Ra2s = {Ra2[7:0]};
|
wire [7:0] Rb0s = {Rb0[7:0]};
|
wire [7:0] Rb0s = {Rb0[7:0]};
|
wire [7:0] Rb1s = {Rb1[7:0]};
|
wire [7:0] Rb1s = {Rb1[7:0]};
|
|
wire [7:0] Rb2s = {Rb2[7:0]};
|
wire [7:0] Rc0s = {Rc0[7:0]};
|
wire [7:0] Rc0s = {Rc0[7:0]};
|
wire [7:0] Rc1s = {Rc1[7:0]};
|
wire [7:0] Rc1s = {Rc1[7:0]};
|
|
wire [7:0] Rc2s = {Rc2[7:0]};
|
wire [7:0] Rt0s = {Rt0[7:0]};
|
wire [7:0] Rt0s = {Rt0[7:0]};
|
wire [7:0] Rt1s = {Rt1[7:0]};
|
wire [7:0] Rt1s = {Rt1[7:0]};
|
|
wire [7:0] Rt2s = {Rt2[7:0]};
|
`else
|
`else
|
wire [6:0] Ra0s = {Ra0[7],Ra0[5:0]};
|
wire [6:0] Ra0s = {Ra0[7],Ra0[5:0]};
|
wire [6:0] Ra1s = {Ra1[7],Ra1[5:0]};
|
wire [6:0] Ra1s = {Ra1[7],Ra1[5:0]};
|
|
wire [6:0] Ra2s = {Ra2[7],Ra2[5:0]};
|
wire [6:0] Rb0s = {Rb0[7],Rb0[5:0]};
|
wire [6:0] Rb0s = {Rb0[7],Rb0[5:0]};
|
wire [6:0] Rb1s = {Rb1[7],Rb1[5:0]};
|
wire [6:0] Rb1s = {Rb1[7],Rb1[5:0]};
|
|
wire [6:0] Rb2s = {Rb2[7],Rb2[5:0]};
|
wire [6:0] Rc0s = {Rc0[7],Rc0[5:0]};
|
wire [6:0] Rc0s = {Rc0[7],Rc0[5:0]};
|
wire [6:0] Rc1s = {Rc1[7],Rc1[5:0]};
|
wire [6:0] Rc1s = {Rc1[7],Rc1[5:0]};
|
|
wire [6:0] Rc2s = {Rc2[7],Rc2[5:0]};
|
wire [6:0] Rt0s = {Rt0[7],Rt0[5:0]};
|
wire [6:0] Rt0s = {Rt0[7],Rt0[5:0]};
|
wire [6:0] Rt1s = {Rt1[7],Rt1[5:0]};
|
wire [6:0] Rt1s = {Rt1[7],Rt1[5:0]};
|
|
wire [6:0] Rt2s = {Rt2[7],Rt2[5:0]};
|
/*
|
/*
|
wire [5:0] Ra0s = {Ra0[5:0]};
|
wire [5:0] Ra0s = {Ra0[5:0]};
|
wire [5:0] Ra1s = {Ra1[5:0]};
|
wire [5:0] Ra1s = {Ra1[5:0]};
|
wire [5:0] Rb0s = {Rb0[5:0]};
|
wire [5:0] Rb0s = {Rb0[5:0]};
|
wire [5:0] Rb1s = {Rb1[5:0]};
|
wire [5:0] Rb1s = {Rb1[5:0]};
|
| Line 182... |
Line 191... |
reg rdvq; // accumulated read violation
|
reg rdvq; // accumulated read violation
|
reg errq; // accumulated err_i input status
|
reg errq; // accumulated err_i input status
|
reg exvq;
|
reg exvq;
|
|
|
// Vector
|
// Vector
|
reg [5:0] vqe0, vqe1; // vector element being queued
|
reg [5:0] vqe0, vqe1, vqe2; // vector element being queued
|
reg [5:0] vqet0, vqet1;
|
reg [5:0] vqet0, vqet1, vqet2;
|
reg [7:0] vl; // vector length
|
reg [7:0] vl; // vector length
|
reg [63:0] vm [0:7]; // vector mask registers
|
reg [63:0] vm [0:7]; // vector mask registers
|
reg [1:0] m2;
|
reg [1:0] m2;
|
|
|
reg [31:0] wb_merges;
|
reg [31:0] wb_merges;
|
| Line 391... |
Line 400... |
// Only need enough bits in the seqnence number to cover the instructions in
|
// Only need enough bits in the seqnence number to cover the instructions in
|
// the queue plus an extra count for skipping on branch misses. In this case
|
// the queue plus an extra count for skipping on branch misses. In this case
|
// that would be four bits minimum (count 0 to 8).
|
// that would be four bits minimum (count 0 to 8).
|
reg [31:0] seq_num;
|
reg [31:0] seq_num;
|
reg [31:0] seq_num1;
|
reg [31:0] seq_num1;
|
|
reg [31:0] seq_num2;
|
wire [63:0] rdat0,rdat1,rdat2;
|
wire [63:0] rdat0,rdat1,rdat2;
|
reg [63:0] xdati;
|
reg [63:0] xdati;
|
|
|
reg canq1, canq2;
|
reg canq1, canq2, canq3;
|
reg queued1;
|
reg queued1;
|
reg queued2;
|
reg queued2;
|
|
reg queued3;
|
reg queuedNop;
|
reg queuedNop;
|
|
|
reg [47:0] codebuf[0:63];
|
reg [47:0] codebuf[0:63];
|
reg [QENTRIES-1:0] setpred;
|
reg [QENTRIES-1:0] setpred;
|
|
|
| Line 563... |
Line 574... |
wire fetchbuf1_v;
|
wire fetchbuf1_v;
|
wire fetchbuf1_thrd;
|
wire fetchbuf1_thrd;
|
wire fetchbuf1_mem;
|
wire fetchbuf1_mem;
|
wire fetchbuf1_memld;
|
wire fetchbuf1_memld;
|
wire fetchbuf1_rfw;
|
wire fetchbuf1_rfw;
|
|
wire [47:0] fetchbuf2_instr;
|
|
wire [2:0] fetchbuf2_insln;
|
|
wire [`ABITS] fetchbuf2_pc;
|
|
wire fetchbuf2_v;
|
|
wire fetchbuf2_thrd;
|
|
wire fetchbuf2_mem;
|
|
wire fetchbuf2_memld;
|
|
wire fetchbuf2_rfw;
|
|
|
wire [47:0] fetchbufA_instr;
|
wire [47:0] fetchbufA_instr;
|
wire [`ABITS] fetchbufA_pc;
|
wire [`ABITS] fetchbufA_pc;
|
wire fetchbufA_v;
|
wire fetchbufA_v;
|
wire [47:0] fetchbufB_instr;
|
wire [47:0] fetchbufB_instr;
|
| Line 576... |
Line 595... |
wire [`ABITS] fetchbufC_pc;
|
wire [`ABITS] fetchbufC_pc;
|
wire fetchbufC_v;
|
wire fetchbufC_v;
|
wire [47:0] fetchbufD_instr;
|
wire [47:0] fetchbufD_instr;
|
wire [`ABITS] fetchbufD_pc;
|
wire [`ABITS] fetchbufD_pc;
|
wire fetchbufD_v;
|
wire fetchbufD_v;
|
|
wire [47:0] fetchbufE_instr;
|
|
wire [`ABITS] fetchbufE_pc;
|
|
wire fetchbufE_v;
|
|
wire [47:0] fetchbufF_instr;
|
|
wire [`ABITS] fetchbufF_pc;
|
|
wire fetchbufF_v;
|
|
|
//reg did_branchback0;
|
//reg did_branchback0;
|
//reg did_branchback1;
|
//reg did_branchback1;
|
|
|
reg id1_v;
|
reg id1_v;
|
| Line 889... |
Line 914... |
reg [37:0] L1_adr, L2_adr;
|
reg [37:0] L1_adr, L2_adr;
|
reg [287:0] L2_rdat;
|
reg [287:0] L2_rdat;
|
wire [287:0] L2_dato;
|
wire [287:0] L2_dato;
|
reg L2_xsel;
|
reg L2_xsel;
|
|
|
FT64_regfile2w6r_oc #(.RBIT(RBIT)) urf1
|
generate begin : gRegfileInst
|
|
if (`WAYS > 2) begin : gb1
|
|
FT64_regfile2w9r_oc #(.RBIT(RBIT)) urf1
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.clk4x(clk4x),
|
.clk4x(clk4x),
|
.wr0(commit0_v),
|
.wr0(commit0_v),
|
.wr1(commit1_v),
|
.wr1(commit1_v),
|
| Line 905... |
Line 932... |
.i1(commit1_bus),
|
.i1(commit1_bus),
|
.rclk(~clk),
|
.rclk(~clk),
|
.ra0(Ra0),
|
.ra0(Ra0),
|
.ra1(Rb0),
|
.ra1(Rb0),
|
.ra2(Rc0),
|
.ra2(Rc0),
|
|
.o0(rfoa0),
|
|
.o1(rfob0),
|
|
.o2(rfoc0a),
|
.ra3(Ra1),
|
.ra3(Ra1),
|
.ra4(Rb1),
|
.ra4(Rb1),
|
.ra5(Rc1),
|
.ra5(Rc1),
|
|
.o3(rfoa1),
|
|
.o4(rfob1),
|
|
.o5(rfoc1a),
|
|
.ra6(Ra2),
|
|
.ra7(Rb2),
|
|
.ra8(Rc2),
|
|
.o6(rfoa2),
|
|
.o7(rfob2),
|
|
.o8(rfoc2a)
|
|
);
|
|
assign rfoc0 = Rc0[11:6]==6'h3F ? vm[Rc0[2:0]] : rfoc0a;
|
|
assign rfoc1 = Rc1[11:6]==6'h3F ? vm[Rc1[2:0]] : rfoc1a;
|
|
assign rfoc2 = Rc2[11:6]==6'h3F ? vm[Rc2[2:0]] : rfoc2a;
|
|
end
|
|
else if (`WAYS > 1) begin : gb1
|
|
FT64_regfile2w6r_oc #(.RBIT(RBIT)) urf1
|
|
(
|
|
.clk(clk),
|
|
.clk4x(clk4x),
|
|
.wr0(commit0_v),
|
|
.wr1(commit1_v),
|
|
.we0(commit0_we),
|
|
.we1(commit1_we),
|
|
.wa0(commit0_tgt),
|
|
.wa1(commit1_tgt),
|
|
.i0(commit0_bus),
|
|
.i1(commit1_bus),
|
|
.rclk(~clk),
|
|
.ra0(Ra0),
|
|
.ra1(Rb0),
|
|
.ra2(Rc0),
|
.o0(rfoa0),
|
.o0(rfoa0),
|
.o1(rfob0),
|
.o1(rfob0),
|
.o2(rfoc0a),
|
.o2(rfoc0a),
|
|
.ra3(Ra1),
|
|
.ra4(Rb1),
|
|
.ra5(Rc1),
|
.o3(rfoa1),
|
.o3(rfoa1),
|
.o4(rfob1),
|
.o4(rfob1),
|
.o5(rfoc1a)
|
.o5(rfoc1a)
|
);
|
);
|
assign rfoc0 = Rc0[11:6]==6'h3F ? vm[Rc0[2:0]] : rfoc0a;
|
assign rfoc0 = Rc0[11:6]==6'h3F ? vm[Rc0[2:0]] : rfoc0a;
|
assign rfoc1 = Rc1[11:6]==6'h3F ? vm[Rc1[2:0]] : rfoc1a;
|
assign rfoc1 = Rc1[11:6]==6'h3F ? vm[Rc1[2:0]] : rfoc1a;
|
|
end
|
|
else begin : gb1
|
|
FT64_regfile1w3r_oc #(.RBIT(RBIT)) urf1
|
|
(
|
|
.clk(clk),
|
|
.wr0(commit0_v),
|
|
.we0(commit0_we),
|
|
.wa0(commit0_tgt),
|
|
.i0(commit0_bus),
|
|
.rclk(~clk),
|
|
.ra0(Ra0),
|
|
.ra1(Rb0),
|
|
.ra2(Rc0),
|
|
.o0(rfoa0),
|
|
.o1(rfob0),
|
|
.o2(rfoc0a)
|
|
);
|
|
end
|
|
assign rfoc0 = Rc0[11:6]==6'h3F ? vm[Rc0[2:0]] : rfoc0a;
|
|
end
|
|
endgenerate
|
|
|
function [3:0] fnInsLength;
|
function [3:0] fnInsLength;
|
input [47:0] ins;
|
input [47:0] ins;
|
|
`ifdef SUPPORT_DCI
|
if (ins[`INSTRUCTION_OP]==`CMPRSSD)
|
if (ins[`INSTRUCTION_OP]==`CMPRSSD)
|
fnInsLength = 4'd2;
|
fnInsLength = 4'd2;
|
else
|
else
|
|
`endif
|
case(ins[7:6])
|
case(ins[7:6])
|
2'd0: fnInsLength = 4'd4;
|
2'd0: fnInsLength = 4'd4;
|
2'd1: fnInsLength = 4'd6;
|
2'd1: fnInsLength = 4'd6;
|
default: fnInsLength = 4'd2;
|
default: fnInsLength = 4'd2;
|
endcase
|
endcase
|
| Line 1030... |
Line 1117... |
);
|
);
|
|
|
wire predict_taken;
|
wire predict_taken;
|
wire predict_taken0;
|
wire predict_taken0;
|
wire predict_taken1;
|
wire predict_taken1;
|
|
wire predict_taken2;
|
wire predict_takenA;
|
wire predict_takenA;
|
wire predict_takenB;
|
wire predict_takenB;
|
wire predict_takenC;
|
wire predict_takenC;
|
wire predict_takenD;
|
wire predict_takenD;
|
|
wire predict_takenE;
|
|
wire predict_takenF;
|
wire predict_takenA1;
|
wire predict_takenA1;
|
wire predict_takenB1;
|
wire predict_takenB1;
|
wire predict_takenC1;
|
wire predict_takenC1;
|
wire predict_takenD1;
|
wire predict_takenD1;
|
|
|
wire [`ABITS] btgtA, btgtB, btgtC, btgtD;
|
wire [`ABITS] btgtA, btgtB, btgtC, btgtD, btgtE, btgtF;
|
wire btbwr0 = iqentry_v[head0] && iqentry_done[head0] &&
|
wire btbwr0 = iqentry_v[head0] && iqentry_done[head0] &&
|
(
|
(
|
iqentry_jal[head0] ||
|
iqentry_jal[head0] ||
|
iqentry_brk[head0] ||
|
iqentry_brk[head0] ||
|
iqentry_rti[head0]);
|
iqentry_rti[head0]);
|
|
generate begin: gbtbvar
|
|
if (`WAYS > 1) begin
|
wire btbwr1 = iqentry_v[head1] && iqentry_done[head1] &&
|
wire btbwr1 = iqentry_v[head1] && iqentry_done[head1] &&
|
(
|
(
|
iqentry_jal[head1] ||
|
iqentry_jal[head1] ||
|
iqentry_brk[head1] ||
|
iqentry_brk[head1] ||
|
iqentry_rti[head1]);
|
iqentry_rti[head1]);
|
|
end
|
|
end
|
|
endgenerate
|
|
|
wire fcu_clk;
|
wire fcu_clk;
|
`ifdef FCU_ENH
|
`ifdef FCU_ENH
|
//BUFGCE ufcuclk
|
//BUFGCE ufcuclk
|
//(
|
//(
|
| Line 1062... |
Line 1157... |
// .O(fcu_clk)
|
// .O(fcu_clk)
|
//);
|
//);
|
`endif
|
`endif
|
assign fcu_clk = clk_i;
|
assign fcu_clk = clk_i;
|
|
|
|
generate begin: gBTBInst
|
|
if (`WAYS > 2) begin
|
`ifdef FCU_ENH
|
`ifdef FCU_ENH
|
FT64_BTB ubtb1
|
FT64_BTB ubtb1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.wclk(fcu_clk),
|
.wclk(fcu_clk),
|
| Line 1080... |
Line 1177... |
.btgtB(btgtB),
|
.btgtB(btgtB),
|
.pcC(fetchbufC_pc),
|
.pcC(fetchbufC_pc),
|
.btgtC(btgtC),
|
.btgtC(btgtC),
|
.pcD(fetchbufD_pc),
|
.pcD(fetchbufD_pc),
|
.btgtD(btgtD),
|
.btgtD(btgtD),
|
|
.pcE(fetchbufE_pc),
|
|
.btgtE(btgtE),
|
|
.pcF(fetchbufF_pc),
|
|
.btgtF(btgtF),
|
.npcA(BRKPC),
|
.npcA(BRKPC),
|
.npcB(BRKPC),
|
.npcB(BRKPC),
|
.npcC(BRKPC),
|
.npcC(BRKPC),
|
.npcD(BRKPC)
|
.npcD(BRKPC),
|
|
.npcE(BRKPC),
|
|
.npcF(BRKPC)
|
);
|
);
|
`else
|
`else
|
// Branch tergets are picked up by fetchbuf logic and need to be present.
|
// Branch tergets are picked up by fetchbuf logic and need to be present.
|
// Without a target predictor they are just set to the reset address.
|
// Without a target predictor they are just set to the reset address.
|
// This virtually guarentees a miss.
|
// This virtually guarentees a miss.
|
assign btgtA = RSTPC;
|
assign btgtA = RSTPC;
|
assign btgtB = RSTPC;
|
assign btgtB = RSTPC;
|
assign btgtC = RSTPC;
|
assign btgtC = RSTPC;
|
assign btgtD = RSTPC;
|
assign btgtD = RSTPC;
|
|
assign btgtE = RSTPC;
|
|
assign btgtF = RSTPC;
|
`endif
|
`endif
|
|
end
|
|
else if (`WAYS > 1) begin
|
|
`ifdef FCU_ENH
|
|
FT64_BTB ubtb1
|
|
(
|
|
.rst(rst),
|
|
.wclk(fcu_clk),
|
|
.wr(btbwr0 | btbwr1),
|
|
.wadr(btbwr0 ? iqentry_pc[head0] : iqentry_pc[head1]),
|
|
.wdat(btbwr0 ? iqentry_a0[head0] : iqentry_a0[head1]),
|
|
.valid(btbwr0 ? iqentry_bt[head0] & iqentry_v[head0] : iqentry_bt[head1] & iqentry_v[head1]),
|
|
.rclk(~clk),
|
|
.pcA(fetchbufA_pc),
|
|
.btgtA(btgtA),
|
|
.pcB(fetchbufB_pc),
|
|
.btgtB(btgtB),
|
|
.pcC(fetchbufC_pc),
|
|
.btgtC(btgtC),
|
|
.pcD(fetchbufD_pc),
|
|
.btgtD(btgtD),
|
|
.pcE(32'd0),
|
|
.btgtE(),
|
|
.pcF(32'd0),
|
|
.btgtF(),
|
|
.npcA(BRKPC),
|
|
.npcB(BRKPC),
|
|
.npcC(BRKPC),
|
|
.npcD(BRKPC),
|
|
.npcE(BRKPC),
|
|
.npcF(BRKPC)
|
|
);
|
|
`else
|
|
// Branch tergets are picked up by fetchbuf logic and need to be present.
|
|
// Without a target predictor they are just set to the reset address.
|
|
// This virtually guarentees a miss.
|
|
assign btgtA = RSTPC;
|
|
assign btgtB = RSTPC;
|
|
assign btgtC = RSTPC;
|
|
assign btgtD = RSTPC;
|
|
`endif
|
|
end
|
|
else begin
|
|
`ifdef FCU_ENH
|
|
FT64_BTB ubtb1
|
|
(
|
|
.rst(rst),
|
|
.wclk(fcu_clk),
|
|
.wr(btbwr0),
|
|
.wadr(iqentry_pc[head0]),
|
|
.wdat(iqentry_a0[head0]),
|
|
.valid(iqentry_bt[head0] & iqentry_v[head0]),
|
|
.rclk(~clk),
|
|
.pcA(fetchbufA_pc),
|
|
.btgtA(btgtA),
|
|
.pcB(fetchbufB_pc),
|
|
.btgtB(btgtB),
|
|
.pcC(32'd0),
|
|
.btgtC(),
|
|
.pcD(32'd0),
|
|
.btgtD(),
|
|
.pcE(32'd0),
|
|
.btgtE(),
|
|
.pcF(32'd0),
|
|
.btgtF(),
|
|
.npcA(BRKPC),
|
|
.npcB(BRKPC),
|
|
.npcC(BRKPC),
|
|
.npcD(BRKPC),
|
|
.npcE(BRKPC),
|
|
.npcF(BRKPC)
|
|
);
|
|
`else
|
|
// Branch tergets are picked up by fetchbuf logic and need to be present.
|
|
// Without a target predictor they are just set to the reset address.
|
|
// This virtually guarentees a miss.
|
|
assign btgtA = RSTPC;
|
|
assign btgtB = RSTPC;
|
|
`endif
|
|
end
|
|
end
|
|
endgenerate
|
|
|
|
generate begin: gBPInst
|
|
if (`WAYS > 2) begin
|
`ifdef FCU_ENH
|
`ifdef FCU_ENH
|
FT64_BranchPredictor ubp1
|
FT64_BranchPredictor ubp1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.clk(fcu_clk),
|
.clk(fcu_clk),
|
| Line 1107... |
Line 1295... |
.xisBranch1(iqentry_br[head1] & commit1_v),
|
.xisBranch1(iqentry_br[head1] & commit1_v),
|
.pcA(fetchbufA_pc),
|
.pcA(fetchbufA_pc),
|
.pcB(fetchbufB_pc),
|
.pcB(fetchbufB_pc),
|
.pcC(fetchbufC_pc),
|
.pcC(fetchbufC_pc),
|
.pcD(fetchbufD_pc),
|
.pcD(fetchbufD_pc),
|
|
.pcE(fetchbufE_pc),
|
|
.pcF(fetchbufF_pc),
|
.xpc0(iqentry_pc[head0]),
|
.xpc0(iqentry_pc[head0]),
|
.xpc1(iqentry_pc[head1]),
|
.xpc1(iqentry_pc[head1]),
|
.takb0(commit0_v & iqentry_takb[head0]),
|
.takb0(commit0_v & iqentry_takb[head0]),
|
.takb1(commit1_v & iqentry_takb[head1]),
|
.takb1(commit1_v & iqentry_takb[head1]),
|
.predict_takenA(predict_takenA),
|
.predict_takenA(predict_takenA),
|
.predict_takenB(predict_takenB),
|
.predict_takenB(predict_takenB),
|
.predict_takenC(predict_takenC),
|
.predict_takenC(predict_takenC),
|
.predict_takenD(predict_takenD)
|
.predict_takenD(predict_takenD),
|
|
.predict_takenE(predict_takenE),
|
|
.predict_takenF(predict_takenF)
|
);
|
);
|
`else
|
`else
|
// Predict based on sign of displacement
|
// Predict based on sign of displacement
|
assign predict_takenA = fetchbufA_instr[31];
|
assign predict_takenA = fetchbufA_instr[31];
|
assign predict_takenB = fetchbufB_instr[31];
|
assign predict_takenB = fetchbufB_instr[31];
|
assign predict_takenC = fetchbufC_instr[31];
|
assign predict_takenC = fetchbufC_instr[31];
|
assign predict_takenD = fetchbufD_instr[31];
|
assign predict_takenD = fetchbufD_instr[31];
|
|
assign predict_takenE = fetchbufE_instr[31];
|
|
assign predict_takenF = fetchbufF_instr[31];
|
`endif
|
`endif
|
|
end
|
|
else if (`WAYS > 1) begin
|
|
`ifdef FCU_ENH
|
|
FT64_BranchPredictor ubp1
|
|
(
|
|
.rst(rst),
|
|
.clk(fcu_clk),
|
|
.en(bpe),
|
|
.xisBranch0(iqentry_br[head0] & commit0_v),
|
|
.xisBranch1(iqentry_br[head1] & commit1_v),
|
|
.pcA(fetchbufA_pc),
|
|
.pcB(fetchbufB_pc),
|
|
.pcC(fetchbufC_pc),
|
|
.pcD(fetchbufD_pc),
|
|
.pcE(32'd0),
|
|
.pcF(32'd0),
|
|
.xpc0(iqentry_pc[head0]),
|
|
.xpc1(iqentry_pc[head1]),
|
|
.takb0(commit0_v & iqentry_takb[head0]),
|
|
.takb1(commit1_v & iqentry_takb[head1]),
|
|
.predict_takenA(predict_takenA),
|
|
.predict_takenB(predict_takenB),
|
|
.predict_takenC(predict_takenC),
|
|
.predict_takenD(predict_takenD),
|
|
.predict_takenE(),
|
|
.predict_takenF()
|
|
);
|
|
`else
|
|
// Predict based on sign of displacement
|
|
assign predict_takenA = fetchbufA_instr[31];
|
|
assign predict_takenB = fetchbufB_instr[31];
|
|
assign predict_takenC = fetchbufC_instr[31];
|
|
assign predict_takenD = fetchbufD_instr[31];
|
|
`endif
|
|
end
|
|
else begin
|
|
`ifdef FCU_ENH
|
|
FT64_BranchPredictor ubp1
|
|
(
|
|
.rst(rst),
|
|
.clk(fcu_clk),
|
|
.en(bpe),
|
|
.xisBranch0(iqentry_br[head0] & commit0_v),
|
|
.xisBranch1(1'b0),
|
|
.pcA(fetchbufA_pc),
|
|
.pcB(fetchbufB_pc),
|
|
.pcC(32'd0),
|
|
.pcD(32'd0),
|
|
.pcE(32'd0),
|
|
.pcF(32'd0),
|
|
.xpc0(iqentry_pc[head0]),
|
|
.xpc1(32'd0),
|
|
.takb0(commit0_v & iqentry_takb[head0]),
|
|
.takb1(1'b0),
|
|
.predict_takenA(predict_takenA),
|
|
.predict_takenB(predict_takenB),
|
|
.predict_takenC(),
|
|
.predict_takenD(),
|
|
.predict_takenE(),
|
|
.predict_takenF()
|
|
);
|
|
`else
|
|
// Predict based on sign of displacement
|
|
assign predict_takenA = fetchbufA_instr[31];
|
|
assign predict_takenB = fetchbufB_instr[31];
|
|
`endif
|
|
end
|
|
end
|
|
endgenerate
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Debug
|
// Debug
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
`ifdef SUPPORT_DBG
|
`ifdef SUPPORT_DBG
|
| Line 1414... |
Line 1677... |
assign rdat2 = dram2_unc ? xdati : dc2_out;
|
assign rdat2 = dram2_unc ? xdati : dc2_out;
|
|
|
reg preload;
|
reg preload;
|
reg [1:0] dccnt;
|
reg [1:0] dccnt;
|
wire dhit0, dhit1, dhit2;
|
wire dhit0, dhit1, dhit2;
|
|
wire dhit0a, dhit1a, dhit2a;
|
wire dhit00, dhit10, dhit20;
|
wire dhit00, dhit10, dhit20;
|
wire dhit01, dhit11, dhit21;
|
wire dhit01, dhit11, dhit21;
|
reg [`ABITS] dc_wadr;
|
reg [`ABITS] dc_wadr;
|
reg [63:0] dc_wdat;
|
reg [63:0] dc_wdat;
|
reg isStore;
|
reg isStore;
|
|
|
|
// If the data is in the write buffer, give the buffer a chance to
|
|
// write out the data before trying to load from the cache.
|
|
reg wb_hit0, wb_hit1, wb_hit2;
|
|
always @*
|
|
begin
|
|
wb_hit0 <= FALSE;
|
|
wb_hit1 <= FALSE;
|
|
wb_hit2 <= FALSE;
|
|
for (n = 0; n < `WB_DEPTH; n = n + 1) begin
|
|
if (wb_v[n] && wb_addr[n][31:3]==dram0_addr[31:3])
|
|
wb_hit0 <= TRUE;
|
|
if (`NUM_MEM > 1 && wb_addr[n][31:3]==dram1_addr[31:3])
|
|
wb_hit1 <= TRUE;
|
|
if (`NUM_MEM > 2 && wb_addr[n][31:3]==dram2_addr[31:3])
|
|
wb_hit2 <= TRUE;
|
|
end
|
|
end
|
|
|
|
assign dhit0 = dhit0a & !wb_hit0;
|
|
assign dhit1 = dhit1a & !wb_hit1;
|
|
assign dhit2 = dhit2a & !wb_hit2;
|
|
wire whit0, whit1, whit2;
|
|
|
FT64_dcache udc0
|
FT64_dcache udc0
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.wclk(clk),
|
.wclk(clk),
|
.wr((bstate==B2d && ack_i)||((bstate==B1||(bstate==B19 && isStore)) && dhit0)),
|
.wr((bstate==B2d && ack_i)||((bstate==B1||(bstate==B19 && isStore)) && whit0)),
|
.sel(sel_o),
|
.sel(sel_o),
|
.wadr({pcr[5:0],adr_o}),
|
.wadr({pcr[5:0],adr_o}),
|
|
.whit(whit0),
|
.i(bstate==B2d ? dat_i : dat_o),
|
.i(bstate==B2d ? dat_i : dat_o),
|
.rclk(clk),
|
.rclk(clk),
|
.rdsize(dram0_memsize),
|
.rdsize(dram0_memsize),
|
.radr({pcr[5:0],dram0_addr}),
|
.radr({pcr[5:0],dram0_addr}),
|
.o(dc0_out),
|
.o(dc0_out),
|
.hit(),
|
.hit(),
|
.hit0(dhit0),
|
.hit0(dhit0a),
|
.hit1()
|
.hit1()
|
);
|
);
|
generate begin : gDCacheInst
|
generate begin : gDCacheInst
|
if (`NUM_MEM > 1) begin
|
if (`NUM_MEM > 1) begin
|
FT64_dcache udc1
|
FT64_dcache udc1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.wclk(clk),
|
.wclk(clk),
|
.wr((bstate==B2d && ack_i)||((bstate==B1||(bstate==B19 && isStore)) && dhit1)),
|
.wr((bstate==B2d && ack_i)||((bstate==B1||(bstate==B19 && isStore)) && whit1)),
|
.sel(sel_o),
|
.sel(sel_o),
|
.wadr({pcr[5:0],adr_o}),
|
.wadr({pcr[5:0],adr_o}),
|
|
.whit(whit1),
|
.i(bstate==B2d ? dat_i : dat_o),
|
.i(bstate==B2d ? dat_i : dat_o),
|
.rclk(clk),
|
.rclk(clk),
|
.rdsize(dram1_memsize),
|
.rdsize(dram1_memsize),
|
.radr({pcr[5:0],dram1_addr}),
|
.radr({pcr[5:0],dram1_addr}),
|
.o(dc1_out),
|
.o(dc1_out),
|
.hit(),
|
.hit(),
|
.hit0(dhit1),
|
.hit0(dhit1a),
|
.hit1()
|
.hit1()
|
);
|
);
|
end
|
end
|
if (`NUM_MEM > 2) begin
|
if (`NUM_MEM > 2) begin
|
FT64_dcache udc2
|
FT64_dcache udc2
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.wclk(clk),
|
.wclk(clk),
|
.wr((bstate==B2d && ack_i)||((bstate==B1||(bstate==B19 && isStore)) && dhit2)),
|
.wr((bstate==B2d && ack_i)||((bstate==B1||(bstate==B19 && isStore)) && whit2)),
|
.sel(sel_o),
|
.sel(sel_o),
|
.wadr({pcr[5:0],adr_o}),
|
.wadr({pcr[5:0],adr_o}),
|
|
.whit(whit2),
|
.i(bstate==B2d ? dat_i : dat_o),
|
.i(bstate==B2d ? dat_i : dat_o),
|
.rclk(clk),
|
.rclk(clk),
|
.rdsize(dram2_memsize),
|
.rdsize(dram2_memsize),
|
.radr({pcr[5:0],dram2_addr}),
|
.radr({pcr[5:0],dram2_addr}),
|
.o(dc2_out),
|
.o(dc2_out),
|
.hit(),
|
.hit(),
|
.hit0(dhit2),
|
.hit0(dhit2a),
|
.hit1()
|
.hit1()
|
);
|
);
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
| Line 3012... |
Line 3302... |
//
|
//
|
assign fetchbuf0_mem = IsMem(fetchbuf0_instr);
|
assign fetchbuf0_mem = IsMem(fetchbuf0_instr);
|
assign fetchbuf0_memld = IsMem(fetchbuf0_instr) & IsLoad(fetchbuf0_instr);
|
assign fetchbuf0_memld = IsMem(fetchbuf0_instr) & IsLoad(fetchbuf0_instr);
|
assign fetchbuf0_rfw = IsRFW(fetchbuf0_instr,vqe0,vl,fetchbuf0_thrd);
|
assign fetchbuf0_rfw = IsRFW(fetchbuf0_instr,vqe0,vl,fetchbuf0_thrd);
|
|
|
|
generate begin: gFetchbufDec
|
|
if (`WAYS > 1) begin
|
assign fetchbuf1_mem = IsMem(fetchbuf1_instr);
|
assign fetchbuf1_mem = IsMem(fetchbuf1_instr);
|
assign fetchbuf1_memld = IsMem(fetchbuf1_instr) & IsLoad(fetchbuf1_instr);
|
assign fetchbuf1_memld = IsMem(fetchbuf1_instr) & IsLoad(fetchbuf1_instr);
|
assign fetchbuf1_rfw = IsRFW(fetchbuf1_instr,vqe1,vl,fetchbuf1_thrd);
|
assign fetchbuf1_rfw = IsRFW(fetchbuf1_instr,vqe1,vl,fetchbuf1_thrd);
|
|
end
|
|
if (`WAYS > 2) begin
|
|
assign fetchbuf2_mem = IsMem(fetchbuf2_instr);
|
|
assign fetchbuf2_memld = IsMem(fetchbuf2_instr) & IsLoad(fetchbuf2_instr);
|
|
assign fetchbuf2_rfw = IsRFW(fetchbuf2_instr,vqe2,vl,fetchbuf2_thrd);
|
|
end
|
|
end
|
|
endgenerate
|
|
|
|
generate begin : gFetchbufInst
|
|
if (`WAYS > 2) begin : gb1
|
|
FT64_fetchbuf_x3 #(AMSB,RSTPC) ufb1
|
|
(
|
|
.rst(rst),
|
|
.clk4x(clk4x),
|
|
.clk(clk),
|
|
.fcu_clk(fcu_clk),
|
|
.cs_i(adr_o[31:16]==16'hFFFF),
|
|
.cyc_i(cyc_o),
|
|
.stb_i(stb_o),
|
|
.ack_o(dc_ack),
|
|
.we_i(we_o),
|
|
.adr_i(adr_o[15:0]),
|
|
.dat_i(dat_o[47:0]),
|
|
.cmpgrp(cr0[10:8]),
|
|
.freezePC(freezePC),
|
|
.regLR(regLR),
|
|
.thread_en(thread_en),
|
|
.insn0(insn0),
|
|
.insn1(insn1),
|
|
.insn1(insn2),
|
|
.phit(phit),
|
|
.threadx(threadx),
|
|
.branchmiss(branchmiss),
|
|
.misspc(misspc),
|
|
.branchmiss_thrd(branchmiss_thrd),
|
|
.predict_takenA(predict_takenA),
|
|
.predict_takenB(predict_takenB),
|
|
.predict_takenC(predict_takenC),
|
|
.predict_takenD(predict_takenD),
|
|
.predict_takenE(predict_takenE),
|
|
.predict_takenF(predict_takenF),
|
|
.predict_taken0(predict_taken0),
|
|
.predict_taken1(predict_taken1),
|
|
.predict_taken1(predict_taken2),
|
|
.queued1(queued1),
|
|
.queued2(queued2),
|
|
.queued2(queued3),
|
|
.queuedNop(queuedNop),
|
|
.pc0(pc0),
|
|
.pc1(pc1),
|
|
.fetchbuf(fetchbuf),
|
|
.fetchbufA_v(fetchbufA_v),
|
|
.fetchbufB_v(fetchbufB_v),
|
|
.fetchbufC_v(fetchbufC_v),
|
|
.fetchbufD_v(fetchbufD_v),
|
|
.fetchbufD_v(fetchbufE_v),
|
|
.fetchbufD_v(fetchbufF_v),
|
|
.fetchbufA_pc(fetchbufA_pc),
|
|
.fetchbufB_pc(fetchbufB_pc),
|
|
.fetchbufC_pc(fetchbufC_pc),
|
|
.fetchbufD_pc(fetchbufD_pc),
|
|
.fetchbufD_pc(fetchbufE_pc),
|
|
.fetchbufD_pc(fetchbufF_pc),
|
|
.fetchbufA_instr(fetchbufA_instr),
|
|
.fetchbufB_instr(fetchbufB_instr),
|
|
.fetchbufC_instr(fetchbufC_instr),
|
|
.fetchbufD_instr(fetchbufD_instr),
|
|
.fetchbufE_instr(fetchbufE_instr),
|
|
.fetchbufF_instr(fetchbufF_instr),
|
|
.fetchbuf0_instr(fetchbuf0_instr),
|
|
.fetchbuf1_instr(fetchbuf1_instr),
|
|
.fetchbuf0_thrd(fetchbuf0_thrd),
|
|
.fetchbuf1_thrd(fetchbuf1_thrd),
|
|
.fetchbuf2_thrd(fetchbuf2_thrd),
|
|
.fetchbuf0_pc(fetchbuf0_pc),
|
|
.fetchbuf1_pc(fetchbuf1_pc),
|
|
.fetchbuf2_pc(fetchbuf2_pc),
|
|
.fetchbuf0_v(fetchbuf0_v),
|
|
.fetchbuf1_v(fetchbuf1_v),
|
|
.fetchbuf2_v(fetchbuf2_v),
|
|
.fetchbuf0_insln(fetchbuf0_insln),
|
|
.fetchbuf1_insln(fetchbuf1_insln),
|
|
.fetchbuf2_insln(fetchbuf2_insln),
|
|
.codebuf0(codebuf[insn0[21:16]]),
|
|
.codebuf1(codebuf[insn1[21:16]]),
|
|
.codebuf2(codebuf[insn2[21:16]]),
|
|
.btgtA(btgtA),
|
|
.btgtB(btgtB),
|
|
.btgtC(btgtC),
|
|
.btgtD(btgtD),
|
|
.btgtE(btgtE),
|
|
.btgtF(btgtF),
|
|
.nop_fetchbuf(nop_fetchbuf),
|
|
.take_branch0(take_branch0),
|
|
.take_branch1(take_branch1),
|
|
.take_branch2(take_branch2),
|
|
.stompedRets(stompedOnRets),
|
|
.panic(fb_panic)
|
|
);
|
|
end
|
|
else if (`WAYS > 1) begin : gb1
|
FT64_fetchbuf #(AMSB,RSTPC) ufb1
|
FT64_fetchbuf #(AMSB,RSTPC) ufb1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.clk4x(clk4x),
|
.clk4x(clk4x),
|
.clk(clk),
|
.clk(clk),
|
| Line 3086... |
Line 3479... |
.take_branch0(take_branch0),
|
.take_branch0(take_branch0),
|
.take_branch1(take_branch1),
|
.take_branch1(take_branch1),
|
.stompedRets(stompedOnRets),
|
.stompedRets(stompedOnRets),
|
.panic(fb_panic)
|
.panic(fb_panic)
|
);
|
);
|
|
end
|
|
else begin : gb1
|
|
FT64_fetchbuf_x1 #(AMSB,RSTPC) ufb1
|
|
(
|
|
.rst(rst),
|
|
.clk4x(clk4x),
|
|
.clk(clk),
|
|
.fcu_clk(fcu_clk),
|
|
.cs_i(adr_o[31:16]==16'hFFFF),
|
|
.cyc_i(cyc_o),
|
|
.stb_i(stb_o),
|
|
.ack_o(dc_ack),
|
|
.we_i(we_o),
|
|
.adr_i(adr_o[15:0]),
|
|
.dat_i(dat_o[47:0]),
|
|
.cmpgrp(cr0[10:8]),
|
|
.freezePC(freezePC),
|
|
.regLR(regLR),
|
|
.thread_en(thread_en),
|
|
.insn0(insn0),
|
|
.phit(phit),
|
|
.threadx(threadx),
|
|
.branchmiss(branchmiss),
|
|
.misspc(misspc),
|
|
.branchmiss_thrd(branchmiss_thrd),
|
|
.predict_takenA(predict_takenA),
|
|
.predict_takenB(predict_takenB),
|
|
.predict_taken0(predict_taken0),
|
|
.queued1(queued1),
|
|
.queuedNop(queuedNop),
|
|
.pc0(pc0),
|
|
.fetchbuf(fetchbuf),
|
|
.fetchbufA_v(fetchbufA_v),
|
|
.fetchbufB_v(fetchbufB_v),
|
|
.fetchbufA_pc(fetchbufA_pc),
|
|
.fetchbufB_pc(fetchbufB_pc),
|
|
.fetchbufA_instr(fetchbufA_instr),
|
|
.fetchbufB_instr(fetchbufB_instr),
|
|
.fetchbuf0_instr(fetchbuf0_instr),
|
|
.fetchbuf0_thrd(fetchbuf0_thrd),
|
|
.fetchbuf0_pc(fetchbuf0_pc),
|
|
.fetchbuf0_v(fetchbuf0_v),
|
|
.fetchbuf0_insln(fetchbuf0_insln),
|
|
.codebuf0(codebuf[insn0[21:16]]),
|
|
.btgtA(btgtA),
|
|
.btgtB(btgtB),
|
|
.nop_fetchbuf(nop_fetchbuf),
|
|
.take_branch0(take_branch0),
|
|
.stompedRets(stompedOnRets),
|
|
.panic(fb_panic)
|
|
);
|
|
assign fetchbuf1_v = `INV;
|
|
end
|
|
end
|
|
endgenerate
|
|
|
|
|
|
|
//initial begin: stop_at
|
//initial begin: stop_at
|
//#1000000; panic <= `PANIC_OVERRUN;
|
//#1000000; panic <= `PANIC_OVERRUN;
|
| Line 5595... |
Line 6043... |
// The following signals only pulse
|
// The following signals only pulse
|
|
|
// Instruction decode output should only pulse once for a queue entry. We
|
// Instruction decode output should only pulse once for a queue entry. We
|
// want the decode to be invalidated after a clock cycle so that it isn't
|
// want the decode to be invalidated after a clock cycle so that it isn't
|
// inadvertently used to update the queue at a later point.
|
// inadvertently used to update the queue at a later point.
|
|
dramA_v <= `INV;
|
|
dramB_v <= `INV;
|
|
dramC_v <= `INV;
|
id1_vi <= `INV;
|
id1_vi <= `INV;
|
if (`NUM_IDU > 1)
|
if (`NUM_IDU > 1)
|
id2_vi <= `INV;
|
id2_vi <= `INV;
|
if (`NUM_IDU > 2)
|
if (`NUM_IDU > 2)
|
id3_vi <= `INV;
|
id3_vi <= `INV;
|
| Line 7042... |
Line 7493... |
sel_o <= wb_sel[0];
|
sel_o <= wb_sel[0];
|
adr_o <= wb_addr[0];
|
adr_o <= wb_addr[0];
|
dat_o <= wb_data[0];
|
dat_o <= wb_data[0];
|
ol_o <= wb_ol[0];
|
ol_o <= wb_ol[0];
|
wbo_id <= wb_id[0];
|
wbo_id <= wb_id[0];
|
|
isStore <= TRUE;
|
bstate <= wb_rmw[0] ? B12 : B1;
|
bstate <= wb_rmw[0] ? B12 : B1;
|
end
|
end
|
begin
|
begin
|
for (j = 1; j < `WB_DEPTH; j = j + 1) begin
|
for (j = 1; j < `WB_DEPTH; j = j + 1) begin
|
wb_v[j-1] <= wb_v[j];
|
wb_v[j-1] <= wb_v[j];
|
| Line 7165... |
Line 7617... |
stb_o <= `HIGH;
|
stb_o <= `HIGH;
|
sel_o <= fnSelect(dram0_instr,dram0_addr);
|
sel_o <= fnSelect(dram0_instr,dram0_addr);
|
adr_o <= dram0_addr;
|
adr_o <= dram0_addr;
|
dat_o <= fnDato(dram0_instr,dram0_data);
|
dat_o <= fnDato(dram0_instr,dram0_data);
|
ol_o <= dram0_ol;
|
ol_o <= dram0_ol;
|
|
isStore <= TRUE;
|
bstate <= B1;
|
bstate <= B1;
|
`else
|
`else
|
if (wbptr<`WB_DEPTH-1) begin
|
if (wbptr<`WB_DEPTH-1) begin
|
dram0 <= `DRAMREQ_READY;
|
dram0 <= `DRAMREQ_READY;
|
dram0_instr[`INSTRUCTION_OP] <= `NOP;
|
dram0_instr[`INSTRUCTION_OP] <= `NOP;
|
| Line 7207... |
Line 7660... |
stb_o <= `HIGH;
|
stb_o <= `HIGH;
|
sel_o <= fnSelect(dram1_instr,dram1_addr);
|
sel_o <= fnSelect(dram1_instr,dram1_addr);
|
adr_o <= dram1_addr;
|
adr_o <= dram1_addr;
|
dat_o <= fnDato(dram1_instr,dram1_data);
|
dat_o <= fnDato(dram1_instr,dram1_data);
|
ol_o <= dram1_ol;
|
ol_o <= dram1_ol;
|
|
isStore <= TRUE;
|
bstate <= B1;
|
bstate <= B1;
|
`else
|
`else
|
if (wbptr<`WB_DEPTH-1) begin
|
if (wbptr<`WB_DEPTH-1) begin
|
dram1 <= `DRAMREQ_READY;
|
dram1 <= `DRAMREQ_READY;
|
dram1_instr[`INSTRUCTION_OP] <= `NOP;
|
dram1_instr[`INSTRUCTION_OP] <= `NOP;
|
| Line 7249... |
Line 7703... |
stb_o <= `HIGH;
|
stb_o <= `HIGH;
|
sel_o <= fnSelect(dram2_instr,dram2_addr);
|
sel_o <= fnSelect(dram2_instr,dram2_addr);
|
adr_o <= dram2_addr;
|
adr_o <= dram2_addr;
|
dat_o <= fnDato(dram2_instr,dram2_data);
|
dat_o <= fnDato(dram2_instr,dram2_data);
|
ol_o <= dram2_ol;
|
ol_o <= dram2_ol;
|
|
isStore <= TRUE;
|
bstate <= B1;
|
bstate <= B1;
|
`else
|
`else
|
if (wbptr<`WB_DEPTH-1) begin
|
if (wbptr<`WB_DEPTH-1) begin
|
dram2 <= `DRAMREQ_READY;
|
dram2 <= `DRAMREQ_READY;
|
dram2_instr[`INSTRUCTION_OP] <= `NOP;
|
dram2_instr[`INSTRUCTION_OP] <= `NOP;
|
| Line 7417... |
Line 7872... |
if (acki|err_i) begin
|
if (acki|err_i) begin
|
isStore <= `TRUE;
|
isStore <= `TRUE;
|
cyc_o <= `LOW;
|
cyc_o <= `LOW;
|
stb_o <= `LOW;
|
stb_o <= `LOW;
|
we_o <= `LOW;
|
we_o <= `LOW;
|
sel_o <= 8'h00;
|
|
cr_o <= 1'b0;
|
cr_o <= 1'b0;
|
// This isn't a good way of doing things; the state should be propagated
|
// This isn't a good way of doing things; the state should be propagated
|
// to the commit stage, however since this is a store we know there will
|
// to the commit stage, however since this is a store we know there will
|
// be no change of program flow. So the reservation status bit is set
|
// be no change of program flow. So the reservation status bit is set
|
// here. The author wanted to avoid the complexity of propagating the
|
// here. The author wanted to avoid the complexity of propagating the
|
| Line 7621... |
Line 8075... |
end
|
end
|
else begin
|
else begin
|
cas <= dat_i;
|
cas <= dat_i;
|
cyc_o <= `LOW;
|
cyc_o <= `LOW;
|
stb_o <= `LOW;
|
stb_o <= `LOW;
|
sel_o <= 8'h00;
|
|
case(bwhich)
|
case(bwhich)
|
2'b00: dram0 <= `DRAMREQ_READY;
|
2'b00: dram0 <= `DRAMREQ_READY;
|
2'b01: dram1 <= `DRAMREQ_READY;
|
2'b01: dram1 <= `DRAMREQ_READY;
|
2'b10: dram2 <= `DRAMREQ_READY;
|
2'b10: dram2 <= `DRAMREQ_READY;
|
default: ;
|
default: ;
|
| Line 7656... |
Line 8109... |
bstate <= B20;
|
bstate <= B20;
|
end
|
end
|
else begin
|
else begin
|
cyc_o <= `LOW;
|
cyc_o <= `LOW;
|
stb_o <= `LOW;
|
stb_o <= `LOW;
|
sel_o <= 8'h00;
|
|
sr_o <= `LOW;
|
sr_o <= `LOW;
|
xdati <= dat_i;
|
xdati <= dat_i;
|
case(bwhich)
|
case(bwhich)
|
2'b00: begin
|
2'b00: begin
|
dram0 <= `DRAMREQ_READY;
|
dram0 <= `DRAMREQ_READY;
|
| Line 7691... |
Line 8143... |
default: bstate <= BIDLE;
|
default: bstate <= BIDLE;
|
endcase
|
endcase
|
end
|
end
|
B17: bstate <= B18;
|
B17: bstate <= B18;
|
B18: bstate <= B19;
|
B18: bstate <= B19;
|
B19: if (~acki) begin bstate <= BIDLE; isStore <= `FALSE; end
|
B19: if (~acki) begin
|
|
sel_o <= 8'h00;
|
|
bstate <= BIDLE;
|
|
isStore <= `FALSE;
|
|
end
|
B20:
|
B20:
|
if (~ack_i) begin
|
if (~ack_i) begin
|
stb_o <= `HIGH;
|
stb_o <= `HIGH;
|
we_o <= `HIGH;
|
we_o <= `HIGH;
|
dat_o <= fnDato(rmw_instr,rmw_res);
|
dat_o <= fnDato(rmw_instr,rmw_res);
|
| Line 7821... |
Line 8277... |
end
|
end
|
`else
|
`else
|
$display ("Regfile: %d", rgs);
|
$display ("Regfile: %d", rgs);
|
for (n=0; n < 32; n=n+4) begin
|
for (n=0; n < 32; n=n+4) begin
|
$display("%d: %h %d %o %d: %h %d %o %d: %h %d %o %d: %h %d %o#",
|
$display("%d: %h %d %o %d: %h %d %o %d: %h %d %o %d: %h %d %o#",
|
n[4:0]+0, urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b00}], regIsValid[n+0], rf_source[n+0],
|
n[4:0]+0, gRegfileInst.gb1.urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b00}], regIsValid[n+0], rf_source[n+0],
|
n[4:0]+1, urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b01}], regIsValid[n+1], rf_source[n+1],
|
n[4:0]+1, gRegfileInst.gb1.urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b01}], regIsValid[n+1], rf_source[n+1],
|
n[4:0]+2, urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b10}], regIsValid[n+2], rf_source[n+2],
|
n[4:0]+2, gRegfileInst.gb1.urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b10}], regIsValid[n+2], rf_source[n+2],
|
n[4:0]+3, urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b11}], regIsValid[n+3], rf_source[n+3]
|
n[4:0]+3, gRegfileInst.gb1.urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b11}], regIsValid[n+3], rf_source[n+3]
|
);
|
);
|
end
|
end
|
`endif
|
`endif
|
`ifdef FCU_ENH
|
`ifdef FCU_ENH
|
$display("Call Stack:");
|
$display("Call Stack:");
|
for (n = 0; n < 16; n = n + 4)
|
for (n = 0; n < 16; n = n + 4)
|
$display("%c%d: %h %c%d: %h %c%d: %h %c%d: %h",
|
$display("%c%d: %h %c%d: %h %c%d: %h %c%d: %h",
|
ufb1.ursb1.rasp==n+0 ?">" : " ", n[4:0]+0, ufb1.ursb1.ras[n+0],
|
gFetchbufInst.gb1.ufb1.ursb1.rasp==n+0 ?">" : " ", n[4:0]+0, gFetchbufInst.gb1.ufb1.ursb1.ras[n+0],
|
ufb1.ursb1.rasp==n+1 ?">" : " ", n[4:0]+1, ufb1.ursb1.ras[n+1],
|
gFetchbufInst.gb1.ufb1.ursb1.rasp==n+1 ?">" : " ", n[4:0]+1, gFetchbufInst.gb1.ufb1.ursb1.ras[n+1],
|
ufb1.ursb1.rasp==n+2 ?">" : " ", n[4:0]+2, ufb1.ursb1.ras[n+2],
|
gFetchbufInst.gb1.ufb1.ursb1.rasp==n+2 ?">" : " ", n[4:0]+2, gFetchbufInst.gb1.ufb1.ursb1.ras[n+2],
|
ufb1.ursb1.rasp==n+3 ?">" : " ", n[4:0]+3, ufb1.ursb1.ras[n+3]
|
gFetchbufInst.gb1.ufb1.ursb1.rasp==n+3 ?">" : " ", n[4:0]+3, gFetchbufInst.gb1.ufb1.ursb1.ras[n+3]
|
);
|
);
|
$display("\n");
|
$display("\n");
|
`endif
|
`endif
|
// $display("Return address stack:");
|
// $display("Return address stack:");
|
// for (n = 0; n < 16; n = n + 1)
|
// for (n = 0; n < 16; n = n + 1)
|
// $display("%d %h", rasp+n[3:0], ras[rasp+n[3:0]]);
|
// $display("%d %h", rasp+n[3:0], ras[rasp+n[3:0]]);
|
$display("TakeBr:%d #", take_branch);//, backpc);
|
$display("TakeBr:%d #", take_branch);//, backpc);
|
$display("Insn%d: %h", 0, insn0);
|
$display("Insn%d: %h", 0, insn0);
|
if (`WAYS > 1)
|
if (`WAYS==1) begin
|
|
$display("%c%c A: %d %h %h #",
|
|
45, fetchbuf?45:62, fetchbufA_v, fetchbufA_instr, fetchbufA_pc);
|
|
$display("%c%c B: %d %h %h #",
|
|
45, fetchbuf?62:45, fetchbufB_v, fetchbufB_instr, fetchbufB_pc);
|
|
end
|
|
else if (`WAYS > 1) begin
|
$display("Insn%d: %h", 1, insn1);
|
$display("Insn%d: %h", 1, insn1);
|
$display("%c%c A: %d %h %h #",
|
$display("%c%c A: %d %h %h #",
|
45, fetchbuf?45:62, fetchbufA_v, fetchbufA_instr, fetchbufA_pc);
|
45, fetchbuf?45:62, fetchbufA_v, fetchbufA_instr, fetchbufA_pc);
|
$display("%c%c B: %d %h %h #",
|
$display("%c%c B: %d %h %h #",
|
45, fetchbuf?45:62, fetchbufB_v, fetchbufB_instr, fetchbufB_pc);
|
45, fetchbuf?45:62, fetchbufB_v, fetchbufB_instr, fetchbufB_pc);
|
|
end
|
|
else if (`WAYS > 2) begin
|
$display("%c%c C: %d %h %h #",
|
$display("%c%c C: %d %h %h #",
|
45, fetchbuf?62:45, fetchbufC_v, fetchbufC_instr, fetchbufC_pc);
|
45, fetchbuf?62:45, fetchbufC_v, fetchbufC_instr, fetchbufC_pc);
|
$display("%c%c D: %d %h %h #",
|
$display("%c%c D: %d %h %h #",
|
45, fetchbuf?62:45, fetchbufD_v, fetchbufD_instr, fetchbufD_pc);
|
45, fetchbuf?62:45, fetchbufD_v, fetchbufD_instr, fetchbufD_pc);
|
|
end
|
for (i=0; i<QENTRIES; i=i+1)
|
for (i=0; i<QENTRIES; i=i+1)
|
$display("%c%c %d: %c%c%c%c %d %d %c%c %c %c%h %d %o %h %h %h %d %o %h %d %o %h %d %o %d:%h %h %d#",
|
$display("%c%c %d: %c%c%c%c %d %d %c%c %c %c%h %d %o %h %h %h %d %o %h %d %o %h %d %o %d:%h %h %d#",
|
(i[`QBITS]==head0)?"C":".",
|
(i[`QBITS]==head0)?"C":".",
|
(i[`QBITS]==tail0)?"Q":".",
|
(i[`QBITS]==tail0)?"Q":".",
|
i[`QBITS],
|
i[`QBITS],
|
