| Line 89... |
Line 89... |
parameter RBIT = 11;
|
parameter RBIT = 11;
|
parameter DEBUG = 1'b0;
|
parameter DEBUG = 1'b0;
|
parameter NMAP = QENTRIES;
|
parameter NMAP = QENTRIES;
|
parameter BRANCH_PRED = 1'b0;
|
parameter BRANCH_PRED = 1'b0;
|
parameter SUP_TXE = 1'b0;
|
parameter SUP_TXE = 1'b0;
|
parameter SUP_VECTOR = `SUPPORT_VECTOR;
|
`ifdef SUPPORT_VECTOR
|
|
parameter SUP_VECTOR = 1'b1;
|
|
`else
|
|
parameter SUP_VECTOR = 1'b0;
|
|
`endif
|
parameter DBW = 64;
|
parameter DBW = 64;
|
parameter ABW = 32;
|
parameter ABW = 32;
|
parameter AMSB = ABW-1;
|
parameter AMSB = ABW-1;
|
parameter NTHREAD = 1;
|
parameter NTHREAD = 1;
|
reg [3:0] i;
|
reg [3:0] i;
|
| Line 869... |
Line 873... |
parameter B_DCacheLoadStart = 5'd2;
|
parameter B_DCacheLoadStart = 5'd2;
|
parameter B_DCacheLoadStb = 5'd3;
|
parameter B_DCacheLoadStb = 5'd3;
|
parameter B_DCacheLoadWait1 = 5'd4;
|
parameter B_DCacheLoadWait1 = 5'd4;
|
parameter B_DCacheLoadWait2 = 5'd5;
|
parameter B_DCacheLoadWait2 = 5'd5;
|
parameter B_DCacheLoadResetBusy = 5'd6;
|
parameter B_DCacheLoadResetBusy = 5'd6;
|
parameter B7 = 5'd7;
|
parameter B_ICacheAck = 5'd7;
|
parameter B8 = 5'd8;
|
parameter B8 = 5'd8;
|
parameter B9 = 5'd9;
|
parameter B_ICacheNack = 5'd9;
|
parameter B10 = 5'd10;
|
parameter B10 = 5'd10;
|
parameter B11 = 5'd11;
|
parameter B11 = 5'd11;
|
parameter B12 = 5'd12;
|
parameter B12 = 5'd12;
|
parameter B13 = 5'd13;
|
parameter B13 = 5'd13;
|
parameter B14 = 5'd14;
|
parameter B14 = 5'd14;
|
| Line 895... |
Line 899... |
reg [3:0] icstate,picstate;
|
reg [3:0] icstate,picstate;
|
parameter IDLE = 4'd0;
|
parameter IDLE = 4'd0;
|
parameter IC1 = 4'd1;
|
parameter IC1 = 4'd1;
|
parameter IC2 = 4'd2;
|
parameter IC2 = 4'd2;
|
parameter IC3 = 4'd3;
|
parameter IC3 = 4'd3;
|
parameter IC4 = 4'd4;
|
parameter IC_WaitL2 = 4'd4;
|
parameter IC5 = 4'd5;
|
parameter IC5 = 4'd5;
|
parameter IC6 = 4'd6;
|
parameter IC6 = 4'd6;
|
parameter IC7 = 4'd7;
|
parameter IC7 = 4'd7;
|
parameter IC8 = 4'd8;
|
parameter IC_Next = 4'd8;
|
parameter IC9 = 4'd9;
|
parameter IC9 = 4'd9;
|
parameter IC10 = 4'd10;
|
parameter IC10 = 4'd10;
|
parameter IC3a = 4'd11;
|
parameter IC3a = 4'd11;
|
reg invic, invdc;
|
reg invic, invdc;
|
reg [1:0] icwhich;
|
reg [1:0] icwhich;
|
| Line 915... |
Line 919... |
always @*
|
always @*
|
phit <= ihit&&icstate==IDLE;
|
phit <= ihit&&icstate==IDLE;
|
reg [2:0] iccnt;
|
reg [2:0] iccnt;
|
reg L1_wr0,L1_wr1,L1_wr2;
|
reg L1_wr0,L1_wr1,L1_wr2;
|
reg L1_invline;
|
reg L1_invline;
|
|
wire [1:0] ic0_fault,ic1_fault,ic2_fault;
|
reg [8:0] L1_en;
|
reg [8:0] L1_en;
|
reg [37:0] L1_adr, L2_adr;
|
reg [37:0] L1_adr, L2_adr;
|
reg [287:0] L2_rdat;
|
reg [289:0] L2_rdat;
|
wire [287:0] L2_dato;
|
wire [289:0] L2_dato;
|
reg L2_xsel;
|
reg L2_xsel;
|
|
|
generate begin : gRegfileInst
|
generate begin : gRegfileInst
|
if (`WAYS > 2) begin : gb1
|
if (`WAYS > 2) begin : gb1
|
FT64_regfile2w9r_oc #(.RBIT(RBIT)) urf1
|
FT64_regfile2w9r_oc #(.RBIT(RBIT)) urf1
|
| Line 1052... |
Line 1057... |
.rst(rst),
|
.rst(rst),
|
.clk(clk),
|
.clk(clk),
|
.nxt(icnxt),
|
.nxt(icnxt),
|
.wr(L1_wr0),
|
.wr(L1_wr0),
|
.en(L1_en),
|
.en(L1_en),
|
.adr(icstate==IDLE||icstate==IC8 ? {pcr[5:0],pc0} : L1_adr),
|
.adr(icstate==IDLE||icstate==IC_Next ? {pcr[5:0],pc0} : L1_adr),
|
.wadr(L1_adr),
|
.wadr(L1_adr),
|
.i(L2_rdat),
|
.i(L2_rdat),
|
.o(insn0a),
|
.o(insn0a),
|
|
.fault(ic0_fault),
|
.hit(ihit0),
|
.hit(ihit0),
|
.invall(invic),
|
.invall(invic),
|
.invline(L1_invline)
|
.invline(L1_invline)
|
);
|
);
|
generate begin : gICacheInst
|
generate begin : gICacheInst
|
| Line 1069... |
Line 1075... |
.rst(rst),
|
.rst(rst),
|
.clk(clk),
|
.clk(clk),
|
.nxt(icnxt),
|
.nxt(icnxt),
|
.wr(L1_wr1),
|
.wr(L1_wr1),
|
.en(L1_en),
|
.en(L1_en),
|
.adr(icstate==IDLE||icstate==IC8 ? (thread_en ? {pcr[5:0],pc1}: {pcr[5:0],pc0plus6} ): L1_adr),
|
.adr(icstate==IDLE||icstate==IC_Next ? (thread_en ? {pcr[5:0],pc1}: {pcr[5:0],pc0plus6} ): L1_adr),
|
.wadr(L1_adr),
|
.wadr(L1_adr),
|
.i(L2_rdat),
|
.i(L2_rdat),
|
.o(insn1b),
|
.o(insn1b),
|
|
.fault(ic1_fault),
|
.hit(ihit1),
|
.hit(ihit1),
|
.invall(invic),
|
.invall(invic),
|
.invline(L1_invline)
|
.invline(L1_invline)
|
);
|
);
|
end
|
end
|
| Line 1089... |
Line 1096... |
.rst(rst),
|
.rst(rst),
|
.clk(clk),
|
.clk(clk),
|
.nxt(icnxt),
|
.nxt(icnxt),
|
.wr(L1_wr2),
|
.wr(L1_wr2),
|
.en(L1_en),
|
.en(L1_en),
|
.adr(icstate==IDLE||icstate==IC8 ? (thread_en ? {pcr[5:0],pc2} : {pcr[5:0],pc0plus12}) : L1_adr),
|
.adr(icstate==IDLE||icstate==IC_Next ? (thread_en ? {pcr[5:0],pc2} : {pcr[5:0],pc0plus12}) : L1_adr),
|
.wadr(L1_adr),
|
.wadr(L1_adr),
|
.i(L2_rdat),
|
.i(L2_rdat),
|
.o(insn2b),
|
.o(insn2b),
|
|
.fault(ic2_fault),
|
.hit(ihit2),
|
.hit(ihit2),
|
.invall(invic),
|
.invall(invic),
|
.invline(L1_invline)
|
.invline(L1_invline)
|
);
|
);
|
end
|
end
|
| Line 1108... |
Line 1116... |
FT64_L2_icache uic2
|
FT64_L2_icache uic2
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.clk(clk),
|
.clk(clk),
|
.nxt(L2_nxt),
|
.nxt(L2_nxt),
|
.wr(bstate==B7 && ack_i),
|
.wr(bstate==B_ICacheAck && ack_i),
|
.xsel(L2_xsel),
|
.xsel(L2_xsel),
|
.adr(L2_adr),
|
.adr(L2_adr),
|
.cnt(iccnt),
|
.cnt(iccnt),
|
.exv_i(exvq),
|
.exv_i(exvq),
|
.i(dat_i),
|
.i(dat_i),
|
| Line 1651... |
Line 1659... |
insn0 <= {8'd0,3'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
|
insn0 <= {8'd0,3'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
|
else if (phit) begin
|
else if (phit) begin
|
if (insn0a[`INSTRUCTION_OP]==`BRK && insn0a[23:21]==3'd0 && insn0a[7:6]==2'b00)
|
if (insn0a[`INSTRUCTION_OP]==`BRK && insn0a[23:21]==3'd0 && insn0a[7:6]==2'b00)
|
insn0 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
insn0 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
else
|
else
|
insn0 <= insn0a;
|
insn0 <= ic0_fault[1] ? `INSN_FLT_IBE : ic0_fault[0] ? `INSN_FLT_EXF : insn0a;
|
end
|
end
|
else
|
else
|
insn0 <= `NOP_INSN;
|
insn0 <= `NOP_INSN;
|
generate begin : gInsnMux
|
generate begin : gInsnMux
|
if (`WAYS > 1) begin
|
if (`WAYS > 1) begin
|
| Line 1664... |
Line 1672... |
insn1 <= {8'd0,3'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
|
insn1 <= {8'd0,3'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
|
else if (phit) begin
|
else if (phit) begin
|
if (insn1a[`INSTRUCTION_OP]==`BRK && insn1a[23:21]==3'd0 && insn1a[7:6]==2'b00)
|
if (insn1a[`INSTRUCTION_OP]==`BRK && insn1a[23:21]==3'd0 && insn1a[7:6]==2'b00)
|
insn1 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
insn1 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
else
|
else
|
insn1 <= insn1a;
|
insn1 <= ic1_fault[1] ? `INSN_FLT_IBE : ic1_fault[0] ? `INSN_FLT_EXF : insn1a;
|
end
|
end
|
else
|
else
|
insn1 <= `NOP_INSN;
|
insn1 <= `NOP_INSN;
|
end
|
end
|
if (`WAYS > 2) begin
|
if (`WAYS > 2) begin
|
| Line 1677... |
Line 1685... |
insn2 <= {8'd0,3'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
|
insn2 <= {8'd0,3'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
|
else if (phit) begin
|
else if (phit) begin
|
if (insn2a[`INSTRUCTION_OP]==`BRK && insn1a[23:21]==3'd0 && insn2a[7:6]==2'b00)
|
if (insn2a[`INSTRUCTION_OP]==`BRK && insn1a[23:21]==3'd0 && insn2a[7:6]==2'b00)
|
insn2 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
insn2 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
else
|
else
|
insn2 <= insn2a;
|
insn2 <= ic2_fault[1] ? `INSN_FLT_IBE : ic2_fault[0] ? `INSN_FLT_EXF : insn2a;
|
end
|
end
|
else
|
else
|
insn2 <= `NOP_INSN;
|
insn2 <= `NOP_INSN;
|
end
|
end
|
end
|
end
|
| Line 3869... |
Line 3877... |
&& (!iqentry_v[head5]))
|
&& (!iqentry_v[head5]))
|
)
|
)
|
) begin
|
) begin
|
iqentry_alu0_issue[head7] = `TRUE;
|
iqentry_alu0_issue[head7] = `TRUE;
|
end
|
end
|
|
else if (could_issue[head8] && iqentry_alu[head8]
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2]))
|
|
)
|
|
&& (!(iqentry_v[head4] && iqentry_sync[head4]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3]))
|
|
)
|
|
&& (!(iqentry_v[head5] && iqentry_sync[head5]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4]))
|
|
)
|
|
&& (!(iqentry_v[head6] && iqentry_sync[head6]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4])
|
|
&& (!iqentry_v[head5]))
|
|
)
|
|
&& (!(iqentry_v[head7] && iqentry_sync[head7]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4])
|
|
&& (!iqentry_v[head5])
|
|
&& (!iqentry_v[head6])
|
|
)
|
|
)
|
|
) begin
|
|
iqentry_alu0_issue[head8] = `TRUE;
|
|
end
|
|
else if (could_issue[head9] && iqentry_alu[head9]
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2]))
|
|
)
|
|
&& (!(iqentry_v[head4] && iqentry_sync[head4]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3]))
|
|
)
|
|
&& (!(iqentry_v[head5] && iqentry_sync[head5]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4]))
|
|
)
|
|
&& (!(iqentry_v[head6] && iqentry_sync[head6]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4])
|
|
&& (!iqentry_v[head5]))
|
|
)
|
|
&& (!(iqentry_v[head7] && iqentry_sync[head7]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4])
|
|
&& (!iqentry_v[head5])
|
|
&& (!iqentry_v[head6]))
|
|
)
|
|
&& (!(iqentry_v[head8] && iqentry_sync[head8]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4])
|
|
&& (!iqentry_v[head5])
|
|
&& (!iqentry_v[head6])
|
|
&& (!iqentry_v[head7])
|
|
)
|
|
)
|
|
) begin
|
|
iqentry_alu0_issue[head9] = `TRUE;
|
|
end
|
`endif
|
`endif
|
end
|
end
|
|
|
if (alu1_available && alu1_idle && `NUM_ALU > 1) begin
|
if (alu1_available && alu1_idle && `NUM_ALU > 1) begin
|
if ((could_issue & ~iqentry_alu0_issue & ~iqentry_alu0) != 8'h00) begin
|
if ((could_issue & ~iqentry_alu0_issue & ~iqentry_alu0) != 8'h00) begin
|
| Line 4661... |
Line 4769... |
&& (!iqentry_v[head5]))
|
&& (!iqentry_v[head5]))
|
)
|
)
|
) begin
|
) begin
|
iqentry_fcu_issue[head7] = `TRUE;
|
iqentry_fcu_issue[head7] = `TRUE;
|
end
|
end
|
|
else if (could_issue[head8] && iqentry_fc[head8]
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2]))
|
|
)
|
|
&& (!(iqentry_v[head4] && iqentry_sync[head4]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3]))
|
|
)
|
|
&& (!(iqentry_v[head5] && iqentry_sync[head5]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4]))
|
|
)
|
|
&& (!(iqentry_v[head6] && iqentry_sync[head6]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4])
|
|
&& (!iqentry_v[head5]))
|
|
)
|
|
&& (!(iqentry_v[head7] && iqentry_sync[head7]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4])
|
|
&& (!iqentry_v[head5])
|
|
&& (!iqentry_v[head6])
|
|
)
|
|
)
|
|
) begin
|
|
iqentry_fcu_issue[head8] = `TRUE;
|
|
end
|
|
else if (could_issue[head9] && iqentry_fc[head9]
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2]))
|
|
)
|
|
&& (!(iqentry_v[head4] && iqentry_sync[head4]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3]))
|
|
)
|
|
&& (!(iqentry_v[head5] && iqentry_sync[head5]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4]))
|
|
)
|
|
&& (!(iqentry_v[head6] && iqentry_sync[head6]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4])
|
|
&& (!iqentry_v[head5]))
|
|
)
|
|
&& (!(iqentry_v[head7] && iqentry_sync[head7]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4])
|
|
&& (!iqentry_v[head5])
|
|
&& (!iqentry_v[head6]))
|
|
)
|
|
&& (!(iqentry_v[head8] && iqentry_sync[head8]) ||
|
|
((!iqentry_v[head0])
|
|
&& (!iqentry_v[head1])
|
|
&& (!iqentry_v[head2])
|
|
&& (!iqentry_v[head3])
|
|
&& (!iqentry_v[head4])
|
|
&& (!iqentry_v[head5])
|
|
&& (!iqentry_v[head6])
|
|
&& (!iqentry_v[head7])
|
|
)
|
|
)
|
|
) begin
|
|
iqentry_fcu_issue[head9] = `TRUE;
|
|
end
|
`endif
|
`endif
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
| Line 5101... |
Line 5309... |
&& !(iqentry_fc[head2]||iqentry_canex[head2])
|
&& !(iqentry_fc[head2]||iqentry_canex[head2])
|
&& !(iqentry_fc[head3]||iqentry_canex[head3])
|
&& !(iqentry_fc[head3]||iqentry_canex[head3])
|
&& !(iqentry_fc[head4]||iqentry_canex[head4])
|
&& !(iqentry_fc[head4]||iqentry_canex[head4])
|
&& !(iqentry_fc[head5]||iqentry_canex[head5])
|
&& !(iqentry_fc[head5]||iqentry_canex[head5])
|
&& !(iqentry_fc[head6]||iqentry_canex[head6]));
|
&& !(iqentry_fc[head6]||iqentry_canex[head6]));
|
|
|
|
memissue[ head8 ] = ~iqentry_stomp[head8] && iqentry_memready[ head8 ] // addr and data are valid
|
|
// ... and no preceding instruction is ready to go
|
|
&& issue_count < `NUM_MEM
|
|
//&& ~iqentry_memready[head0]
|
|
//&& ~iqentry_memready[head1]
|
|
//&& ~iqentry_memready[head2]
|
|
//&& ~iqentry_memready[head3]
|
|
//&& ~iqentry_memready[head4]
|
|
//&& ~iqentry_memready[head5]
|
|
//&& ~iqentry_memready[head6]
|
|
// ... and there is no address-overlap with any preceding instruction
|
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0]
|
|
|| (iqentry_a1_v[head0] && (iqentry_a1[head8][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0])))
|
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1]) || iqentry_done[head1]
|
|
|| (iqentry_a1_v[head1] && (iqentry_a1[head8][AMSB:3] != iqentry_a1[head1][AMSB:3] || iqentry_out[head1] || iqentry_done[head1])))
|
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2]) || iqentry_done[head2]
|
|
|| (iqentry_a1_v[head2] && (iqentry_a1[head8][AMSB:3] != iqentry_a1[head2][AMSB:3] || iqentry_out[head2] || iqentry_done[head2])))
|
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3]) || iqentry_done[head3]
|
|
|| (iqentry_a1_v[head3] && (iqentry_a1[head8][AMSB:3] != iqentry_a1[head3][AMSB:3] || iqentry_out[head3] || iqentry_done[head3])))
|
|
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4]) || iqentry_done[head4]
|
|
|| (iqentry_a1_v[head4] && (iqentry_a1[head8][AMSB:3] != iqentry_a1[head4][AMSB:3] || iqentry_out[head4] || iqentry_done[head4])))
|
|
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5]) || iqentry_done[head5]
|
|
|| (iqentry_a1_v[head5] && (iqentry_a1[head8][AMSB:3] != iqentry_a1[head5][AMSB:3] || iqentry_out[head5] || iqentry_done[head5])))
|
|
&& (!iqentry_mem[head6] || (iqentry_agen[head6] & iqentry_out[head6]) || iqentry_done[head6]
|
|
|| (iqentry_a1_v[head6] && (iqentry_a1[head8][AMSB:3] != iqentry_a1[head6][AMSB:3] || iqentry_out[head6] || iqentry_done[head6])))
|
|
&& (!iqentry_mem[head7] || (iqentry_agen[head7] & iqentry_out[head7]) || iqentry_done[head7]
|
|
|| (iqentry_a1_v[head7] && (iqentry_a1[head8][AMSB:3] != iqentry_a1[head7][AMSB:3] || iqentry_out[head7] || iqentry_done[head7])))
|
|
&& (iqentry_rl[head8] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
|
&& (iqentry_done[head4] || !iqentry_v[head4] || !iqentry_mem[head4])
|
|
&& (iqentry_done[head5] || !iqentry_v[head5] || !iqentry_mem[head5])
|
|
&& (iqentry_done[head6] || !iqentry_v[head6] || !iqentry_mem[head6])
|
|
&& (iqentry_done[head7] || !iqentry_v[head7] || !iqentry_mem[head7])
|
|
: 1'b1)
|
|
// ... if a preivous op has the aquire bit set
|
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
|
&& !(iqentry_aq[head1] && iqentry_v[head1])
|
|
&& !(iqentry_aq[head2] && iqentry_v[head2])
|
|
&& !(iqentry_aq[head3] && iqentry_v[head3])
|
|
&& !(iqentry_aq[head4] && iqentry_v[head4])
|
|
&& !(iqentry_aq[head5] && iqentry_v[head5])
|
|
&& !(iqentry_aq[head6] && iqentry_v[head6])
|
|
&& !(iqentry_aq[head7] && iqentry_v[head7])
|
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
|
&& (!(iqentry_iv[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
|
&& (!(iqentry_iv[head2] && iqentry_memsb[head2]) ||
|
|
((iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (iqentry_done[head1] || !iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_iv[head3] && iqentry_memsb[head3]) ||
|
|
((iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (iqentry_done[head2] || !iqentry_v[head2]))
|
|
)
|
|
&& (!(iqentry_iv[head4] && iqentry_memsb[head4]) ||
|
|
((iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (iqentry_done[head3] || !iqentry_v[head3]))
|
|
)
|
|
&& (!(iqentry_iv[head5] && iqentry_memsb[head5]) ||
|
|
((iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (iqentry_done[head3] || !iqentry_v[head3])
|
|
&& (iqentry_done[head4] || !iqentry_v[head4]))
|
|
)
|
|
&& (!(iqentry_iv[head6] && iqentry_memsb[head6]) ||
|
|
((iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (iqentry_done[head3] || !iqentry_v[head3])
|
|
&& (iqentry_done[head4] || !iqentry_v[head4])
|
|
&& (iqentry_done[head5] || !iqentry_v[head5]))
|
|
)
|
|
&& (!(iqentry_iv[head7] && iqentry_memsb[head7]) ||
|
|
((iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (iqentry_done[head3] || !iqentry_v[head3])
|
|
&& (iqentry_done[head4] || !iqentry_v[head4])
|
|
&& (iqentry_done[head5] || !iqentry_v[head5])
|
|
&& (iqentry_done[head6] || !iqentry_v[head6])
|
|
)
|
|
)
|
|
&& (!(iqentry_iv[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
|
&& (!(iqentry_iv[head2] && iqentry_memdb[head2]) ||
|
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_iv[head3] && iqentry_memdb[head3]) ||
|
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]))
|
|
)
|
|
&& (!(iqentry_iv[head4] && iqentry_memdb[head4]) ||
|
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]))
|
|
)
|
|
&& (!(iqentry_iv[head5] && iqentry_memdb[head5]) ||
|
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])
|
|
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4]))
|
|
)
|
|
&& (!(iqentry_iv[head6] && iqentry_memdb[head6]) ||
|
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])
|
|
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4])
|
|
&& (!iqentry_mem[head5] || iqentry_done[head5] || !iqentry_v[head5]))
|
|
)
|
|
&& (!(iqentry_iv[head7] && iqentry_memdb[head7]) ||
|
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])
|
|
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4])
|
|
&& (!iqentry_mem[head5] || iqentry_done[head5] || !iqentry_v[head5])
|
|
&& (!iqentry_mem[head6] || iqentry_done[head6] || !iqentry_v[head6])
|
|
)
|
|
)
|
|
// ... and, if it is a SW, there is no chance of it being undone
|
|
&& (iqentry_load[head8] ||
|
|
!(iqentry_fc[head0]||iqentry_canex[head0])
|
|
&& !(iqentry_fc[head1]||iqentry_canex[head1])
|
|
&& !(iqentry_fc[head2]||iqentry_canex[head2])
|
|
&& !(iqentry_fc[head3]||iqentry_canex[head3])
|
|
&& !(iqentry_fc[head4]||iqentry_canex[head4])
|
|
&& !(iqentry_fc[head5]||iqentry_canex[head5])
|
|
&& !(iqentry_fc[head6]||iqentry_canex[head6])
|
|
&& !(iqentry_fc[head7]||iqentry_canex[head7])
|
|
);
|
|
memissue[ head9 ] = ~iqentry_stomp[head9] && iqentry_memready[ head9 ] // addr and data are valid
|
|
// ... and no preceding instruction is ready to go
|
|
&& issue_count < `NUM_MEM
|
|
//&& ~iqentry_memready[head0]
|
|
//&& ~iqentry_memready[head1]
|
|
//&& ~iqentry_memready[head2]
|
|
//&& ~iqentry_memready[head3]
|
|
//&& ~iqentry_memready[head4]
|
|
//&& ~iqentry_memready[head5]
|
|
//&& ~iqentry_memready[head6]
|
|
// ... and there is no address-overlap with any preceding instruction
|
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0]
|
|
|| (iqentry_a1_v[head0] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0])))
|
|
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1]) || iqentry_done[head1]
|
|
|| (iqentry_a1_v[head1] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head1][AMSB:3] || iqentry_out[head1] || iqentry_done[head1])))
|
|
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2]) || iqentry_done[head2]
|
|
|| (iqentry_a1_v[head2] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head2][AMSB:3] || iqentry_out[head2] || iqentry_done[head2])))
|
|
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3]) || iqentry_done[head3]
|
|
|| (iqentry_a1_v[head3] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head3][AMSB:3] || iqentry_out[head3] || iqentry_done[head3])))
|
|
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4]) || iqentry_done[head4]
|
|
|| (iqentry_a1_v[head4] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head4][AMSB:3] || iqentry_out[head4] || iqentry_done[head4])))
|
|
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5]) || iqentry_done[head5]
|
|
|| (iqentry_a1_v[head5] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head5][AMSB:3] || iqentry_out[head5] || iqentry_done[head5])))
|
|
&& (!iqentry_mem[head6] || (iqentry_agen[head6] & iqentry_out[head6]) || iqentry_done[head6]
|
|
|| (iqentry_a1_v[head6] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head6][AMSB:3] || iqentry_out[head6] || iqentry_done[head6])))
|
|
&& (!iqentry_mem[head7] || (iqentry_agen[head7] & iqentry_out[head7]) || iqentry_done[head7]
|
|
|| (iqentry_a1_v[head7] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head7][AMSB:3] || iqentry_out[head7] || iqentry_done[head7])))
|
|
&& (!iqentry_mem[head8] || (iqentry_agen[head8] & iqentry_out[head8]) || iqentry_done[head8]
|
|
|| (iqentry_a1_v[head8] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head8][AMSB:3] || iqentry_out[head8] || iqentry_done[head8])))
|
|
&& (iqentry_rl[head9] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
|
&& (iqentry_done[head4] || !iqentry_v[head4] || !iqentry_mem[head4])
|
|
&& (iqentry_done[head5] || !iqentry_v[head5] || !iqentry_mem[head5])
|
|
&& (iqentry_done[head6] || !iqentry_v[head6] || !iqentry_mem[head6])
|
|
&& (iqentry_done[head7] || !iqentry_v[head7] || !iqentry_mem[head7])
|
|
&& (iqentry_done[head8] || !iqentry_v[head8] || !iqentry_mem[head8])
|
|
: 1'b1)
|
|
// ... if a preivous op has the aquire bit set
|
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
|
&& !(iqentry_aq[head1] && iqentry_v[head1])
|
|
&& !(iqentry_aq[head2] && iqentry_v[head2])
|
|
&& !(iqentry_aq[head3] && iqentry_v[head3])
|
|
&& !(iqentry_aq[head4] && iqentry_v[head4])
|
|
&& !(iqentry_aq[head5] && iqentry_v[head5])
|
|
&& !(iqentry_aq[head6] && iqentry_v[head6])
|
|
&& !(iqentry_aq[head7] && iqentry_v[head7])
|
|
&& !(iqentry_aq[head8] && iqentry_v[head8])
|
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
|
&& (!(iqentry_iv[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
|
&& (!(iqentry_iv[head2] && iqentry_memsb[head2]) ||
|
|
((iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (iqentry_done[head1] || !iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_iv[head3] && iqentry_memsb[head3]) ||
|
|
((iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (iqentry_done[head2] || !iqentry_v[head2]))
|
|
)
|
|
&& (!(iqentry_iv[head4] && iqentry_memsb[head4]) ||
|
|
((iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (iqentry_done[head3] || !iqentry_v[head3]))
|
|
)
|
|
&& (!(iqentry_iv[head5] && iqentry_memsb[head5]) ||
|
|
((iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (iqentry_done[head3] || !iqentry_v[head3])
|
|
&& (iqentry_done[head4] || !iqentry_v[head4]))
|
|
)
|
|
&& (!(iqentry_iv[head6] && iqentry_memsb[head6]) ||
|
|
((iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (iqentry_done[head3] || !iqentry_v[head3])
|
|
&& (iqentry_done[head4] || !iqentry_v[head4])
|
|
&& (iqentry_done[head5] || !iqentry_v[head5]))
|
|
)
|
|
&& (!(iqentry_iv[head7] && iqentry_memsb[head7]) ||
|
|
((iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (iqentry_done[head3] || !iqentry_v[head3])
|
|
&& (iqentry_done[head4] || !iqentry_v[head4])
|
|
&& (iqentry_done[head5] || !iqentry_v[head5])
|
|
&& (iqentry_done[head6] || !iqentry_v[head6]))
|
|
)
|
|
&& (!(iqentry_iv[head8] && iqentry_memsb[head8]) ||
|
|
((iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (iqentry_done[head3] || !iqentry_v[head3])
|
|
&& (iqentry_done[head4] || !iqentry_v[head4])
|
|
&& (iqentry_done[head5] || !iqentry_v[head5])
|
|
&& (iqentry_done[head6] || !iqentry_v[head6])
|
|
&& (iqentry_done[head7] || !iqentry_v[head7])
|
|
)
|
|
)
|
|
&& (!(iqentry_iv[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
|
&& (!(iqentry_iv[head2] && iqentry_memdb[head2]) ||
|
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]))
|
|
)
|
|
&& (!(iqentry_iv[head3] && iqentry_memdb[head3]) ||
|
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]))
|
|
)
|
|
&& (!(iqentry_iv[head4] && iqentry_memdb[head4]) ||
|
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]))
|
|
)
|
|
&& (!(iqentry_iv[head5] && iqentry_memdb[head5]) ||
|
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])
|
|
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4]))
|
|
)
|
|
&& (!(iqentry_iv[head6] && iqentry_memdb[head6]) ||
|
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])
|
|
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4])
|
|
&& (!iqentry_mem[head5] || iqentry_done[head5] || !iqentry_v[head5]))
|
|
)
|
|
&& (!(iqentry_iv[head7] && iqentry_memdb[head7]) ||
|
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])
|
|
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4])
|
|
&& (!iqentry_mem[head5] || iqentry_done[head5] || !iqentry_v[head5])
|
|
&& (!iqentry_mem[head6] || iqentry_done[head6] || !iqentry_v[head6]))
|
|
)
|
|
&& (!(iqentry_iv[head8] && iqentry_memdb[head8]) ||
|
|
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])
|
|
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4])
|
|
&& (!iqentry_mem[head5] || iqentry_done[head5] || !iqentry_v[head5])
|
|
&& (!iqentry_mem[head6] || iqentry_done[head6] || !iqentry_v[head6])
|
|
&& (!iqentry_mem[head7] || iqentry_done[head7] || !iqentry_v[head7])
|
|
)
|
|
)
|
|
// ... and, if it is a SW, there is no chance of it being undone
|
|
&& (iqentry_load[head9] ||
|
|
!(iqentry_fc[head0]||iqentry_canex[head0])
|
|
&& !(iqentry_fc[head1]||iqentry_canex[head1])
|
|
&& !(iqentry_fc[head2]||iqentry_canex[head2])
|
|
&& !(iqentry_fc[head3]||iqentry_canex[head3])
|
|
&& !(iqentry_fc[head4]||iqentry_canex[head4])
|
|
&& !(iqentry_fc[head5]||iqentry_canex[head5])
|
|
&& !(iqentry_fc[head6]||iqentry_canex[head6])
|
|
&& !(iqentry_fc[head7]||iqentry_canex[head7])
|
|
&& !(iqentry_fc[head8]||iqentry_canex[head8])
|
|
);
|
`endif
|
`endif
|
end
|
end
|
|
|
reg [2:0] wbptr;
|
reg [2:0] wbptr;
|
always @*
|
always @*
|
| Line 5563... |
Line 6075... |
for (n = 0; n < QENTRIES; n = n + 1)
|
for (n = 0; n < QENTRIES; n = n + 1)
|
iqentry_memopsvalid[n] <= (iqentry_mem[n] & iqentry_a2_v[n] & iqentry_agen[n]);
|
iqentry_memopsvalid[n] <= (iqentry_mem[n] & iqentry_a2_v[n] & iqentry_agen[n]);
|
|
|
always @*
|
always @*
|
for (n = 0; n < QENTRIES; n = n + 1)
|
for (n = 0; n < QENTRIES; n = n + 1)
|
iqentry_memready[n] <= (iqentry_v[n] & iqentry_memopsvalid[n] & ~iqentry_memissue[n] & ~iqentry_done[n] & ~iqentry_out[n] & ~iqentry_stomp[n]);
|
iqentry_memready[n] <= (iqentry_v[n] & iqentry_iv[n] & iqentry_memopsvalid[n] & ~iqentry_memissue[n] & ~iqentry_done[n] & ~iqentry_out[n] & ~iqentry_stomp[n]);
|
|
|
assign outstanding_stores = (dram0 && dram0_store) ||
|
assign outstanding_stores = (dram0 && dram0_store) ||
|
(dram1 && dram1_store) ||
|
(dram1 && dram1_store) ||
|
(dram2 && dram2_store);
|
(dram2 && dram2_store);
|
|
|
| Line 6631... |
Line 7143... |
if ((fetchbuf0_v && fetchbuf0_pc==misspc) ||
|
if ((fetchbuf0_v && fetchbuf0_pc==misspc) ||
|
(fetchbuf1_v && fetchbuf1_pc==misspc))
|
(fetchbuf1_v && fetchbuf1_pc==misspc))
|
fcu_clearbm <= `TRUE;
|
fcu_clearbm <= `TRUE;
|
end
|
end
|
|
|
if (mem1_available && dramA_v && iqentry_v[ dramA_id[`QBITS] ] && iqentry_load[ dramA_id[`QBITS] ]) begin
|
if (mem1_available && dramA_v && iqentry_v[ dramA_id[`QBITS] ] && iqentry_load[ dramA_id[`QBITS] ] && !iqentry_stomp[dramA_id[`QBITS]]) begin
|
iqentry_res [ dramA_id[`QBITS] ] <= dramA_bus;
|
iqentry_res [ dramA_id[`QBITS] ] <= dramA_bus;
|
iqentry_exc [ dramA_id[`QBITS] ] <= dramA_exc;
|
iqentry_exc [ dramA_id[`QBITS] ] <= dramA_exc;
|
iqentry_done[ dramA_id[`QBITS] ] <= `VAL;
|
iqentry_done[ dramA_id[`QBITS] ] <= `VAL;
|
iqentry_out [ dramA_id[`QBITS] ] <= `INV;
|
iqentry_out [ dramA_id[`QBITS] ] <= `INV;
|
iqentry_cmt [ dramA_id[`QBITS] ] <= `VAL;
|
iqentry_cmt [ dramA_id[`QBITS] ] <= `VAL;
|
iqentry_aq [ dramA_id[`QBITS] ] <= `INV;
|
iqentry_aq [ dramA_id[`QBITS] ] <= `INV;
|
end
|
end
|
if (mem2_available && `NUM_MEM > 1 && dramB_v && iqentry_v[ dramB_id[`QBITS] ] && iqentry_load[ dramB_id[`QBITS] ]) begin
|
if (mem2_available && `NUM_MEM > 1 && dramB_v && iqentry_v[ dramB_id[`QBITS] ] && iqentry_load[ dramB_id[`QBITS] ] && !iqentry_stomp[dramB_id[`QBITS]]) begin
|
iqentry_res [ dramB_id[`QBITS] ] <= dramB_bus;
|
iqentry_res [ dramB_id[`QBITS] ] <= dramB_bus;
|
iqentry_exc [ dramB_id[`QBITS] ] <= dramB_exc;
|
iqentry_exc [ dramB_id[`QBITS] ] <= dramB_exc;
|
iqentry_done[ dramB_id[`QBITS] ] <= `VAL;
|
iqentry_done[ dramB_id[`QBITS] ] <= `VAL;
|
iqentry_out [ dramB_id[`QBITS] ] <= `INV;
|
iqentry_out [ dramB_id[`QBITS] ] <= `INV;
|
iqentry_cmt [ dramB_id[`QBITS] ] <= `VAL;
|
iqentry_cmt [ dramB_id[`QBITS] ] <= `VAL;
|
iqentry_aq [ dramB_id[`QBITS] ] <= `INV;
|
iqentry_aq [ dramB_id[`QBITS] ] <= `INV;
|
end
|
end
|
if (mem3_available && `NUM_MEM > 2 && dramC_v && iqentry_v[ dramC_id[`QBITS] ] && iqentry_load[ dramC_id[`QBITS] ]) begin
|
if (mem3_available && `NUM_MEM > 2 && dramC_v && iqentry_v[ dramC_id[`QBITS] ] && iqentry_load[ dramC_id[`QBITS] ] && !iqentry_stomp[dramC_id[`QBITS]]) begin
|
iqentry_res [ dramC_id[`QBITS] ] <= dramC_bus;
|
iqentry_res [ dramC_id[`QBITS] ] <= dramC_bus;
|
iqentry_exc [ dramC_id[`QBITS] ] <= dramC_exc;
|
iqentry_exc [ dramC_id[`QBITS] ] <= dramC_exc;
|
iqentry_done[ dramC_id[`QBITS] ] <= `VAL;
|
iqentry_done[ dramC_id[`QBITS] ] <= `VAL;
|
iqentry_out [ dramC_id[`QBITS] ] <= `INV;
|
iqentry_out [ dramC_id[`QBITS] ] <= `INV;
|
iqentry_cmt [ dramC_id[`QBITS] ] <= `VAL;
|
iqentry_cmt [ dramC_id[`QBITS] ] <= `VAL;
|
| Line 7072... |
Line 7584... |
|
|
//
|
//
|
// grab requests that have finished and put them on the dram_bus
|
// grab requests that have finished and put them on the dram_bus
|
if (mem1_available && dram0 == `DRAMREQ_READY) begin
|
if (mem1_available && dram0 == `DRAMREQ_READY) begin
|
dram0 <= `DRAMSLOT_AVAIL;
|
dram0 <= `DRAMSLOT_AVAIL;
|
dramA_v <= dram0_load;
|
dramA_v <= dram0_load && !iqentry_stomp[dram0_id[`QBITS]];
|
dramA_id <= dram0_id;
|
dramA_id <= dram0_id;
|
dramA_exc <= dram0_exc;
|
dramA_exc <= dram0_exc;
|
dramA_bus <= fnDati(dram0_instr,dram0_addr,rdat0);
|
dramA_bus <= fnDati(dram0_instr,dram0_addr,rdat0);
|
if (dram0_store) $display("m[%h] <- %h", dram0_addr, dram0_data);
|
if (dram0_store) $display("m[%h] <- %h", dram0_addr, dram0_data);
|
end
|
end
|
// else
|
// else
|
// dramA_v <= `INV;
|
// dramA_v <= `INV;
|
if (mem2_available && dram1 == `DRAMREQ_READY && `NUM_MEM > 1) begin
|
if (mem2_available && dram1 == `DRAMREQ_READY && `NUM_MEM > 1) begin
|
dram1 <= `DRAMSLOT_AVAIL;
|
dram1 <= `DRAMSLOT_AVAIL;
|
dramB_v <= dram1_load;
|
dramB_v <= dram1_load && !iqentry_stomp[dram1_id[`QBITS]];
|
dramB_id <= dram1_id;
|
dramB_id <= dram1_id;
|
dramB_exc <= dram1_exc;
|
dramB_exc <= dram1_exc;
|
dramB_bus <= fnDati(dram1_instr,dram1_addr,rdat1);
|
dramB_bus <= fnDati(dram1_instr,dram1_addr,rdat1);
|
if (dram1_store) $display("m[%h] <- %h", dram1_addr, dram1_data);
|
if (dram1_store) $display("m[%h] <- %h", dram1_addr, dram1_data);
|
end
|
end
|
// else
|
// else
|
// dramB_v <= `INV;
|
// dramB_v <= `INV;
|
if (mem3_available && dram2 == `DRAMREQ_READY && `NUM_MEM > 2) begin
|
if (mem3_available && dram2 == `DRAMREQ_READY && `NUM_MEM > 2) begin
|
dram2 <= `DRAMSLOT_AVAIL;
|
dram2 <= `DRAMSLOT_AVAIL;
|
dramC_v <= dram2_load;
|
dramC_v <= dram2_load && !iqentry_stomp[dram2_id[`QBITS]];
|
dramC_id <= dram2_id;
|
dramC_id <= dram2_id;
|
dramC_exc <= dram2_exc;
|
dramC_exc <= dram2_exc;
|
dramC_bus <= fnDati(dram2_instr,dram2_addr,rdat2);
|
dramC_bus <= fnDati(dram2_instr,dram2_addr,rdat2);
|
if (dram2_store) $display("m[%h] <- %h", dram2_addr, dram2_data);
|
if (dram2_store) $display("m[%h] <- %h", dram2_addr, dram2_data);
|
end
|
end
|
|
/*
|
|
// Squash load results for stomped on instructions
|
|
begin
|
|
if (iqentry_stomp[dram0_id[`QBITS]])
|
|
dram0_load <= `FALSE;
|
|
if (`NUM_MEM > 1)
|
|
if (iqentry_stomp[dram1_id[`QBITS]])
|
|
dram1_load <= `FALSE;
|
|
if (`NUM_MEM > 2)
|
|
if (iqentry_stomp[dram2_id[`QBITS]])
|
|
dram2_load <= `FALSE;
|
|
end
|
|
*/
|
|
|
// else
|
// else
|
// dramC_v <= `INV;
|
// dramC_v <= `INV;
|
|
|
//
|
//
|
// determine if the instructions ready to issue can, in fact, issue.
|
// determine if the instructions ready to issue can, in fact, issue.
|
| Line 7403... |
Line 7929... |
picstate <= icstate;
|
picstate <= icstate;
|
case(icstate)
|
case(icstate)
|
IDLE:
|
IDLE:
|
// If the bus unit is busy doing an update involving L1_adr or L2_adr
|
// If the bus unit is busy doing an update involving L1_adr or L2_adr
|
// we have to wait.
|
// we have to wait.
|
if (bstate != B7 && bstate != B9) begin
|
if (bstate != B_ICacheAck && bstate != B_ICacheNack) begin
|
if (!ihit0) begin
|
if (!ihit0) begin
|
L1_adr <= {pcr[5:0],pc0[31:5],5'h0};
|
L1_adr <= {pcr[5:0],pc0[31:5],5'h0};
|
L2_adr <= {pcr[5:0],pc0[31:5],5'h0};
|
L2_adr <= {pcr[5:0],pc0[31:5],5'h0};
|
L1_invline <= TRUE;
|
L1_invline <= TRUE;
|
icwhich <= 2'b00;
|
icwhich <= 2'b00;
|
| Line 7443... |
Line 7969... |
icstate <= IC2;
|
icstate <= IC2;
|
end
|
end
|
end
|
end
|
IC2: icstate <= IC3;
|
IC2: icstate <= IC3;
|
IC3: icstate <= IC3a;
|
IC3: icstate <= IC3a;
|
IC3a: icstate <= IC4;
|
IC3a: icstate <= IC_WaitL2;
|
// If data was in the L2 cache already there's no need to wait on the
|
// If data was in the L2 cache already there's no need to wait on the
|
// BIU to retrieve data. It can be determined if the hit signal was
|
// BIU to retrieve data. It can be determined if the hit signal was
|
// already active when this state was entered in which case waiting
|
// already active when this state was entered in which case waiting
|
// will do no good.
|
// will do no good.
|
// The IC machine will stall in this state until the BIU has loaded the
|
// The IC machine will stall in this state until the BIU has loaded the
|
// L2 cache.
|
// L2 cache.
|
IC4:
|
IC_WaitL2:
|
if (ihitL2 && picstate==IC3a) begin
|
if (ihitL2 && picstate==IC3a) begin
|
L1_en <= 9'h1FF;
|
L1_en <= 9'h1FF;
|
L1_wr0 <= TRUE;
|
L1_wr0 <= TRUE;
|
L1_wr1 <= TRUE && `WAYS > 1;
|
L1_wr1 <= TRUE && `WAYS > 1;
|
L1_wr2 <= TRUE && `WAYS > 2;
|
L1_wr2 <= TRUE && `WAYS > 2;
|
L1_adr <= L2_adr;
|
L1_adr <= L2_adr;
|
L2_rdat <= L2_dato;
|
L2_rdat <= L2_dato;
|
icstate <= IC5;
|
icstate <= IC5;
|
end
|
end
|
else if (bstate!=B9)
|
else if (bstate!=B_ICacheNack)
|
;
|
;
|
else begin
|
else begin
|
L1_en <= 9'h1FF;
|
L1_en <= 9'h1FF;
|
L1_wr0 <= TRUE;
|
L1_wr0 <= TRUE;
|
L1_wr1 <= TRUE && `WAYS > 1;
|
L1_wr1 <= TRUE && `WAYS > 1;
|
L1_wr2 <= TRUE && `WAYS > 2;
|
L1_wr2 <= TRUE && `WAYS > 2;
|
L1_adr <= L2_adr;
|
L1_adr <= L2_adr;
|
L2_rdat <= L2_dato;
|
// L2_rdat set below while loading cache line
|
|
//L2_rdat <= L2_dato;
|
icstate <= IC5;
|
icstate <= IC5;
|
end
|
end
|
IC5:
|
IC5:
|
begin
|
begin
|
L1_en <= 9'h000;
|
L1_en <= 9'h000;
|
| Line 7480... |
Line 8007... |
L1_wr1 <= FALSE;
|
L1_wr1 <= FALSE;
|
L1_wr2 <= FALSE;
|
L1_wr2 <= FALSE;
|
icstate <= IC6;
|
icstate <= IC6;
|
end
|
end
|
IC6: icstate <= IC7;
|
IC6: icstate <= IC7;
|
IC7: icstate <= IC8;
|
IC7: icstate <= IC_Next;
|
IC8: begin
|
IC_Next:
|
|
begin
|
icstate <= IDLE;
|
icstate <= IDLE;
|
icnxt <= TRUE;
|
icnxt <= TRUE;
|
end
|
end
|
default: icstate <= IDLE;
|
default: icstate <= IDLE;
|
endcase
|
endcase
|
|
|
if (mem1_available && dram0_load)
|
if (mem1_available && dram0_load)
|
case(dram0)
|
case(dram0)
|
`DRAMSLOT_AVAIL: ;
|
`DRAMSLOT_AVAIL: ;
|
`DRAMSLOT_BUSY: dram0 <= dram0 + !dram0_unc;
|
`DRAMSLOT_BUSY:
|
3'd2: dram0 <= dram0 + 3'd1;
|
dram0 <= dram0 + !dram0_unc;
|
3'd3: dram0 <= dram0 + 3'd1;
|
3'd2:
|
3'd4: if (dhit0) dram0 <= `DRAMREQ_READY; else dram0 <= `DRAMSLOT_REQBUS;
|
dram0 <= dram0 + 3'd1;
|
|
3'd3:
|
|
dram0 <= dram0 + 3'd1;
|
|
3'd4:
|
|
if (iqentry_v[dram0_id[`QBITS]] && !iqentry_stomp[dram0_id[`QBITS]]) begin
|
|
if (dhit0)
|
|
dram0 <= `DRAMREQ_READY;
|
|
else
|
|
dram0 <= `DRAMSLOT_REQBUS;
|
|
end
|
|
else begin
|
|
dram0 <= `DRAMSLOT_AVAIL;
|
|
dram0_load <= `FALSE;
|
|
end
|
`DRAMSLOT_REQBUS: ;
|
`DRAMSLOT_REQBUS: ;
|
`DRAMSLOT_HASBUS: ;
|
`DRAMSLOT_HASBUS: ;
|
`DRAMREQ_READY: ;
|
`DRAMREQ_READY: ;
|
endcase
|
endcase
|
|
|
if (mem2_available && dram1_load && `NUM_MEM > 1)
|
if (mem2_available && dram1_load && `NUM_MEM > 1)
|
case(dram1)
|
case(dram1)
|
`DRAMSLOT_AVAIL: ;
|
`DRAMSLOT_AVAIL: ;
|
`DRAMSLOT_BUSY: dram1 <= dram1 + !dram1_unc;
|
`DRAMSLOT_BUSY:
|
3'd2: dram1 <= dram1 + 3'd1;
|
dram1 <= dram1 + !dram1_unc;
|
3'd3: dram1 <= dram1 + 3'd1;
|
3'd2:
|
3'd4: if (dhit1) dram1 <= `DRAMREQ_READY; else dram1 <= `DRAMSLOT_REQBUS;
|
dram1 <= dram1 + 3'd1;
|
|
3'd3:
|
|
dram1 <= dram1 + 3'd1;
|
|
3'd4:
|
|
if (iqentry_v[dram1_id[`QBITS]] && !iqentry_stomp[dram1_id[`QBITS]]) begin
|
|
if (dhit1)
|
|
dram1 <= `DRAMREQ_READY;
|
|
else
|
|
dram1 <= `DRAMSLOT_REQBUS;
|
|
end
|
|
else begin
|
|
dram1 <= `DRAMSLOT_AVAIL;
|
|
dram1_load <= `FALSE;
|
|
end
|
`DRAMSLOT_REQBUS: ;
|
`DRAMSLOT_REQBUS: ;
|
`DRAMSLOT_HASBUS: ;
|
`DRAMSLOT_HASBUS: ;
|
`DRAMREQ_READY: ;
|
`DRAMREQ_READY: ;
|
endcase
|
endcase
|
|
|
if (mem3_available && dram2_load && `NUM_MEM > 2)
|
if (mem3_available && dram2_load && `NUM_MEM > 2)
|
case(dram2)
|
case(dram2)
|
`DRAMSLOT_AVAIL: ;
|
`DRAMSLOT_AVAIL: ;
|
`DRAMSLOT_BUSY: dram2 <= dram2 + !dram2_unc;
|
`DRAMSLOT_BUSY:
|
3'd2: dram2 <= dram2 + 3'd1;
|
dram2 <= dram2 + !dram2_unc;
|
3'd3: dram2 <= dram2 + 3'd1;
|
3'd2:
|
3'd4: if (dhit2) dram2 <= `DRAMREQ_READY; else dram2 <= `DRAMSLOT_REQBUS;
|
dram2 <= dram2 + 3'd1;
|
|
3'd3:
|
|
dram2 <= dram2 + 3'd1;
|
|
3'd4:
|
|
if (iqentry_v[dram2_id[`QBITS]] && !iqentry_stomp[dram2_id[`QBITS]]) begin
|
|
if (dhit2)
|
|
dram2 <= `DRAMREQ_READY;
|
|
else
|
|
dram2 <= `DRAMSLOT_REQBUS;
|
|
end
|
|
else begin
|
|
dram2 <= `DRAMSLOT_AVAIL;
|
|
dram2_load <= `FALSE;
|
|
end
|
`DRAMSLOT_REQBUS: ;
|
`DRAMSLOT_REQBUS: ;
|
`DRAMSLOT_HASBUS: ;
|
`DRAMSLOT_HASBUS: ;
|
`DRAMREQ_READY: ;
|
`DRAMREQ_READY: ;
|
endcase
|
endcase
|
|
|
| Line 7921... |
Line 8488... |
// L2_adr <= icwhich ? {pc0[31:5],5'b0} : {pc1[31:5],5'b0};
|
// L2_adr <= icwhich ? {pc0[31:5],5'b0} : {pc1[31:5],5'b0};
|
adr_o <= {pcr[5:0],L1_adr[31:5],5'h0};
|
adr_o <= {pcr[5:0],L1_adr[31:5],5'h0};
|
ol_o <= ol[0];
|
ol_o <= ol[0];
|
L2_adr <= {pcr[5:0],L1_adr[31:5],5'h0};
|
L2_adr <= {pcr[5:0],L1_adr[31:5],5'h0};
|
L2_xsel <= 1'b0;
|
L2_xsel <= 1'b0;
|
bstate <= B7;
|
bstate <= B_ICacheAck;
|
end
|
end
|
end
|
end
|
// Terminal state for a store operation.
|
// Terminal state for a store operation.
|
// Note that if only a single memory channel is selected, bwhich will be a
|
// Note that if only a single memory channel is selected, bwhich will be a
|
// constant 0. This should cause the extra code to be removed.
|
// constant 0. This should cause the extra code to be removed.
|
| Line 8078... |
Line 8645... |
if (dram2 != `DRAMSLOT_AVAIL && dram2_addr[31:5]==adr_o[31:5]) dram2 <= `DRAMSLOT_BUSY;
|
if (dram2 != `DRAMSLOT_AVAIL && dram2_addr[31:5]==adr_o[31:5]) dram2 <= `DRAMSLOT_BUSY;
|
if (~ack_i) bstate <= BIDLE;
|
if (~ack_i) bstate <= BIDLE;
|
end
|
end
|
|
|
// Ack state for instruction cache load
|
// Ack state for instruction cache load
|
B7:
|
B_ICacheAck:
|
if (ack_i|err_i) begin
|
if (ack_i|err_i) begin
|
errq <= errq | err_i;
|
errq <= errq | err_i;
|
exvq <= exvq | exv_i;
|
exvq <= exvq | exv_i;
|
// L1_en <= 9'h3 << {L2_xsel,L2_adr[4:3],1'b0};
|
// L1_en <= 9'h3 << {L2_xsel,L2_adr[4:3],1'b0};
|
// L1_wr0 <= `TRUE;
|
// L1_wr0 <= `TRUE;
|
// L1_wr1 <= `TRUE;
|
// L1_wr1 <= `TRUE;
|
// L1_adr <= L2_adr;
|
// L1_adr <= L2_adr;
|
if (err_i)
|
if (err_i)
|
L2_rdat <= {9{11'b0,4'd7,1'b0,`FLT_IBE,2'b00,`BRK}};
|
L2_rdat <= {18{`INSN_FLT_IBE}};
|
else
|
else
|
L2_rdat <= {dat_i[31:0],{4{dat_i}}};
|
case(iccnt)
|
|
3'd0: L2_rdat[63:0] <= dat_i;
|
|
3'd1: L2_rdat[127:64] <= dat_i;
|
|
3'd2: L2_rdat[191:128] <= dat_i;
|
|
3'd3: L2_rdat[255:192] <= dat_i;
|
|
3'd4: L2_rdat[287:256] <= dat_i[31:0];
|
|
default: ;
|
|
endcase
|
|
//L2_rdat <= {dat_i[31:0],{4{dat_i}}};
|
iccnt <= iccnt + 3'd1;
|
iccnt <= iccnt + 3'd1;
|
//stb_o <= `LOW;
|
//stb_o <= `LOW;
|
if (iccnt==3'd3)
|
if (iccnt==3'd3)
|
cti_o <= 3'b111;
|
cti_o <= 3'b111;
|
if (iccnt==3'd4) begin
|
if (iccnt==3'd4) begin
|
| Line 8101... |
Line 8676... |
bte_o <= 2'b00; // linear burst
|
bte_o <= 2'b00; // linear burst
|
cyc_o <= `LOW;
|
cyc_o <= `LOW;
|
stb_o <= `LOW;
|
stb_o <= `LOW;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
icl_o <= `LOW;
|
icl_o <= `LOW;
|
bstate <= B9;
|
bstate <= B_ICacheNack;
|
end
|
end
|
else begin
|
else begin
|
L2_adr[4:3] <= L2_adr[4:3] + 2'd1;
|
L2_adr[4:3] <= L2_adr[4:3] + 2'd1;
|
if (L2_adr[4:3]==2'b11)
|
if (L2_adr[4:3]==2'b11)
|
L2_xsel <= 1'b1;
|
L2_xsel <= 1'b1;
|
end
|
end
|
end
|
end
|
B9:
|
B_ICacheNack:
|
begin
|
begin
|
L1_wr0 <= `FALSE;
|
L1_wr0 <= `FALSE;
|
L1_wr1 <= `FALSE;
|
L1_wr1 <= `FALSE;
|
L1_wr2 <= `FALSE;
|
L1_wr2 <= `FALSE;
|
L1_en <= 9'h1FF;
|
L1_en <= 9'h1FF;
|
| Line 8547... |
Line 9122... |
$display("");
|
$display("");
|
end
|
end
|
if (|panic && ~outstanding_stores) begin
|
if (|panic && ~outstanding_stores) begin
|
$finish;
|
$finish;
|
end
|
end
|
for (n = 0; n < QENTRIES; n = n + 1)
|
/*
|
if (branchmiss) begin
|
for (n = 0; n < QENTRIES; n = n + 1)
|
if (!setpred[n]) begin
|
if (branchmiss) begin
|
iqentry_instr[n][`INSTRUCTION_OP] <= `NOP;
|
if (!setpred[n]) begin
|
iqentry_done[n] <= `VAL;
|
iqentry_instr[n][`INSTRUCTION_OP] <= `NOP;
|
iqentry_cmt[n] <= `VAL;
|
iqentry_done[n] <= iqentry_v[n];
|
end
|
iqentry_cmt[n] <= iqentry_v[n];
|
end
|
end
|
|
end
|
|
*/
|
if (snr) begin
|
if (snr) begin
|
seq_num <= 32'd0;
|
seq_num <= 32'd0;
|
seq_num1 <= 32'd0;
|
seq_num1 <= 32'd0;
|
end
|
end
|
end // clock domain
|
end // clock domain
|
