| Line 7... |
Line 7... |
//
|
//
|
// FT64_BTB.v
|
// FT64_BTB.v
|
//
|
//
|
// ============================================================================
|
// ============================================================================
|
//
|
//
|
module FT64_BTB(rst, wclk, wr, wadr, wdat, valid, rclk, pcA, btgtA, pcB, btgtB, pcC, btgtC, pcD, btgtD,
|
module FT64_BTB(rst, wclk, wr, wadr, wdat, valid, rclk, pcA, btgtA, pcB, btgtB,
|
npcA, npcB, npcC, npcD);
|
pcC, btgtC, pcD, btgtD, pcE, btgtE, pcF, btgtF,
|
|
npcA, npcB, npcC, npcD, npcE, npcF);
|
parameter AMSB = 31;
|
parameter AMSB = 31;
|
parameter RSTPC = 32'hFFFC0100;
|
parameter RSTPC = 32'hFFFC0100;
|
input rst;
|
input rst;
|
input wclk;
|
input wclk;
|
input wr;
|
input wr;
|
| Line 26... |
Line 27... |
output [AMSB:0] btgtB;
|
output [AMSB:0] btgtB;
|
input [AMSB:0] pcC;
|
input [AMSB:0] pcC;
|
output [AMSB:0] btgtC;
|
output [AMSB:0] btgtC;
|
input [AMSB:0] pcD;
|
input [AMSB:0] pcD;
|
output [AMSB:0] btgtD;
|
output [AMSB:0] btgtD;
|
|
input [AMSB:0] pcE;
|
|
output [AMSB:0] btgtE;
|
|
input [AMSB:0] pcF;
|
|
output [AMSB:0] btgtF;
|
input [AMSB:0] npcA;
|
input [AMSB:0] npcA;
|
input [AMSB:0] npcB;
|
input [AMSB:0] npcB;
|
input [AMSB:0] npcC;
|
input [AMSB:0] npcC;
|
input [AMSB:0] npcD;
|
input [AMSB:0] npcD;
|
|
input [AMSB:0] npcE;
|
|
input [AMSB:0] npcF;
|
|
|
integer n;
|
integer n;
|
reg [(AMSB+1)*2+1:0] mem [0:1023];
|
reg [(AMSB+1)*2+1:0] mem [0:1023];
|
reg [9:0] radrA, radrB, radrC, radrD;
|
reg [9:0] radrA, radrB, radrC, radrD, radrE, radrF;
|
initial begin
|
initial begin
|
for (n = 0; n < 1024; n = n + 1)
|
for (n = 0; n < 1024; n = n + 1)
|
mem[n] <= RSTPC;
|
mem[n] <= RSTPC;
|
end
|
end
|
always @(posedge wclk)
|
always @(posedge wclk)
|
| Line 52... |
Line 59... |
#1 radrB <= pcB[11:2];
|
#1 radrB <= pcB[11:2];
|
always @(posedge rclk)
|
always @(posedge rclk)
|
#1 radrC <= pcC[11:2];
|
#1 radrC <= pcC[11:2];
|
always @(posedge rclk)
|
always @(posedge rclk)
|
#1 radrD <= pcD[11:2];
|
#1 radrD <= pcD[11:2];
|
|
always @(posedge rclk)
|
|
#1 radrE <= pcE[11:2];
|
|
always @(posedge rclk)
|
|
#1 radrF <= pcF[11:2];
|
wire hitA = mem[radrA][(AMSB+1)*2:AMSB+1]==pcA && mem[radrA][(AMSB+1)*2+1];
|
wire hitA = mem[radrA][(AMSB+1)*2:AMSB+1]==pcA && mem[radrA][(AMSB+1)*2+1];
|
wire hitB = mem[radrB][(AMSB+1)*2:AMSB+1]==pcB && mem[radrB][(AMSB+1)*2+1];
|
wire hitB = mem[radrB][(AMSB+1)*2:AMSB+1]==pcB && mem[radrB][(AMSB+1)*2+1];
|
wire hitC = mem[radrC][(AMSB+1)*2:AMSB+1]==pcC && mem[radrC][(AMSB+1)*2+1];
|
wire hitC = mem[radrC][(AMSB+1)*2:AMSB+1]==pcC && mem[radrC][(AMSB+1)*2+1];
|
wire hitD = mem[radrD][(AMSB+1)*2:AMSB+1]==pcD && mem[radrD][(AMSB+1)*2+1];
|
wire hitD = mem[radrD][(AMSB+1)*2:AMSB+1]==pcD && mem[radrD][(AMSB+1)*2+1];
|
|
wire hitE = mem[radrE][(AMSB+1)*2:AMSB+1]==pcE && mem[radrE][(AMSB+1)*2+1];
|
|
wire hitF = mem[radrF][(AMSB+1)*2:AMSB+1]==pcF && mem[radrF][(AMSB+1)*2+1];
|
assign btgtA = hitA ? mem[radrA][AMSB:0] : npcA;
|
assign btgtA = hitA ? mem[radrA][AMSB:0] : npcA;
|
assign btgtB = hitB ? mem[radrB][AMSB:0] : npcB;
|
assign btgtB = hitB ? mem[radrB][AMSB:0] : npcB;
|
assign btgtC = hitC ? mem[radrC][AMSB:0] : npcC;
|
assign btgtC = hitC ? mem[radrC][AMSB:0] : npcC;
|
assign btgtD = hitD ? mem[radrD][AMSB:0] : npcD;
|
assign btgtD = hitD ? mem[radrD][AMSB:0] : npcD;
|
|
assign btgtE = hitE ? mem[radrE][AMSB:0] : npcE;
|
|
assign btgtF = hitF ? mem[radrF][AMSB:0] : npcF;
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
