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//
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//
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//=============================================================================
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//=============================================================================
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//
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//
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module FT64_BranchPredictor(rst, clk, en,
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module FT64_BranchPredictor(rst, clk, en,
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xisBranch0, xisBranch1,
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xisBranch0, xisBranch1,
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pcA, pcB, pcC, pcD, xpc0, xpc1, takb0, takb1,
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pcA, pcB, pcC, pcD, pcE, pcF, xpc0, xpc1, takb0, takb1,
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predict_takenA, predict_takenB, predict_takenC, predict_takenD);
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predict_takenA, predict_takenB, predict_takenC, predict_takenD,
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predict_takenE, predict_takenF);
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parameter DBW=32;
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parameter DBW=32;
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input rst;
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input rst;
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input clk;
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input clk;
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input en;
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input en;
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input xisBranch0;
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input xisBranch0;
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input xisBranch1;
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input xisBranch1;
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input [DBW-1:0] pcA;
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input [DBW-1:0] pcA;
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input [DBW-1:0] pcB;
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input [DBW-1:0] pcB;
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input [DBW-1:0] pcC;
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input [DBW-1:0] pcC;
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input [DBW-1:0] pcD;
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input [DBW-1:0] pcD;
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input [DBW-1:0] pcE;
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input [DBW-1:0] pcF;
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input [DBW-1:0] xpc0;
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input [DBW-1:0] xpc0;
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input [DBW-1:0] xpc1;
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input [DBW-1:0] xpc1;
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input takb0;
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input takb0;
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input takb1;
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input takb1;
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output predict_takenA;
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output predict_takenA;
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output predict_takenB;
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output predict_takenB;
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output predict_takenC;
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output predict_takenC;
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output predict_takenD;
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output predict_takenD;
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output predict_takenE;
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output predict_takenF;
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integer n;
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integer n;
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reg [31:0] pcs [0:31];
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reg [31:0] pcs [0:31];
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reg [31:0] pc;
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reg [31:0] pc;
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reg takb;
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reg takb;
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wire [8:0] bht_wa = {pc[8:2],gbl_branch_hist[2:1]}; // write address
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wire [8:0] bht_wa = {pc[8:2],gbl_branch_hist[2:1]}; // write address
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wire [8:0] bht_raA = {pcA[8:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raA = {pcA[8:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raB = {pcB[8:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raB = {pcB[8:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raC = {pcC[8:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raC = {pcC[8:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raD = {pcD[8:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raD = {pcD[8:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raE = {pcE[8:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raF = {pcF[8:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [1:0] bht_xbits = branch_history_table[bht_wa];
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wire [1:0] bht_xbits = branch_history_table[bht_wa];
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wire [1:0] bht_ibitsA = branch_history_table[bht_raA];
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wire [1:0] bht_ibitsA = branch_history_table[bht_raA];
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wire [1:0] bht_ibitsB = branch_history_table[bht_raB];
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wire [1:0] bht_ibitsB = branch_history_table[bht_raB];
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wire [1:0] bht_ibitsC = branch_history_table[bht_raC];
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wire [1:0] bht_ibitsC = branch_history_table[bht_raC];
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wire [1:0] bht_ibitsD = branch_history_table[bht_raD];
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wire [1:0] bht_ibitsD = branch_history_table[bht_raD];
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wire [1:0] bht_ibitsE = branch_history_table[bht_raE];
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wire [1:0] bht_ibitsF = branch_history_table[bht_raF];
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assign predict_takenA = (bht_ibitsA==2'd0 || bht_ibitsA==2'd1) && en;
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assign predict_takenA = (bht_ibitsA==2'd0 || bht_ibitsA==2'd1) && en;
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assign predict_takenB = (bht_ibitsB==2'd0 || bht_ibitsB==2'd1) && en;
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assign predict_takenB = (bht_ibitsB==2'd0 || bht_ibitsB==2'd1) && en;
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assign predict_takenC = (bht_ibitsC==2'd0 || bht_ibitsC==2'd1) && en;
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assign predict_takenC = (bht_ibitsC==2'd0 || bht_ibitsC==2'd1) && en;
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assign predict_takenD = (bht_ibitsD==2'd0 || bht_ibitsD==2'd1) && en;
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assign predict_takenD = (bht_ibitsD==2'd0 || bht_ibitsD==2'd1) && en;
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assign predict_takenE = (bht_ibitsE==2'd0 || bht_ibitsE==2'd1) && en;
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assign predict_takenF = (bht_ibitsF==2'd0 || bht_ibitsF==2'd1) && en;
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always @(posedge clk)
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always @(posedge clk)
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if (rst)
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if (rst)
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pcstail <= 5'd0;
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pcstail <= 5'd0;
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else begin
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else begin
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