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Line 23... |
//
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//
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//
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//
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//=============================================================================
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//=============================================================================
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//
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//
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module FT64_BranchPredictor(rst, clk, en,
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module FT64_BranchPredictor(rst, clk, en,
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xisBranch0, xisBranch1,
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xisBranch0, xisBranch1, xisBranch2,
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pcA, pcB, pcC, pcD, pcE, pcF, xpc0, xpc1, takb0, takb1,
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pcA, pcB, pcC, pcD, pcE, pcF, xpc0, xpc1, xpc2, takb0, takb1, takb2,
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predict_takenA, predict_takenB, predict_takenC, predict_takenD,
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predict_takenA, predict_takenB, predict_takenC, predict_takenD,
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predict_takenE, predict_takenF);
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predict_takenE, predict_takenF);
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parameter DBW=32;
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parameter DBW=32;
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input rst;
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input rst;
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input clk;
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input clk;
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input en;
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input en;
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input xisBranch0;
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input xisBranch0;
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input xisBranch1;
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input xisBranch1;
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input xisBranch2;
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input [DBW-1:0] pcA;
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input [DBW-1:0] pcA;
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input [DBW-1:0] pcB;
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input [DBW-1:0] pcB;
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input [DBW-1:0] pcC;
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input [DBW-1:0] pcC;
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input [DBW-1:0] pcD;
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input [DBW-1:0] pcD;
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input [DBW-1:0] pcE;
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input [DBW-1:0] pcE;
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input [DBW-1:0] pcF;
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input [DBW-1:0] pcF;
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input [DBW-1:0] xpc0;
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input [DBW-1:0] xpc0;
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input [DBW-1:0] xpc1;
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input [DBW-1:0] xpc1;
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input [DBW-1:0] xpc2;
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input takb0;
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input takb0;
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input takb1;
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input takb1;
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input takb2;
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output predict_takenA;
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output predict_takenA;
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output predict_takenB;
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output predict_takenB;
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output predict_takenC;
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output predict_takenC;
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output predict_takenD;
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output predict_takenD;
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output predict_takenE;
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output predict_takenE;
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Line 68... |
initial begin
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initial begin
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gbl_branch_hist = 3'b000;
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gbl_branch_hist = 3'b000;
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for (n = 0; n < 512; n = n + 1)
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for (n = 0; n < 512; n = n + 1)
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branch_history_table[n] = 3;
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branch_history_table[n] = 3;
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end
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end
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wire [8:0] bht_wa = {pc[8:2],gbl_branch_hist[2:1]}; // write address
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wire [8:0] bht_wa = {pc[7:1],gbl_branch_hist[2:1]}; // write address
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wire [8:0] bht_raA = {pcA[8:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raA = {pcA[7:1],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raB = {pcB[8:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raB = {pcB[7:1],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raC = {pcC[8:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raC = {pcC[7:1],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raD = {pcD[8:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raD = {pcD[7:1],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raE = {pcE[8:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raE = {pcE[7:1],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raF = {pcF[8:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [8:0] bht_raF = {pcF[7:1],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [1:0] bht_xbits = branch_history_table[bht_wa];
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wire [1:0] bht_xbits = branch_history_table[bht_wa];
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wire [1:0] bht_ibitsA = branch_history_table[bht_raA];
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wire [1:0] bht_ibitsA = branch_history_table[bht_raA];
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wire [1:0] bht_ibitsB = branch_history_table[bht_raB];
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wire [1:0] bht_ibitsB = branch_history_table[bht_raB];
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wire [1:0] bht_ibitsC = branch_history_table[bht_raC];
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wire [1:0] bht_ibitsC = branch_history_table[bht_raC];
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wire [1:0] bht_ibitsD = branch_history_table[bht_raD];
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wire [1:0] bht_ibitsD = branch_history_table[bht_raD];
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Line 93... |
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always @(posedge clk)
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always @(posedge clk)
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if (rst)
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if (rst)
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pcstail <= 5'd0;
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pcstail <= 5'd0;
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else begin
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else begin
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if (xisBranch0 & xisBranch1) begin
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case({xisBranch0,xisBranch1,xisBranch2})
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pcs[pcstail] <= {xpc0[31:1],takb0};
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3'b000: ;
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pcs[pcstail+1] <= {xpc1[31:1],takb1};
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3'b001:
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pcstail <= pcstail + 5'd2;
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begin
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pcs[pcstail] <= {xpc2[31:1],takb2};
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pcstail <= pcstail + 5'd1;
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end
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end
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else if (xisBranch0) begin
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3'b010:
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pcs[pcstail] <= {xpc0[31:1],takb0};
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begin
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pcs[pcstail] <= {xpc1[31:1],takb1};
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pcstail <= pcstail + 5'd1;
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pcstail <= pcstail + 5'd1;
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end
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end
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else if (xisBranch1) begin
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3'b011:
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begin
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pcs[pcstail] <= {xpc1[31:1],takb1};
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pcs[pcstail] <= {xpc1[31:1],takb1};
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pcs[pcstail+1] <= {xpc2[31:1],takb2};
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pcstail <= pcstail + 5'd2;
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end
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3'b100:
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begin
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pcs[pcstail] <= {xpc0[31:1],takb0};
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pcstail <= pcstail + 5'd1;
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pcstail <= pcstail + 5'd1;
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end
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end
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3'b101:
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begin
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pcs[pcstail] <= {xpc0[31:1],takb0};
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pcs[pcstail+1] <= {xpc2[31:1],takb2};
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pcstail <= pcstail + 5'd2;
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end
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3'b110:
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begin
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pcs[pcstail] <= {xpc0[31:1],takb0};
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pcs[pcstail+1] <= {xpc1[31:1],takb1};
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pcstail <= pcstail + 5'd2;
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end
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3'b111:
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begin
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pcs[pcstail] <= {xpc0[31:1],takb0};
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pcs[pcstail+1] <= {xpc1[31:1],takb1};
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pcs[pcstail+2] <= {xpc2[31:1],takb2};
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pcstail <= pcstail + 5'd3;
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end
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endcase
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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if (rst)
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if (rst)
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pcshead <= 5'd0;
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pcshead <= 5'd0;
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