| Line 20... |
Line 20... |
// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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`include "FT64_config.vh"
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`include "FT64_defines.vh"
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`include "FT64_defines.vh"
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// FETCH
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// FETCH
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//
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//
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// fetch exactly two instructions from memory into the fetch buffer
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// fetch exactly two instructions from memory into the fetch buffer
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// unless either one of the buffers is still full, in which case we
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// unless either one of the buffers is still full, in which case we
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// do nothing (kinda like alpha approach)
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// do nothing (kinda like alpha approach)
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// Like to turn this into an independent module at some point.
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// Like to turn this into an independent module at some point.
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//
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//
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module FT64_fetchbuf(rst, clk4x, clk,
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module FT64_fetchbuf(rst, clk4x, clk, fcu_clk,
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cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i,
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cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i,
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hirq, thread_en,
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hirq, thread_en,
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regLR,
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regLR,
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insn0, insn1, phit,
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insn0, insn1, phit,
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threadx,
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threadx,
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| Line 51... |
Line 52... |
fetchbuf0_v, fetchbuf1_v,
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fetchbuf0_v, fetchbuf1_v,
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codebuf0, codebuf1,
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codebuf0, codebuf1,
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btgtA, btgtB, btgtC, btgtD,
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btgtA, btgtB, btgtC, btgtD,
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nop_fetchbuf,
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nop_fetchbuf,
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take_branch0, take_branch1,
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take_branch0, take_branch1,
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stompedRets
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stompedRets,
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panic
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);
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);
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parameter AMSB = 31;
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parameter AMSB = `AMSB;
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parameter RSTPC = 32'hFFFC0100;
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parameter RSTPC = 32'hFFFC0100;
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parameter TRUE = 1'b1;
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parameter TRUE = 1'b1;
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parameter FALSE = 1'b0;
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parameter FALSE = 1'b0;
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input rst;
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input rst;
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input clk4x;
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input clk4x;
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input clk;
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input clk;
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input fcu_clk;
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input cs_i;
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input cs_i;
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input cyc_i;
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input cyc_i;
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input stb_i;
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input stb_i;
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output ack_o;
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output ack_o;
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input we_i;
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input we_i;
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| Line 121... |
Line 124... |
input [AMSB:0] btgtD;
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input [AMSB:0] btgtD;
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input [3:0] nop_fetchbuf;
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input [3:0] nop_fetchbuf;
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output take_branch0;
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output take_branch0;
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output take_branch1;
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output take_branch1;
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input [3:0] stompedRets;
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input [3:0] stompedRets;
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output reg [3:0] panic;
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integer n;
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integer n;
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//`include "FT64_decode.vh"
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//`include "FT64_decode.vh"
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|
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function IsBranch;
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function IsBranch;
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| Line 277... |
Line 280... |
pc1 <= thread_en ? (fetchbuf ? pc1b : pc1a) : pc1a;
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pc1 <= thread_en ? (fetchbuf ? pc1b : pc1a) : pc1a;
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end
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end
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*/
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*/
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assign threadx = fetchbuf;
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assign threadx = fetchbuf;
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`ifdef FCU_ENH
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FT64_RSB #(AMSB) ursb1
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FT64_RSB #(AMSB) ursb1
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(
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(
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.rst(rst),
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.rst(rst),
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.clk(clk),
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.clk(fcu_clk),
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.regLR(regLR),
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.regLR(regLR),
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.queued1(queued1),
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.queued1(queued1),
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.queued2(queued2),
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.queued2(queued2),
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.fetchbuf0_v(fetchbuf0_v),
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.fetchbuf0_v(fetchbuf0_v),
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.fetchbuf0_pc(fetchbuf0_pc),
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.fetchbuf0_pc(fetchbuf0_pc),
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| Line 298... |
Line 302... |
);
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);
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|
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FT64_RSB #(AMSB) ursb2
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FT64_RSB #(AMSB) ursb2
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(
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(
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.rst(rst),
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.rst(rst),
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.clk(clk),
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.clk(fcu_clk),
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.regLR(regLR),
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.regLR(regLR),
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.queued1(queued1),
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.queued1(queued1),
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.queued2(1'b0),
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.queued2(1'b0),
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.fetchbuf0_v(fetchbuf1_v),
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.fetchbuf0_v(fetchbuf1_v),
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.fetchbuf0_pc(fetchbuf1_pc),
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.fetchbuf0_pc(fetchbuf1_pc),
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| Line 312... |
Line 316... |
.fetchbuf1_instr(`NOP_INSN),
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.fetchbuf1_instr(`NOP_INSN),
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.stompedRets(stompedRets[3:1]),
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.stompedRets(stompedRets[3:1]),
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.stompedRet(stompedRet),
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.stompedRet(stompedRet),
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.pc(retpc1)
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.pc(retpc1)
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);
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);
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`else
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assign retpc0 = RSTPC;
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assign retpc1 = RSTPC;
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`endif
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wire peclk, neclk;
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wire peclk, neclk;
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edge_det ued1 (.rst(rst), .clk(clk4x), .ce(1'b1), .i(clk), .pe(peclk), .ne(neclk), .ee());
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edge_det ued1 (.rst(rst), .clk(clk4x), .ce(1'b1), .i(clk), .pe(peclk), .ne(neclk), .ee());
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|
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always @(posedge clk)
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always @(posedge clk)
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| Line 327... |
Line 335... |
fetchbufA_v <= 0;
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fetchbufA_v <= 0;
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fetchbufB_v <= 0;
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fetchbufB_v <= 0;
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fetchbufC_v <= 0;
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fetchbufC_v <= 0;
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fetchbufD_v <= 0;
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fetchbufD_v <= 0;
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fetchbuf <= 0;
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fetchbuf <= 0;
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panic <= `PANIC_NONE;
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end
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end
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else begin
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else begin
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did_branchback0 <= take_branch0;
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did_branchback0 <= take_branch0;
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did_branchback1 <= take_branch1;
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did_branchback1 <= take_branch1;
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Line 354... |
// keep things simple. For the thread that doesn't miss the current
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// keep things simple. For the thread that doesn't miss the current
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// data for the fetch buffer needs to be retrieved again, so the pc
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// data for the fetch buffer needs to be retrieved again, so the pc
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// for that thread is assigned the current fetchbuf pc.
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// for that thread is assigned the current fetchbuf pc.
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// For the thread that misses the pc is simply assigned the misspc.
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// For the thread that misses the pc is simply assigned the misspc.
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if (branchmiss) begin
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if (branchmiss) begin
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$display("***********");
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$display("Branch miss");
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$display("***********");
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if (branchmiss_thrd) begin
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if (branchmiss_thrd) begin
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pc0 <= fetchbuf0_pc;
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pc0 <= fetchbuf0_pc;
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`ifdef SUPPORT_SMT
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`ifdef SUPPORT_SMT
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pc1 <= misspc;
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pc1 <= misspc;
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`endif
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`endif
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| Line 719... |
Line 731... |
4'b11_11 : begin // enqueue both and flip fetchbuf
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4'b11_11 : begin // enqueue both and flip fetchbuf
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fetchbufA_v <= `INV;
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fetchbufA_v <= `INV;
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fetchbufB_v <= `INV;
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fetchbufB_v <= `INV;
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fetchbuf <= ~fetchbuf;
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fetchbuf <= ~fetchbuf;
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end
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end
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default: ;
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default: panic <= `PANIC_INVALIDIQSTATE;
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endcase
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endcase
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else case ({fetchbufC_v, fetchbufD_v, (queued1|queuedNop), (queued2|queuedNop)})
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else case ({fetchbufC_v, fetchbufD_v, (queued1|queuedNop), (queued2|queuedNop)})
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4'b00_00 : ; // do nothing
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4'b00_00 : ; // do nothing
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// 4'b00_01 : panic <= `PANIC_INVALIDIQSTATE;
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// 4'b00_01 : panic <= `PANIC_INVALIDIQSTATE;
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4'b00_10 : ; // do nothing
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4'b00_10 : ; // do nothing
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| Line 756... |
Line 768... |
4'b11_11 : begin // enqueue both and flip fetchbuf
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4'b11_11 : begin // enqueue both and flip fetchbuf
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fetchbufC_v <= `INV;
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fetchbufC_v <= `INV;
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fetchbufD_v <= `INV;
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fetchbufD_v <= `INV;
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fetchbuf <= ~fetchbuf;
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fetchbuf <= ~fetchbuf;
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end
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end
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default: ;
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default: panic <= `PANIC_INVALIDIQSTATE;
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endcase
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endcase
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//
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//
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// get data iff the fetch buffers are empty
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// get data iff the fetch buffers are empty
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//
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//
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if (fetchbufA_v == `INV && fetchbufB_v == `INV) begin
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if (fetchbufA_v == `INV && fetchbufB_v == `INV) begin
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| Line 852... |
Line 864... |
fetchbufA_pc <= pc0;
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fetchbufA_pc <= pc0;
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if (phit && ~hirq)
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if (phit && ~hirq)
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`ifdef SUPPORT_SMT
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`ifdef SUPPORT_SMT
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pc0 <= pc0 + fetchbuf0_insln;
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pc0 <= pc0 + fetchbuf0_insln;
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`else
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`else
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if (`WAYS > 1)
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pc0 <= pc0 + fetchbuf0_insln + fetchbuf1_insln;
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pc0 <= pc0 + fetchbuf0_insln + fetchbuf1_insln;
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else
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pc0 <= pc0 + fetchbuf0_insln;
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`endif
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`endif
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end
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end
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endtask
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endtask
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task FetchB;
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task FetchB;
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begin
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begin
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fetchbufB_instr <= cinsn1;
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fetchbufB_instr <= cinsn1;
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fetchbufB_v <= `VAL;
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fetchbufB_v <= `WAYS > 1;
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`ifdef SUPPORT_SMT
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fetchbufB_pc <= pc1;
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fetchbufB_pc <= pc1;
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`ifdef SUPPORT_SMT
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if (phit)
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if (phit)
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pc1 <= pc1 + fetchbuf1_insln;
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pc1 <= pc1 + fetchbuf1_insln;
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`else
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fetchbufB_pc <= pc0 + fetchbuf0_insln;
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`endif
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`endif
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end
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end
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endtask
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endtask
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| Line 888... |
Line 901... |
fetchbufC_pc <= pc0;
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fetchbufC_pc <= pc0;
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if (phit && ~hirq)
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if (phit && ~hirq)
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`ifdef SUPPORT_SMT
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`ifdef SUPPORT_SMT
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pc0 <= pc0 + fetchbuf0_insln;
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pc0 <= pc0 + fetchbuf0_insln;
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`else
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`else
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if (`WAYS > 1)
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pc0 <= pc0 + fetchbuf0_insln + fetchbuf1_insln;
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pc0 <= pc0 + fetchbuf0_insln + fetchbuf1_insln;
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else
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pc0 <= pc0 + fetchbuf0_insln;
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`endif
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`endif
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end
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end
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endtask
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endtask
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task FetchD;
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task FetchD;
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begin
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begin
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fetchbufD_instr <= cinsn1;
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fetchbufD_instr <= cinsn1;
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fetchbufD_v <= `VAL;
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fetchbufD_v <= `WAYS > 1;
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`ifdef SUPPORT_SMT
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fetchbufD_pc <= pc1;
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fetchbufD_pc <= pc1;
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`ifdef SUPPORT_SMT
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if (phit)
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if (phit)
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pc1 <= pc1 + fetchbuf1_insln;
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pc1 <= pc1 + fetchbuf1_insln;
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`else
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fetchbufD_pc <= pc0 + fetchbuf0_insln;
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`endif
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`endif
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end
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end
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endtask
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endtask
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task FetchCD;
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task FetchCD;
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