| Line 32... |
Line 32... |
// do nothing (kinda like alpha approach)
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// do nothing (kinda like alpha approach)
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// Like to turn this into an independent module at some point.
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// Like to turn this into an independent module at some point.
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//
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//
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module FT64_fetchbuf(rst, clk4x, clk, fcu_clk,
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module FT64_fetchbuf(rst, clk4x, clk, fcu_clk,
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cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i,
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cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i,
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cmpgrp,
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freezePC, thread_en,
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freezePC, thread_en,
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regLR,
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regLR,
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insn0, insn1, phit,
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insn0, insn1, phit,
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threadx,
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threadx,
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branchmiss, misspc, branchmiss_thrd, predict_taken0, predict_taken1,
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branchmiss, misspc, branchmiss_thrd, predict_taken0, predict_taken1,
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| Line 70... |
Line 71... |
input stb_i;
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input stb_i;
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output ack_o;
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output ack_o;
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input we_i;
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input we_i;
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input [15:0] adr_i;
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input [15:0] adr_i;
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input [31:0] dat_i;
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input [31:0] dat_i;
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input [2:0] cmpgrp;
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input freezePC;
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input freezePC;
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input thread_en;
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input thread_en;
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input [4:0] regLR;
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input [4:0] regLR;
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input [47:0] insn0;
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input [47:0] insn0;
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input [47:0] insn1;
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input [47:0] insn1;
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| Line 162... |
Line 164... |
IsRTI = isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_S2]==`RTI;
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IsRTI = isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_S2]==`RTI;
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endfunction
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endfunction
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function [3:0] fnInsLength;
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function [3:0] fnInsLength;
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input [47:0] ins;
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input [47:0] ins;
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if (ins[`INSTRUCTION_OP]==`CMPRSSD)
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fnInsLength = 4'd2;
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else
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case(ins[7:6])
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case(ins[7:6])
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2'd0: fnInsLength = 4'd4;
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2'd0: fnInsLength = 4'd4;
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2'd1: fnInsLength = 4'd6;
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2'd1: fnInsLength = 4'd6;
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default: fnInsLength = 4'd2;
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default: fnInsLength = 4'd2;
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endcase
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endcase
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| Line 189... |
Line 194... |
|
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Table of decompressed instructions.
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// Table of decompressed instructions.
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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assign ack_o = cs_i & cyc_i & stb_i;
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assign ack_o = cs_i & cyc_i & stb_i;
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reg [47:0] DecompressTable [0:1023];
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reg [47:0] DecompressTable [0:2047];
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always @(posedge clk)
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always @(posedge clk)
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if (cs_i & cyc_i & stb_i & we_i)
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if (cs_i & cyc_i & stb_i & we_i)
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DecompressTable[adr_i[11:2]] <= dat_i;
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DecompressTable[adr_i[12:3]] <= dat_i;
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wire [47:0] expand0 = DecompressTable[insn0[15:6]];
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wire [47:0] expand0 = DecompressTable[{cmpgrp,insn0[15:8]}];
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wire [47:0] expand1 = DecompressTable[insn1[15:6]];
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wire [47:0] expand1 = DecompressTable[{cmpgrp,insn1[15:8]}];
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|
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|
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reg thread;
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reg thread;
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| Line 796... |
Line 801... |
assign fetchbuf0_thrd = 1'b0;
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assign fetchbuf0_thrd = 1'b0;
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assign fetchbuf1_thrd = thread_en;
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assign fetchbuf1_thrd = thread_en;
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|
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always @*
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always @*
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begin
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begin
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if (insn0[7:6]==2'b00 && insn0[`INSTRUCTION_OP]==`EXEC)
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if (insn0[5:0]==`CMPRSSD)
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fetchbuf0_insln <= 4'd2;
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else if (insn0[7:6]==2'b00 && insn0[`INSTRUCTION_OP]==`EXEC)
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fetchbuf0_insln <= fnInsLength(codebuf0);
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fetchbuf0_insln <= fnInsLength(codebuf0);
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else
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else
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fetchbuf0_insln <= fnInsLength(insn0);
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fetchbuf0_insln <= fnInsLength(insn0);
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end
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end
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always @*
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always @*
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begin
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begin
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if (insn1[7:6]==2'b00 && insn1[`INSTRUCTION_OP]==`EXEC)
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if (insn1[5:0]==`CMPRSSD)
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fetchbuf1_insln <= 4'd2;
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else if (insn1[7:6]==2'b00 && insn1[`INSTRUCTION_OP]==`EXEC)
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fetchbuf1_insln <= fnInsLength(codebuf1);
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fetchbuf1_insln <= fnInsLength(codebuf1);
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else
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else
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fetchbuf1_insln <= fnInsLength(insn1);
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fetchbuf1_insln <= fnInsLength(insn1);
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end
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end
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|
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reg [47:0] cinsn0, cinsn1;
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reg [47:0] cinsn0, cinsn1;
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|
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always @*
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always @*
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begin
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begin
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if (insn0[7:6]==2'b00 && insn0[`INSTRUCTION_OP]==`EXEC)
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if (insn0[5:0]==`CMPRSSD)
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cinsn0 <= expand0;
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else if (insn0[7:6]==2'b00 && insn0[`INSTRUCTION_OP]==`EXEC)
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cinsn0 <= codebuf0;
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cinsn0 <= codebuf0;
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else if (insn0[7])
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else if (insn0[7])
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cinsn0 <= xinsn0;
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cinsn0 <= xinsn0;
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else
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else
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cinsn0 <= insn0;
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cinsn0 <= insn0;
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end
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end
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|
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always @*
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always @*
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begin
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begin
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if (insn1[7:6]==2'b00 && insn1[`INSTRUCTION_OP]==`EXEC)
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if (insn1[5:0]==`CMPRSSD)
|
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cinsn1 <= expand1;
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else if (insn1[7:6]==2'b00 && insn1[`INSTRUCTION_OP]==`EXEC)
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cinsn1 <= codebuf1;
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cinsn1 <= codebuf1;
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else if (insn1[7])
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else if (insn1[7])
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cinsn1 <= xinsn1;
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cinsn1 <= xinsn1;
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else
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else
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cinsn1 <= insn1;
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cinsn1 <= insn1;
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