| Line 1... |
Line 1... |
// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2017-2018 Robert Finch, Waterloo
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// \\__/ o\ (C) 2017-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// FT64_alu.v
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// FT64_alu.v
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| Line 23... |
Line 23... |
// ============================================================================
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// ============================================================================
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//
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//
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`include "FT64_defines.vh"
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`include "FT64_defines.vh"
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`include "FT64_config.vh"
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`include "FT64_config.vh"
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|
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module FT64_alu(rst, clk, ld, abort, instr, sz, tlb, store, a, b, c, pc, Ra, tgt, tgt2, ven, vm,
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module FT64_alu(rst, clk, ld, abort, instr, sz, tlb, store, a, b, c, t, pc, Ra, tgt, tgt2, ven, vm,
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csr, o, ob, done, idle, excen, exc, thrd, ptrmask, state, mem, shift,
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csr, o, ob, done, idle, excen, exc, thrd, ptrmask, state, mem, shift,
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ol, dl, ASID, icl_i, cyc_i, we_i, vadr_i, cyc_o, we_o, padr_o, uncached, tlb_miss,
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ol, dl, ASID, icl_i, cyc_i, we_i, vadr_i, cyc_o, we_o, padr_o, uncached, tlb_miss,
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exv_o, rdv_o, wrv_o
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exv_o, rdv_o, wrv_o
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`ifdef SUPPORT_SEGMENTATION
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, zs_base, ds_base, es_base, fs_base, gs_base, hs_base, ss_base, cs_base,
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zsub, dsub, esub, fsub, gsub, hsub, ssub, csub,
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zslb, dslb, eslb, fslb, gslb, hslb, sslb, cslb
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`endif
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`ifdef SUPPORT_BBMS
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`ifdef SUPPORT_BBMS
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, pb, cbl, cbu, ro, dbl, dbu, sbl, sbu, en
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, pb, cbl, cbu, ro, dbl, dbu, sbl, sbu, en
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`endif
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`endif
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);
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);
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parameter DBW = 64;
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parameter DBW = 64;
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| Line 43... |
Line 38... |
parameter BIG = 1'b1;
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parameter BIG = 1'b1;
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parameter SUP_VECTOR = 1;
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parameter SUP_VECTOR = 1;
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parameter TRUE = 1'b1;
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parameter TRUE = 1'b1;
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parameter FALSE = 1'b0;
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parameter FALSE = 1'b0;
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parameter PTR = 20'hFFF01;
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parameter PTR = 20'hFFF01;
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parameter BASE_SHIFT = 13'd0;
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input rst;
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input rst;
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input clk;
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input clk;
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input ld;
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input ld;
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input abort;
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input abort;
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input [47:0] instr;
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input [47:0] instr;
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| Line 54... |
Line 50... |
input tlb;
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input tlb;
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input store;
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input store;
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input [63:0] a;
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input [63:0] a;
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input [63:0] b;
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input [63:0] b;
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input [63:0] c;
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input [63:0] c;
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input [63:0] t; // target register value
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input [31:0] pc;
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input [31:0] pc;
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input [11:0] Ra;
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input [11:0] Ra;
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input [11:0] tgt;
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input [11:0] tgt;
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input [7:0] tgt2;
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input [7:0] tgt2;
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input [5:0] ven;
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input [5:0] ven;
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| Line 87... |
Line 84... |
output uncached;
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output uncached;
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output tlb_miss;
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output tlb_miss;
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output wrv_o;
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output wrv_o;
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output rdv_o;
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output rdv_o;
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output exv_o;
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output exv_o;
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`ifdef SUPPORT_SEGMENTATION
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input [63:0] zs_base;
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input [63:0] ds_base;
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input [63:0] es_base;
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input [63:0] fs_base;
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input [63:0] gs_base;
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input [63:0] hs_base;
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input [63:0] ss_base;
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input [63:0] cs_base;
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input [63:0] zslb;
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input [63:0] dslb;
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input [63:0] eslb;
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input [63:0] fslb;
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input [63:0] gslb;
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input [63:0] hslb;
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input [63:0] sslb;
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input [63:0] cslb;
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input [63:0] zsub;
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input [63:0] dsub;
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input [63:0] esub;
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input [63:0] fsub;
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input [63:0] gsub;
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input [63:0] hsub;
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input [63:0] ssub;
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input [63:0] csub;
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`endif
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`ifdef SUPPORT_BBMS
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`ifdef SUPPORT_BBMS
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input [63:0] pb;
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input [63:0] pb;
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input [63:0] cbl;
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input [63:0] cbl;
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input [63:0] cbu;
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input [63:0] cbu;
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input [63:0] ro;
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input [63:0] ro;
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| Line 138... |
Line 109... |
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integer n;
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integer n;
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|
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reg adrDone, adrIdle;
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reg adrDone, adrIdle;
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reg [63:0] usa; // unsegmented address
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reg [63:0] usa; // unsegmented address
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`ifdef SUPPORT_SEGMENTATION
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reg [63:0] pb;
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reg [63:0] ub;
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reg [63:0] lb;
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always @*
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case(usa[63:61])
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3'd0: pb <= zs_base;
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3'd1: pb <= ds_base;
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3'd2: pb <= es_base;
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3'd3: pb <= fs_base;
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3'd4: pb <= gs_base;
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3'd5: pb <= hs_base;
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3'd6: pb <= ss_base;
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3'd7: pb <= cs_base;
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endcase
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always @*
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case(usa[63:61])
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3'd0: ub <= zsub;
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3'd1: ub <= dsub;
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3'd2: ub <= esub;
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3'd3: ub <= fsub;
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3'd4: ub <= gsub;
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3'd5: ub <= hsub;
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3'd6: ub <= ssub;
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3'd7: ub <= csub;
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endcase
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always @*
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case(usa[63:61])
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3'd0: lb <= zslb;
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3'd1: lb <= dslb;
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3'd2: lb <= eslb;
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3'd3: lb <= fslb;
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3'd4: lb <= gslb;
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3'd5: lb <= hslb;
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3'd6: lb <= sslb;
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3'd7: lb <= cslb;
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endcase
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`else
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`ifndef SUPPORT_BBMS
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`ifndef SUPPORT_BBMS
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reg [63:0] pb = 64'h0;
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reg [63:0] pb = 64'h0;
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`endif
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`endif
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`endif
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reg [63:0] addro;
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reg [63:0] addro;
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reg [63:0] adr; // load / store address
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reg [63:0] adr; // load / store address
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reg [63:0] shift8;
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reg [63:0] shift8;
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|
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wire [7:0] a8 = a[7:0];
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wire [7:0] a8 = a[7:0];
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| Line 315... |
Line 247... |
endcase
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endcase
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endfunction
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endfunction
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|
|
function IsShiftAndOp;
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function IsShiftAndOp;
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input [47:0] isn;
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input [47:0] isn;
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if (isn[`INSTRUCTION_L2]==2'b01) begin
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case(isn[`INSTRUCTION_OP])
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`R2:
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case(isn[47:42])
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`SHIFTR: IsShiftAndOp = TRUE;
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default: IsShiftAndOp = FALSE;
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endcase
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default: IsShiftAndOp = FALSE;
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endcase
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|
end
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else
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IsShiftAndOp = FALSE;
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IsShiftAndOp = FALSE;
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endfunction
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endfunction
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|
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wire [63:0] bfout,shfto;
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wire [63:0] bfout,shfto;
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wire [63:0] shftob;
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wire [63:0] shftob;
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wire [63:0] shftco;
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wire [63:0] shftco;
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reg [63:0] shift10;
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|
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always @(posedge clk)
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always @(posedge clk)
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shift9 <= shift8;
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shift9 <= shift8;
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always @*
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case (instr[41:36])
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`ADD: shift10 <= shift9 + c;
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`SUB: shift10 <= shift9 - c;
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`AND: shift10 <= shift9 & c;
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`OR: shift10 <= shift9 | c;
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`XOR: shift10 <= shift9 ^ c;
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6'h20: shift10 <= ~shift9; // COM
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6'h21: shift10 <= !shift9; // NOT
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default: shift10 <= shift9;
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endcase
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|
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wire tlb_done, tlb_idle;
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wire tlb_done, tlb_idle;
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wire [DBW-1:0] tlbo;
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wire [DBW-1:0] tlbo;
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|
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`ifdef SUPPORT_TLB
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`ifdef SUPPORT_TLB
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| Line 621... |
Line 576... |
.dvByZr(divByZero),
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.dvByZr(divByZero),
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.done(div_done),
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.done(div_done),
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.idle(div_idle)
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.idle(div_idle)
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);
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);
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|
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wire [5:0] bshift = instr[31:26]==`SHIFTR ? b[5:0] : {instr[30],instr[22:18]};
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wire [5:0] bshift = IsShiftAndOp(instr) ? ( instr[29] ? {instr[28],instr[22:18]} : b[5:0])
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: (instr[31:26]==`SHIFTR ? b[5:0] : {instr[30],instr[22:18]});
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|
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FT64_shift ushft1
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FT64_shift ushft1
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(
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(
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.instr(instr),
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.instr(instr),
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.a(a),
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.a(a),
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| Line 798... |
Line 754... |
wire [63:0] redor64 = {63'd0,|a};
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wire [63:0] redor64 = {63'd0,|a};
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wire [63:0] redor32 = {31'd0,|a[63:32],31'd0,|a[31:0]};
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wire [63:0] redor32 = {31'd0,|a[63:32],31'd0,|a[31:0]};
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wire [63:0] redor16 = {15'd0,|a[63:48],15'd0,|a[47:32],15'd0,|a[31:16],15'd0,|a[15:0]};
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wire [63:0] redor16 = {15'd0,|a[63:48],15'd0,|a[47:32],15'd0,|a[31:16],15'd0,|a[15:0]};
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wire [63:0] redor8 = {7'b0,|a[63:56],6'b0,|a[55:48],7'd0,|a[47:40],7'd0,|a[39:32],7'd0,
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wire [63:0] redor8 = {7'b0,|a[63:56],6'b0,|a[55:48],7'd0,|a[47:40],7'd0,|a[39:32],7'd0,
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|a[31:24],7'd0,|a[23:16],7'd0,|a[15:8],7'd0,|a[7:0]};
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|a[31:24],7'd0,|a[23:16],7'd0,|a[15:8],7'd0,|a[7:0]};
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wire [63:0] redand64 = {63'd0,&a};
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wire [63:0] redand32 = {31'd0,&a[63:32],31'd0,&a[31:0]};
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wire [63:0] redand16 = {15'd0,&a[63:48],15'd0,&a[47:32],15'd0,&a[31:16],15'd0,&a[15:0]};
|
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wire [63:0] redand8 = {7'b0,&a[63:56],6'b0,&a[55:48],7'd0,&a[47:40],7'd0,&a[39:32],7'd0,
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|
&a[31:24],7'd0,&a[23:16],7'd0,&a[15:8],7'd0,&a[7:0]};
|
wire [63:0] zxb10 = {54'd0,b[9:0]};
|
wire [63:0] zxb10 = {54'd0,b[9:0]};
|
wire [63:0] sxb10 = {{54{b[9]}},b[9:0]};
|
wire [63:0] sxb10 = {{54{b[9]}},b[9:0]};
|
wire [63:0] zxb26 = {38'd0,instr[47:32],instr[27:18]};
|
wire [63:0] zxb26 = {38'd0,instr[47:32],instr[27:18]};
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wire [63:0] sxb26 = {{38{instr[47]}},instr[47:32],instr[27:18]};
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wire [63:0] sxb26 = {{38{instr[47]}},instr[47:32],instr[27:18]};
|
reg [15:0] mask;
|
reg [15:0] mask;
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| Line 976... |
Line 937... |
endcase
|
endcase
|
default: o[63:0] = 64'hDCDCDCDCDCDCDCDC;
|
default: o[63:0] = 64'hDCDCDCDCDCDCDCDC;
|
endcase
|
endcase
|
case(instr[35:33])
|
case(instr[35:33])
|
`ASL,`ASR,`SHL,`SHR,`ROL,`ROR:
|
`ASL,`ASR,`SHL,`SHR,`ROL,`ROR:
|
o[63:0] = shift9;
|
o[63:0] = shift10;
|
default: o[63:0] = 64'hDCDCDCDCDCDCDCDC;
|
default: o[63:0] = 64'hDCDCDCDCDCDCDCDC;
|
endcase
|
endcase
|
end
|
end
|
`MIN:
|
`MIN:
|
case(instr[30:28])
|
case(instr[30:28])
|
| Line 1037... |
Line 998... |
2'd0: o = {-a[63:56],-a[55:48],-a[47:40],-a[39:32],-a[31:24],-a[23:16],-a[15:8],-a[7:0]};
|
2'd0: o = {-a[63:56],-a[55:48],-a[47:40],-a[39:32],-a[31:24],-a[23:16],-a[15:8],-a[7:0]};
|
2'd1: o = {-a[63:48],-a[47:32],-a[31:16],-a[15:0]};
|
2'd1: o = {-a[63:48],-a[47:32],-a[31:16],-a[15:0]};
|
2'd2: o = {-a[63:32],-a[31:0]};
|
2'd2: o = {-a[63:32],-a[31:0]};
|
2'd3: o = -a;
|
2'd3: o = -a;
|
endcase
|
endcase
|
|
`REDAND:
|
|
case(sz[1:0])
|
|
2'd0: o = redand8;
|
|
2'd1: o = redand16;
|
|
2'd2: o = redand32;
|
|
2'd3: o = redand64;
|
|
endcase
|
`REDOR: case(sz[1:0])
|
`REDOR: case(sz[1:0])
|
2'd0: o = redor8;
|
2'd0: o = redor8;
|
2'd1: o = redor16;
|
2'd1: o = redor16;
|
2'd2: o = redor32;
|
2'd2: o = redor32;
|
2'd3: o = redor64;
|
2'd3: o = redor64;
|
| Line 1054... |
Line 1022... |
// 5'h1C: o[63:0] = tmem[a[9:0]];
|
// 5'h1C: o[63:0] = tmem[a[9:0]];
|
default: o = 64'hDEADDEADDEADDEAD;
|
default: o = 64'hDEADDEADDEADDEAD;
|
endcase
|
endcase
|
`BMM: o[63:0] = BIG ? bmmo : 64'hCCCCCCCCCCCCCCCC;
|
`BMM: o[63:0] = BIG ? bmmo : 64'hCCCCCCCCCCCCCCCC;
|
`SHIFT31,
|
`SHIFT31,
|
`SHIFT63,
|
`SHIFT63:
|
|
begin
|
|
if (instr[25:23]==`SHL || instr[25:23]==`ASL)
|
|
o = shfto;
|
|
else
|
|
o = BIG ? shfto : 64'hCCCCCCCCCCCCCCCC;
|
|
$display("BIG=%d",BIG);
|
|
if(!BIG)
|
|
$stop;
|
|
end
|
`SHIFTR:
|
`SHIFTR:
|
begin
|
begin
|
if (instr[25:23]==`SHL || instr[25:23]==`ASL)
|
if (instr[25:23]==`SHL || instr[25:23]==`ASL)
|
o[63:0] = shfto;
|
o = shfto;
|
else
|
else
|
o[63:0] = BIG ? shfto : 64'hCCCCCCCCCCCCCCCC;
|
o = BIG ? shfto : 64'hCCCCCCCCCCCCCCCC;
|
$display("BIG=%d",BIG);
|
$display("BIG=%d",BIG);
|
if(!BIG)
|
if(!BIG)
|
$stop;
|
$stop;
|
end
|
end
|
`ADD:
|
`ADD:
|
| Line 1099... |
Line 1076... |
end
|
end
|
endcase
|
endcase
|
`else
|
`else
|
o = a + b;
|
o = a + b;
|
`endif
|
`endif
|
|
// If the operation is SIMD the target register must be passed in arg T.
|
`SUB:
|
`SUB:
|
`ifdef SIMD
|
`ifdef SIMD
|
case(sz)
|
case(sz)
|
3'd0,3'd4:
|
3'd0:
|
|
begin
|
|
o[7:0] = a[7:0] - b[7:0];
|
|
o[63:8] = t[63:8];
|
|
end
|
|
3'd4:
|
begin
|
begin
|
o[7:0] = a[7:0] - b[7:0];
|
o[7:0] = a[7:0] - b[7:0];
|
o[15:8] = a[15:8] - b[15:8];
|
o[15:8] = a[15:8] - b[15:8];
|
o[23:16] = a[23:16] - b[23:16];
|
o[23:16] = a[23:16] - b[23:16];
|
o[31:24] = a[31:24] - b[31:24];
|
o[31:24] = a[31:24] - b[31:24];
|
| Line 1133... |
Line 1116... |
end
|
end
|
endcase
|
endcase
|
`else
|
`else
|
o = a - b;
|
o = a - b;
|
`endif
|
`endif
|
|
`SEQ: tskSeq(instr,instr[25:23],a,b,o);
|
`SLT: tskSlt(instr,instr[25:23],a,b,o);
|
`SLT: tskSlt(instr,instr[25:23],a,b,o);
|
`SLTU: tskSltu(instr,instr[25:23],a,b,o);
|
`SLTU: tskSltu(instr,instr[25:23],a,b,o);
|
`SLE: tskSle(instr,instr[25:23],a,b,o);
|
`SLE: tskSle(instr,instr[25:23],a,b,o);
|
`SLEU: tskSleu(instr,instr[25:23],a,b,o);
|
`SLEU: tskSleu(instr,instr[25:23],a,b,o);
|
`AND: o = and64;
|
`AND: o = and64;
|
| Line 1174... |
Line 1158... |
//o[63:44] = PTR;
|
//o[63:44] = PTR;
|
end
|
end
|
`MIN:
|
`MIN:
|
`ifdef SIMD
|
`ifdef SIMD
|
case(sz)
|
case(sz)
|
3'd0,3'd4:
|
3'd0:
|
|
begin
|
|
o[7:0] = BIG ? ($signed(a[7:0]) < $signed(b[7:0]) ? a[7:0] : b[7:0]) : 8'hCC;
|
|
o[63:8] = BIG ? t[63:8] : 56'hCCCCCCCCCCCCCC;
|
|
end
|
|
3'd1:
|
|
begin
|
|
o[15:0] = BIG ? ($signed(a[15:0]) < $signed(b[15:0]) ? a[15:0] : b[15:0]) : 16'hCCCC;
|
|
o[63:16] = BIG ? t[63:16] : 48'hCCCCCCCCCCCC;
|
|
end
|
|
3'd2:
|
|
begin
|
|
o[31:0] = BIG ? ($signed(a[31:0]) < $signed(b[31:0]) ? a[31:0] : b[31:0]) : 32'hCCCCCCCC;
|
|
o[63:32] = BIG ? t[63:32] : 32'hCCCCCCCC;
|
|
end
|
|
3'd3:
|
|
begin
|
|
o = BIG ? ($signed(a) < $signed(b) ? a : b) : 64'hCCCCCCCCCCCCCCCC;
|
|
end
|
|
3'd4:
|
begin
|
begin
|
o[7:0] = BIG ? ($signed(a[7:0]) < $signed(b[7:0]) ? a[7:0] : b[7:0]) : 8'hCC;
|
o[7:0] = BIG ? ($signed(a[7:0]) < $signed(b[7:0]) ? a[7:0] : b[7:0]) : 8'hCC;
|
o[15:8] = BIG ? ($signed(a[15:8]) < $signed(b[15:8]) ? a[15:8] : b[15:8]) : 64'hCCCCCCCCCCCCCCCC;
|
o[15:8] = BIG ? ($signed(a[15:8]) < $signed(b[15:8]) ? a[15:8] : b[15:8]) : 64'hCCCCCCCCCCCCCCCC;
|
o[23:16] = BIG ? ($signed(a[23:16]) < $signed(b[23:16]) ? a[23:16] : b[23:16]) : 64'hCCCCCCCCCCCCCCCC;
|
o[23:16] = BIG ? ($signed(a[23:16]) < $signed(b[23:16]) ? a[23:16] : b[23:16]) : 64'hCCCCCCCCCCCCCCCC;
|
o[31:24] = BIG ? ($signed(a[31:24]) < $signed(b[31:24]) ? a[31:24] : b[31:24]) : 64'hCCCCCCCCCCCCCCCC;
|
o[31:24] = BIG ? ($signed(a[31:24]) < $signed(b[31:24]) ? a[31:24] : b[31:24]) : 64'hCCCCCCCCCCCCCCCC;
|
o[39:32] = BIG ? ($signed(a[39:32]) < $signed(b[39:32]) ? a[39:32] : b[39:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[39:32] = BIG ? ($signed(a[39:32]) < $signed(b[39:32]) ? a[39:32] : b[39:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[47:40] = BIG ? ($signed(a[47:40]) < $signed(b[47:40]) ? a[47:40] : b[47:40]) : 64'hCCCCCCCCCCCCCCCC;
|
o[47:40] = BIG ? ($signed(a[47:40]) < $signed(b[47:40]) ? a[47:40] : b[47:40]) : 64'hCCCCCCCCCCCCCCCC;
|
o[55:48] = BIG ? ($signed(a[55:48]) < $signed(b[55:48]) ? a[55:48] : b[55:48]) : 64'hCCCCCCCCCCCCCCCC;
|
o[55:48] = BIG ? ($signed(a[55:48]) < $signed(b[55:48]) ? a[55:48] : b[55:48]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:56] = BIG ? ($signed(a[63:56]) < $signed(b[63:56]) ? a[63:56] : b[63:56]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:56] = BIG ? ($signed(a[63:56]) < $signed(b[63:56]) ? a[63:56] : b[63:56]) : 64'hCCCCCCCCCCCCCCCC;
|
end
|
end
|
3'd1,3'd5:
|
3'd5:
|
begin
|
begin
|
o[15:0] = BIG ? ($signed(a[15:0]) < $signed(b[15:0]) ? a[15:0] : b[15:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[15:0] = BIG ? ($signed(a[15:0]) < $signed(b[15:0]) ? a[15:0] : b[15:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[32:16] = BIG ? ($signed(a[32:16]) < $signed(b[32:16]) ? a[32:16] : b[32:16]) : 64'hCCCCCCCCCCCCCCCC;
|
o[32:16] = BIG ? ($signed(a[32:16]) < $signed(b[32:16]) ? a[32:16] : b[32:16]) : 64'hCCCCCCCCCCCCCCCC;
|
o[47:32] = BIG ? ($signed(a[47:32]) < $signed(b[47:32]) ? a[47:32] : b[47:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[47:32] = BIG ? ($signed(a[47:32]) < $signed(b[47:32]) ? a[47:32] : b[47:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:48] = BIG ? ($signed(a[63:48]) < $signed(b[63:48]) ? a[63:48] : b[63:48]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:48] = BIG ? ($signed(a[63:48]) < $signed(b[63:48]) ? a[63:48] : b[63:48]) : 64'hCCCCCCCCCCCCCCCC;
|
end
|
end
|
3'd2,3'd6:
|
3'd6:
|
begin
|
begin
|
o[31:0] = BIG ? ($signed(a[31:0]) < $signed(b[31:0]) ? a[31:0] : b[31:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[31:0] = BIG ? ($signed(a[31:0]) < $signed(b[31:0]) ? a[31:0] : b[31:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:32] = BIG ? ($signed(a[63:32]) < $signed(b[63:32]) ? a[63:32] : b[63:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:32] = BIG ? ($signed(a[63:32]) < $signed(b[63:32]) ? a[63:32] : b[63:32]) : 64'hCCCCCCCCCCCCCCCC;
|
end
|
end
|
3'd3,3'd7:
|
3'd7:
|
begin
|
begin
|
o[63:0] = BIG ? ($signed(a) < $signed(b) ? a : b) : 64'hCCCCCCCCCCCCCCCC;
|
o = BIG ? ($signed(a) < $signed(b) ? a : b) : 64'hCCCCCCCCCCCCCCCC;
|
end
|
end
|
endcase
|
endcase
|
`else
|
`else
|
o[63:0] = BIG ? ($signed(a) < $signed(b) ? a : b) : 64'hCCCCCCCCCCCCCCCC;
|
o = BIG ? ($signed(a) < $signed(b) ? a : b) : 64'hCCCCCCCCCCCCCCCC;
|
`endif
|
`endif
|
`MAX:
|
`MAX:
|
`ifdef SIMD
|
`ifdef SIMD
|
case(sz)
|
case(sz)
|
3'd0,3'd4:
|
3'd0,3'd4:
|
| Line 1285... |
Line 1288... |
`LBX,`LBUX,`LCX,`LCUX,
|
`LBX,`LBUX,`LCX,`LCUX,
|
`LVBX,`LVBUX,`LVCX,`LVCUX,`LVHX,`LVHUX,`LVWX,
|
`LVBX,`LVBUX,`LVCX,`LVCUX,`LVHX,`LVHUX,`LVWX,
|
`LHX,`LHUX,`LWX,`LWRX:
|
`LHX,`LHUX,`LWX,`LWRX:
|
if (BIG) begin
|
if (BIG) begin
|
usa = a + (c << instr[19:18]);
|
usa = a + (c << instr[19:18]);
|
o = {pb[50:0],13'd0} + usa;
|
o = {pb[50:0],BASE_SHIFT} + usa;
|
end
|
end
|
else
|
else
|
o = 64'hCCCCCCCCEEEEEEEE;
|
o = 64'hCCCCCCCCEEEEEEEE;
|
`LVX,`SVX:
|
`LVX,`SVX:
|
if (BIG) begin
|
if (BIG) begin
|
usa = a + (c << 2'd3);
|
usa = a + (c << 2'd3);
|
o = {pb[50:0],13'd0} + usa;
|
o = {pb[50:0],BASE_SHIFT} + usa;
|
end
|
end
|
else
|
else
|
o = 64'hCCCCCCCCCCCCCCCC;
|
o = 64'hCCCCCCCCCCCCCCCC;
|
`LVWS,`SVWS:
|
`LVWS,`SVWS:
|
if (BIG) begin
|
if (BIG) begin
|
usa = a + ({c * ven,3'b000});
|
usa = a + ({c * ven,3'b000});
|
o = {pb[50:0],13'd0} + usa;
|
o = {pb[50:0],BASE_SHIFT} + usa;
|
end
|
end
|
else
|
else
|
o = 64'hCCCCCCCCCCCCCCCC;
|
o = 64'hCCCCCCCCCCCCCCCC;
|
default: o = 64'hDEADDEADDEADDEAD;
|
default: o = 64'hDEADDEADDEADDEAD;
|
endcase
|
endcase
|
else
|
else
|
case({instr[31:28],instr[17:16]})
|
case({instr[31:28],instr[17:16]})
|
`PUSH:
|
`PUSH:
|
begin
|
begin
|
usa = a - 4'd8;
|
usa = a - 4'd8;
|
o = {pb[50:0],13'd0} + usa;
|
o = {pb[50:0],BASE_SHIFT} + usa;
|
end
|
end
|
`SBX,`SCX,`SHX,`SWX,`SWCX:
|
`SBX,`SCX,`SHX,`SWX,`SWCX:
|
if (BIG) begin
|
if (BIG) begin
|
usa = a + (c << instr[14:13]);
|
usa = a + (c << instr[14:13]);
|
o = {pb[50:0],13'd0} + usa;
|
o = {pb[50:0],BASE_SHIFT} + usa;
|
end
|
end
|
else
|
else
|
o = 64'hCCCCCCCCEEEEEEEE;
|
o = 64'hCCCCCCCCEEEEEEEE;
|
`SVX: if (BIG) begin
|
`SVX: if (BIG) begin
|
usa = a + (c << 2'd3);
|
usa = a + (c << 2'd3);
|
o = {pb[50:0],13'd0} + usa;
|
o = {pb[50:0],BASE_SHIFT} + usa;
|
end
|
end
|
else
|
else
|
o = 64'hCCCCCCCCCCCCCCCC;
|
o = 64'hCCCCCCCCCCCCCCCC;
|
`SVWS:
|
`SVWS:
|
if (BIG) begin
|
if (BIG) begin
|
usa = a + ({c * ven,3'b000});
|
usa = a + ({c * ven,3'b000});
|
o = {pb[50:0],13'd0} + usa;
|
o = {pb[50:0],BASE_SHIFT} + usa;
|
end
|
end
|
else
|
else
|
o = 64'hCCCCCCCCCCCCCCCC;
|
o = 64'hCCCCCCCCCCCCCCCC;
|
default: o = 64'hDEADDEADDEADDEAD;
|
default: o = 64'hDEADDEADDEADDEAD;
|
endcase
|
endcase
|
| Line 1354... |
Line 1357... |
o = {instr[47:18],instr[12:8],30'd0};
|
o = {instr[47:18],instr[12:8],30'd0};
|
else
|
else
|
o = {{15{instr[31]}},instr[31:18],instr[12:8],30'd0};
|
o = {{15{instr[31]}},instr[31:18],instr[12:8],30'd0};
|
end
|
end
|
`ADDI: o = a + b;
|
`ADDI: o = a + b;
|
|
`SEQI: o = a == b;
|
`SLTI: o = $signed(a) < $signed(b);
|
`SLTI: o = $signed(a) < $signed(b);
|
`SLTUI: o = a < b;
|
`SLTUI: o = a < b;
|
`SGTI: o = $signed(a) > $signed(b);
|
`SGTI: o = $signed(a) > $signed(b);
|
`SGTUI: o = a > b;
|
`SGTUI: o = a > b;
|
`ANDI: o = a & andb;
|
`ANDI: o = a & andb;
|
| Line 1371... |
Line 1375... |
`DIVI: o = BIG ? divq : 64'hCCCCCCCCCCCCCCCC;
|
`DIVI: o = BIG ? divq : 64'hCCCCCCCCCCCCCCCC;
|
`MODI: o = BIG ? rem : 64'hCCCCCCCCCCCCCCCC;
|
`MODI: o = BIG ? rem : 64'hCCCCCCCCCCCCCCCC;
|
`LB,`LBU,`SB:
|
`LB,`LBU,`SB:
|
begin
|
begin
|
usa = a + b;
|
usa = a + b;
|
o = {pb[50:0],13'd0} + usa;
|
o = {pb[50:0],BASE_SHIFT} + usa;
|
end
|
end
|
`Lx,`LxU,`Sx,`LVx,`LVxU:
|
`Lx,`LxU,`Sx,`LVx,`LVxU:
|
begin
|
|
casez(b[2:0])
|
casez(b[2:0])
|
3'b100:
|
3'b100:
|
begin
|
begin
|
usa = a + {b[63:3],3'b0}; // LW / SW
|
usa = a + {b[63:3],3'b0}; // LW / SW
|
o = {pb[50:0],13'd0} + usa;
|
o = {pb[50:0],BASE_SHIFT} + usa;
|
end
|
end
|
3'b?10:
|
3'b?10:
|
begin
|
begin
|
usa = a + {b[63:2],2'b0}; // LH / LHU / SH
|
usa = a + {b[63:2],2'b0}; // LH / LHU / SH
|
o = {pb[50:0],13'd0} + usa;
|
o = {pb[50:0],BASE_SHIFT} + usa;
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
usa = a + {b[63:1],1'b0}; // LC / LCU / SC
|
usa = a + {b[63:1],1'b0}; // LC / LCU / SC
|
o = {pb[50:0],13'd0} + usa;
|
o = {pb[50:0],BASE_SHIFT} + usa;
|
end
|
end
|
endcase
|
endcase
|
|
`PUSHC:
|
|
begin
|
|
usa = a - 4'd8;
|
|
o = {pb[50:0],BASE_SHIFT} + usa;
|
end
|
end
|
`LWR,`SWC,`CAS,`CACHE:
|
`LWR,`SWC,`CAS,`CACHE:
|
begin
|
begin
|
usa = a + b;
|
usa = a + b;
|
o = {pb[50:0],13'd0} + usa;
|
o = {pb[50:0],BASE_SHIFT} + usa;
|
end
|
end
|
`LV,`SV:
|
`LV,`SV:
|
begin
|
begin
|
usa = a + b + {ven,3'b0};
|
usa = a + b + {ven,3'b0};
|
o = {pb[50:0],13'd0} + usa;
|
o = {pb[50:0],BASE_SHIFT} + usa;
|
end
|
end
|
`CSRRW:
|
`CSRRW:
|
case(instr[27:18])
|
case(instr[27:18])
|
10'h044: o = BIG ? (csr | {39'd0,thrd,24'h0}) : 64'hDDDDDDDDDDDDDDDD;
|
10'h044: o = BIG ? (csr | {39'd0,thrd,24'h0}) : 64'hDDDDDDDDDDDDDDDD;
|
default: o = BIG ? csr : 64'hDDDDDDDDDDDDDDDD;
|
default: o = BIG ? csr : 64'hDDDDDDDDDDDDDDDD;
|
| Line 1567... |
Line 1574... |
`DIVI: exc <= BIG & excen[4] & divByZero & instr[27] ? `FLT_DBZ : `FLT_NONE;
|
`DIVI: exc <= BIG & excen[4] & divByZero & instr[27] ? `FLT_DBZ : `FLT_NONE;
|
`MODI: exc <= BIG & excen[4] & divByZero & instr[27] ? `FLT_DBZ : `FLT_NONE;
|
`MODI: exc <= BIG & excen[4] & divByZero & instr[27] ? `FLT_DBZ : `FLT_NONE;
|
`CSRRW: exc <= (instr[27:21]==7'b0011011) ? `FLT_SEG : `FLT_NONE;
|
`CSRRW: exc <= (instr[27:21]==7'b0011011) ? `FLT_SEG : `FLT_NONE;
|
`MEMNDX:
|
`MEMNDX:
|
begin
|
begin
|
`ifdef SUPPORT_SEGMENTATION
|
|
if (usa < {lb[50:0],13'h0000} && usa > {ub[50:0],13'h1fff} && dl!=2'b00)
|
|
exc <= (Ra[4:0]==5'd30 || Ra[4:0]==5'd31) ? `FLT_STK : `FLT_SGB;
|
|
else
|
|
`endif
|
|
`ifdef SUPPORT_BBMS
|
`ifdef SUPPORT_BBMS
|
if ((Ra[4:0]==5'd30 || Ra[4:0]==5'd31) && (usa < {sbl[50:0],13'd0} || usa > {sbu[50:0],13'h1FF8}) && dl!=2'b00)
|
if ((Ra[4:0]==5'd30 || Ra[4:0]==5'd31) && (usa < {sbl[50:0],13'd0} || usa > {sbu[50:0],13'h1FF8}) && dl!=2'b00)
|
exc <= `FLT_STK;
|
exc <= `FLT_STK;
|
else if (usa > {sbu[50:0],13'h1FFF} && dl!=2'b00)
|
else if (usa > {sbu[50:0],13'h1FFF} && dl!=2'b00)
|
exc <= `FLT_SGB;
|
exc <= `FLT_SGB;
|
| Line 1600... |
Line 1602... |
else if (instr[7:6]==2'b00) begin
|
else if (instr[7:6]==2'b00) begin
|
if (!instr[31]) begin
|
if (!instr[31]) begin
|
if (BIG) begin
|
if (BIG) begin
|
case({instr[31:28],instr[22:21]})
|
case({instr[31:28],instr[22:21]})
|
`LBX,`LBUX,`LVBX,`LVBUX: exc <= `FLT_NONE;
|
`LBX,`LBUX,`LVBX,`LVBUX: exc <= `FLT_NONE;
|
`LCX,`LCUX,`LVCX,`LVCUX: exc <= |o[ 0] ? `FLT_ALN : `FLT_NONE;
|
`LCX,`LCUX,`LVCX,`LVCUX: exc <= o[ 0] ? `FLT_ALN : `FLT_NONE;
|
`LVHX,`LVHUX,`LHX,`LHUX: exc <= |o[1:0] ? `FLT_ALN : `FLT_NONE;
|
`LVHX,`LVHUX,`LHX,`LHUX: exc <= |o[1:0] ? `FLT_ALN : `FLT_NONE;
|
`LWX,`LVWX,`LWRX,
|
`LWX,`LVWX,`LWRX,
|
`CACHEX,`LVX: exc <= |o[2:0] ? `FLT_ALN : `FLT_NONE;
|
`CACHEX,`LVX: exc <= |o[2:0] ? `FLT_ALN : `FLT_NONE;
|
`LVX,`SVX,`LVWS,`SVWS: exc <= |o[2:0] ? `FLT_ALN : `FLT_NONE;
|
`LVX,`SVX,`LVWS,`SVWS: exc <= |o[2:0] ? `FLT_ALN : `FLT_NONE;
|
default: exc <= `FLT_UNIMP;
|
default: exc <= `FLT_UNIMP;
|
| Line 1616... |
Line 1618... |
else begin
|
else begin
|
if (BIG) begin
|
if (BIG) begin
|
case({instr[31:28],instr[17:16]})
|
case({instr[31:28],instr[17:16]})
|
`PUSH: exc <= |o[2:0] ? `FLT_ALN : `FLT_NONE;
|
`PUSH: exc <= |o[2:0] ? `FLT_ALN : `FLT_NONE;
|
`SBX: exc <= `FLT_NONE;
|
`SBX: exc <= `FLT_NONE;
|
`SCX: exc <= |o[ 0] ? `FLT_ALN : `FLT_NONE;
|
`SCX: exc <= o[ 0] ? `FLT_ALN : `FLT_NONE;
|
`SHX: exc <= |o[1:0] ? `FLT_ALN : `FLT_NONE;
|
`SHX: exc <= |o[1:0] ? `FLT_ALN : `FLT_NONE;
|
`SWX,`SWCX: exc <= |o[2:0] ? `FLT_ALN : `FLT_NONE;
|
`SWX,`SWCX: exc <= |o[2:0] ? `FLT_ALN : `FLT_NONE;
|
`SVX: exc <= |o[2:0] ? `FLT_ALN : `FLT_NONE;
|
`SVX: exc <= |o[2:0] ? `FLT_ALN : `FLT_NONE;
|
`SVWS: exc <= |o[2:0] ? `FLT_ALN : `FLT_NONE;
|
`SVWS: exc <= |o[2:0] ? `FLT_ALN : `FLT_NONE;
|
default: exc <= `FLT_UNIMP;
|
default: exc <= `FLT_UNIMP;
|
| Line 1632... |
Line 1634... |
end
|
end
|
else
|
else
|
exc <= `FLT_UNIMP;
|
exc <= `FLT_UNIMP;
|
end
|
end
|
end
|
end
|
`ifdef SUPPORT_SEGMENTATION
|
|
`LB,`LBU,`SB:
|
|
if (usa < {lb[50:0],13'h0000} && usa > {ub[50:0],13'h1fff} && dl!=2'b00)
|
|
exc <= (Ra[4:0]==5'd30 || Ra[4:0]==5'd31) ? `FLT_STK : `FLT_SGB;
|
|
`endif
|
|
`ifdef SUPPORT_BBMS
|
`ifdef SUPPORT_BBMS
|
`LB,`LBU,`SB:
|
`LB,`LBU,`SB:
|
if ((Ra[4:0]==5'd30 || Ra[4:0]==5'd31) && (usa < {sbl[50:0],13'd0} || usa > {sbu[50:0],13'h1FF8}) && dl!=2'b00)
|
if ((Ra[4:0]==5'd30 || Ra[4:0]==5'd31) && (usa < {sbl[50:0],13'd0} || usa > {sbu[50:0],13'h1FF8}) && dl!=2'b00)
|
exc <= `FLT_STK;
|
exc <= `FLT_STK;
|
else if (usa > {sbu[50:0],13'h1FFF} && dl!=2'b00)
|
else if (usa > {sbu[50:0],13'h1FFF} && dl!=2'b00)
|
| Line 1652... |
Line 1649... |
else if (usa < {ro[50:0],13'd0} && store && dl!=2'b00)
|
else if (usa < {ro[50:0],13'd0} && store && dl!=2'b00)
|
exc <= `FLT_WRV;
|
exc <= `FLT_WRV;
|
`endif
|
`endif
|
`Lx,`Sx,`LxU,`LVx,`LVxU:
|
`Lx,`Sx,`LxU,`LVx,`LVxU:
|
begin
|
begin
|
`ifdef SUPPORT_SEGMENTATION
|
|
if (usa < {lb[50:0],13'h0000} && usa > {ub[50:0],13'h1fff} && dl!=2'b00)
|
|
exc <= (Ra[4:0]==5'd30 || Ra[4:0]==5'd31) ? `FLT_STK : `FLT_SGB;
|
|
else
|
|
`endif
|
|
`ifdef SUPPORT_BBMS
|
`ifdef SUPPORT_BBMS
|
if ((Ra[4:0]==5'd30 || Ra[4:0]==5'd31) && (usa < {sbl[50:0],13'd0} || usa > {sbu[50:0],13'h1FF8}) && dl!=2'b00)
|
if ((Ra[4:0]==5'd30 || Ra[4:0]==5'd31) && (usa < {sbl[50:0],13'd0} || usa > {sbu[50:0],13'h1FF8}) && dl!=2'b00)
|
exc <= `FLT_STK;
|
exc <= `FLT_STK;
|
else if (usa > {sbu[50:0],13'h1FFF} && dl!=2'b00)
|
else if (usa > {sbu[50:0],13'h1FFF} && dl!=2'b00)
|
exc <= `FLT_SGB;
|
exc <= `FLT_SGB;
|
| Line 1671... |
Line 1663... |
else if (usa < {ro[50:0],13'd0} && store && dl!=2'b00)
|
else if (usa < {ro[50:0],13'd0} && store && dl!=2'b00)
|
exc <= `FLT_WRV;
|
exc <= `FLT_WRV;
|
else
|
else
|
`endif
|
`endif
|
casez(b[2:0])
|
casez(b[2:0])
|
3'b100: exc <= |o[2:0] ? `FLT_ALN : `FLT_NONE; // LW / SW
|
3'b100: exc <= o[2:0]!=3'b0 ? `FLT_NONE : `FLT_NONE; // LW / SW
|
3'b?10: exc <= |o[1:0] ? `FLT_ALN : `FLT_NONE; // LH / LHU / SH
|
3'b?10: exc <= o[1:0]!=2'b0 ? `FLT_ALN : `FLT_NONE; // LH / LHU / SH
|
default: exc <= |o[ 0] ? `FLT_ALN : `FLT_NONE; // LC / LCU / SC
|
default: exc <= o[ 0] ? `FLT_ALN : `FLT_NONE; // LC / LCU / SC
|
endcase
|
endcase
|
end
|
end
|
`LWR,`SWC,`CAS,`CACHE:
|
`LWR,`SWC,`CAS,`CACHE:
|
begin
|
begin
|
`ifdef SUPPORT_SEGMENTATION
|
|
if (usa < {lb[50:0],13'h0000} && usa > {ub[50:0],13'h1fff} && dl!=2'b00)
|
|
exc <= (Ra[4:0]==5'd30 || Ra[4:0]==5'd31) ? `FLT_STK : `FLT_SGB;
|
|
else
|
|
`endif
|
|
`ifdef SUPPORT_BBMS
|
`ifdef SUPPORT_BBMS
|
if ((Ra[4:0]==5'd30 || Ra[4:0]==5'd31) && (usa < {sbl[50:0],13'd0} || usa > {sbu[50:0],13'h1FF8}) && dl!=2'b00)
|
if ((Ra[4:0]==5'd30 || Ra[4:0]==5'd31) && (usa < {sbl[50:0],13'd0} || usa > {sbu[50:0],13'h1FF8}) && dl!=2'b00)
|
exc <= `FLT_STK;
|
exc <= `FLT_STK;
|
else if (usa > {sbu[50:0],13'h1FFF} && dl!=2'b00)
|
else if (usa > {sbu[50:0],13'h1FFF} && dl!=2'b00)
|
exc <= `FLT_SGB;
|
exc <= `FLT_SGB;
|
| Line 1696... |
Line 1683... |
exc <= `FLT_SGB;
|
exc <= `FLT_SGB;
|
else if (usa < {ro[50:0],13'd0} && store && dl!=2'b00)
|
else if (usa < {ro[50:0],13'd0} && store && dl!=2'b00)
|
exc <= `FLT_WRV;
|
exc <= `FLT_WRV;
|
else
|
else
|
`endif
|
`endif
|
exc <= |o[2:0] ? `FLT_ALN : `FLT_NONE;
|
exc <= o[2:0]!=3'b0 ? `FLT_ALN : `FLT_NONE;
|
end
|
end
|
default: exc <= `FLT_NONE;
|
default: exc <= `FLT_NONE;
|
endcase
|
endcase
|
end
|
end
|
|
|
| Line 1710... |
Line 1697... |
begin
|
begin
|
aa <= shfto;
|
aa <= shfto;
|
bb <= c;
|
bb <= c;
|
end
|
end
|
|
|
|
task tskSeq;
|
|
input [47:0] instr;
|
|
input [2:0] sz;
|
|
input [63:0] a;
|
|
input [63:0] b;
|
|
output [63:0] o;
|
|
begin
|
|
`ifdef SIMD
|
|
case(sz[2:0])
|
|
3'd0: o[63:0] = $signed(a[7:0]) == $signed(b[7:0]);
|
|
3'd1: o[63:0] = $signed(a[15:0]) == $signed(b[15:0]);
|
|
3'd2: o[63:0] = $signed(a[31:0]) == $signed(b[31:0]);
|
|
3'd3: o[63:0] = $signed(a) == $signed(b);
|
|
3'd4: o[63:0] = {
|
|
7'h0,$signed(a[7:0]) == $signed(b[7:0]),
|
|
7'h0,$signed(a[15:8]) == $signed(b[15:8]),
|
|
7'h0,$signed(a[23:16]) == $signed(b[23:16]),
|
|
7'h0,$signed(a[31:24]) == $signed(b[31:24]),
|
|
7'h0,$signed(a[39:32]) == $signed(b[39:32]),
|
|
7'h0,$signed(a[47:40]) == $signed(b[47:40]),
|
|
7'h0,$signed(a[55:48]) == $signed(b[55:48]),
|
|
7'h0,$signed(a[63:56]) == $signed(b[63:56])
|
|
};
|
|
3'd5: o[63:0] = {
|
|
15'h0,$signed(a[15:0]) == $signed(b[15:0]),
|
|
15'h0,$signed(a[31:16]) == $signed(b[31:16]),
|
|
15'h0,$signed(a[47:32]) == $signed(b[47:32]),
|
|
15'h0,$signed(a[63:48]) == $signed(b[63:48])
|
|
};
|
|
3'd6: o[63:0] = {
|
|
31'h0,$signed(a[31:0]) == $signed(b[31:0]),
|
|
31'h0,$signed(a[63:32]) == $signed(b[63:32])
|
|
};
|
|
3'd7: o[63:0] = $signed(a[63:0]) == $signed(b[63:0]);
|
|
endcase
|
|
`else
|
|
o = $signed(a) == $signed(b);
|
|
`endif
|
|
end
|
|
endtask
|
|
|
task tskSlt;
|
task tskSlt;
|
input [47:0] instr;
|
input [47:0] instr;
|
input [2:0] sz;
|
input [2:0] sz;
|
input [63:0] a;
|
input [63:0] a;
|
input [63:0] b;
|
input [63:0] b;
|
| Line 1787... |
Line 1815... |
31'h0,$signed(a[63:32]) <= $signed(b[63:32])
|
31'h0,$signed(a[63:32]) <= $signed(b[63:32])
|
};
|
};
|
3'd7: o[63:0] = $signed(a[63:0]) <= $signed(b[63:0]);
|
3'd7: o[63:0] = $signed(a[63:0]) <= $signed(b[63:0]);
|
endcase
|
endcase
|
`else
|
`else
|
o[63:0] = $signed(a[63:0]) <= $signed(b[63:0]);
|
o = $signed(a) <= $signed(b);
|
`endif
|
`endif
|
end
|
end
|
endtask
|
endtask
|
|
|
task tskSltu;
|
task tskSltu;
|
